JP2000305112A - Active matrix substrate and production of active matrix substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease production of point defects in a pixel part in an active matrix substrate having the driving circuit device integrated on the same substrate, to stabilize driving characteristics of the driving circuit device without decreasing the driving ability in the driving circuit device, and to improve the display quality of a liquid crystal display device. SOLUTION: In this production method, a silicon oxide film (SiOx) 56 is uniformly formed to 300 nm thickness on semiconductor layers 26, 27, 28 on a glass substrate 11, then the silicon oxide film (SiOx) 56 in the driving circuit region is processed into a thin film of 140 nm thickness in a photolithographic process. Thus, a gate insulating film 37 having 140 nm thickness in the driving circuit region and having 300 nm film thickness in the display region is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix substrate in a liquid crystal display device using a semiconductor thin film transistor as a switching element and a method for manufacturing the active matrix substrate.

[0002]

Recently, a switching element of a semiconductor thin film transistor, been attempted to develop a high-density large-capacity and high-definition active matrix liquid crystal display device, among others greatly from mobility number 10 and number 100 cm ² / Vs good Because of its excellent semiconductor characteristics, an active matrix substrate using a polysilicon thin film transistor (hereinafter abbreviated as p-SiTFT) using a polysilicon (p-Si) film as a semiconductor layer as a switching element has attracted attention.
Further, in such an active matrix substrate, a driving circuit integrated type active matrix type liquid crystal display device in which a switching element for a pixel electrode and a driving circuit element for transmitting a driving signal to the switching element are provided on the same glass substrate is put into practical use. Is planned.

[0003] In the p-Si TFT, usually, a source region and a drain region are formed by implanting impurities into a p-Si film in a self-aligned manner using a gate electrode as a mask.
A top-gate transistor structure in which a gate electrode is arranged above a channel region with a gate insulating film formed over a semiconductor layer interposed therebetween is employed. In a drive circuit integrated type active matrix type liquid crystal display device including a top gate type p-Si TFT, a gate insulating film of a p-Si TFT conventionally used for a switching element of a pixel electrode and a drive circuit element is used. The film thickness was the same.

[0004]

Conventionally, a p-type pixel formed in an active matrix type liquid crystal display device integrated with a drive circuit is known.
In the -Si TFT, the gate insulating film has the same thickness in both the switching element and the driving circuit element of the pixel electrode.

However, when a p-Si TFT is used as a switching element for a pixel electrode, it is desirable that the thickness of the gate insulating film be large. If the thickness is reduced, the point defects of the pixel portion increase and the display quality deteriorates. . On the other hand, p-
When the SiTFT is used as a drive circuit element, if the thickness of the gate insulating film is large, the on-current of the p-SiTFT is reduced, that is, the drive capability is reduced, and display quality such as ghost is deteriorated. As described above, in the active matrix type liquid crystal display device integrated with the driving circuit, the thickness of the gate insulating film required for the switching element of the pixel electrode and the thickness of the gate insulating film required for the driving circuit element are different. There is a problem that the practical application is hindered due to the conflict.

Accordingly, the present invention has been made to solve the above-described problems, and it is possible to prevent a point defect in a pixel portion of an active matrix type liquid crystal display device integrated with a driving circuit, and to prevent a ghost or the like by preventing a reduction in performance of the driving circuit. It is an object of the present invention to provide an active matrix substrate in a liquid crystal display device having good display quality by obtaining stable driving characteristics without causing display defects.

[0007]

In order to solve the above-mentioned problems, the present invention provides an insulating substrate integrally supporting a display area and a driving circuit area, and the display area and the driving circuit area on the insulating substrate. A semiconductor layer formed having a channel region and a source region and a drain region opposed to each other with the channel region interposed therebetween; a gate insulating film covering the semiconductor layer; and a gate insulating film on the gate insulating film facing the channel region of the semiconductor layer. A thin film transistor comprising a gate electrode arranged in a matrix, and a pixel electrode arranged in a matrix in the display region and connected to a source region of the thin film transistor, wherein the gate insulating film has a thickness of the drive circuit region. The display region is formed to have a larger thickness.

According to the present invention, with the above structure, a gate insulating film having a sufficient thickness is obtained in the pixel portion to prevent the occurrence of a point defect, and in the driving circuit, the gate insulating film is made thinner. An active matrix substrate in a high-quality liquid crystal display device that achieves stable driving characteristics is intended to be put to practical use.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. Reference numeral 10 denotes an active matrix type liquid crystal display device. In a display area, a pixel electrode 11 is provided at an intersection of a plurality of signal lines (not shown) and gate lines (not shown) crossing each other. And an n-type p-Si TFT 12 as a switching element, and in a driving circuit region, a p-type p-S
In a gap between an active matrix substrate 17 having an iTFT 13 and an n-type p-Si TFT 14 and a counter substrate 18,
The liquid crystal composition 22 is sealed via the alignment films 20 and 21.

A display region on a glass substrate 23, which is an insulating substrate of the active matrix substrate 17, has a silicon nitride (SiN) film 24a and a silicon oxide (SiO) film 24.
n-type p-Si through the undercoat layer 24 made of
The semiconductor layer 26 of the TFT 12 is patterned, and the semiconductor layer 27 of the p-type p-Si TFT 13 and the semiconductor layer 2 of the n-type p-Si TFT 14
8 is pattern-formed.

The semiconductor layer 26 includes a channel region 26a and a channel region 26a.
Phosphorus (P) adjacent to the channel region 26a. ⁺) Low concentration of ions
LDD (Lightly Doped)
 Drain) regions 26b, 26c and LDD region 2
6b, 26c and phosphorus (P⁺) Doping ions at high concentration
Source region 26d and drain region 26
e. The semiconductor layer 27 includes a channel region 27
a and boron (B⁺ ) Doping ions at high concentration
Source region 27b and drain region 27c
I have. The semiconductor layer 28 includes a channel region 28a, a channel
Phosphorus (P) adjacent to region 28a⁺) Ion at low concentration
LDD (Lightly Doped Dr)
ain) The regions 28b and 28c, and further the LDD region 28b,
Phosphorus (P⁺) Doping with high concentration of ions
From the source region 28d and the drain region 28e
Made up of

Each of the semiconductor layers 26, 27 and 28 is covered with a gate insulating film 30 made of a silicon oxide (SiO ₂ ) film. The thickness of the gate insulating film 30 in the display region is 3
00 nm, and the film thickness in the drive circuit region is 140 n
m, and the channel regions 26a, 27a,
A gate line made of a single metal such as tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu) or a laminated film or an alloy film thereof is formed on the gate line 28a. Gate electrodes 32, 33, and 34 formed integrally with (not shown) are formed.
Further thereon, an interlayer insulating film 37 made of a silicon oxide film (SiO ₂ ) is formed. On the interlayer insulating film 37, a simple substance such as tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu) or a laminated film or an alloy film thereof is used. In the display area, a source electrode 38 connecting the source area 26d and the pixel electrode 11 is formed,
A drain electrode 40 connected to the drain region 26e and integrally formed with a signal line (not shown) is formed.

On the other hand, interlayer insulating film 37 in the drive circuit region
A single layer of tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), or the like, or a laminated film or an alloy film thereof is formed thereon. Source electrodes 41 and 43 connected to the semiconductor layer 28, a drain electrode 42,
44 are formed. Further, a protective insulating film 46 made of a silicon nitride (SiNx) film and a color filter layer 47 made of an organic resin insulating film are formed thereon, and the pixel electrode 11 is formed on the organic resin insulating film 47 in the display area. Are formed.

On the other hand, in the counter substrate 18, a counter electrode 51 made of ITO is formed on the entire surface of a glass substrate 48, which is an insulating substrate, via an undercoat layer 50. 52 and 53 are polarizing plates.

Next, referring to FIG. 2, an n-type p-Si TFT 12 and a p-type p-SiTF 12 on an active matrix substrate 17 will be described.
The manufacturing process of T13 and n-type p-Si TFT 14 will be described. First, as shown in FIG. 2A, a plasma CVD (chemical vapor depot) is formed on a glass substrate 23.
After forming a silicon nitride (SiN) film 24a and a silicon oxide (SiO) film 24b by a position method,
Amorphous silicon (hereinafter a-Si) is formed by plasma CVD.
Abbreviated. ) Films are laminated and an excimer laser (XeC)
1) to irradiate a-Si to polycrystallize to form a polycrystalline silicon (hereinafter abbreviated as p-Si) film having a thickness of 50 nm, and further, through a photolithography process, to form an n-type p-type film in the display region. Si TFT 12, p-type p-Si in drive circuit area
The semiconductor layers 26, 27 and 28 of the TFT 13 and the n-type p-Si TFT 14 are patterned.

As shown in FIG. 2B, a silicon oxide film (SiOx) 56 is formed on the entire surface by a plasma CVD method.
Is uniformly formed to a thickness of 300 nm. Next, as shown in FIG. 2C, a silicon oxide film (SiOx) in the drive circuit region
56 is thinned to 140 nm by a photolithography process, and a gate insulating film 37 having a thickness of 140 nm in the drive circuit region and 300 nm in the display region is formed. During this photolithography process, the contact holes 56a and 56b in the display area are formed simultaneously.

Next, as shown in FIG. 2D, tantalum (T
a), a metal film 57 made of a simple substance such as chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), or a laminated film or alloy film thereof
Is formed, the source region 2 of the semiconductor layer 27 in the drive circuit region is formed.
In order to perform impurity implantation by ion doping into the drain region 7b and the drain region 27c, the gate electrode 33 is left by a photolithography process and the through hole 57 is formed in the metal film 57.
a and 57b are formed. Further, boron ions (B ⁺ ) are implanted at a high concentration into the source region 27b and the drain region 27c of the semiconductor layer 27 by an ion doping method using the gate electrode 33 as a mask.

Next, as shown in FIG. 2E, a metal film 57 is formed in a pattern by a photolithography process, and a gate electrode 32 is formed in a display region and a gate electrode 34 is formed in a drive circuit region. Subsequently, low concentration phosphorus ions (P ⁺ ) are implanted into the semiconductor layers 26 to 28 by ion doping using the gate electrodes 32 to 34 as a mask.

Next, as shown in FIG.
6, 28 LDD regions 26b, 26c, 28b, 28c
After covering the semiconductor layers 26 to 28 with resists 58, 60, and 61 so that impurities are not implanted into the semiconductor layer 27, phosphorus ions (P ⁺⁾ are added to the source regions 26d, 28d and the drain regions 26e, 28e of the semiconductor layers 26, 28. ) Is injected at a high concentration. At this time, since the thickness of the gate insulating film 37 is different between the display region and the drive circuit region, ion doping may be performed by adjusting the acceleration voltage in two stages.

Next, as shown in FIG. 2 (g), after forming an interlayer insulating film 37 made of silicon oxide (SiO ₂ ) using, for example, a plasma CVD method, the glass substrate 23 is annealed at 500 ° C. for 1 hour. Activate impurities. FIG. 2
As shown in (h), the source region 26 of each of the semiconductor layers 26 to 28 is formed on the interlayer insulating film 37 by a photolithography process.
d, 27b, 28d, drain regions 26e, 27c, 2
After forming a contact hole reaching 8e, tantalum (T
a), a metal film composed of a simple substance such as chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu) or a laminated film or an alloy film thereof, and a photolithography step Source electrode 3
8, 41, 43, and drain electrodes 40, 42, 44 integral with a signal line (not shown) are patterned, and an n-type p-Si TFT 12, a p-type p-Si TFT 13, an n-type p-type Forming the SiTFT 14;

Thereafter, a protective insulating film 46 made of a silicon nitride (SiN _x ) film and an organic resin insulating film 47 are formed on the entire surface of the glass substrate 23 by a plasma CVD method, and then a through hole reaching the source electrode 38 is formed. Then, after forming an ITO film by a sputtering method, the pixel electrode 11 is patterned by a photolithography process to obtain an active matrix substrate 17.

Alignment films 20 and 21 made of a low-temperature curing type polyimide are applied by printing on the entire surface of the active matrix substrate 17 and the counter substrate 18 thus obtained. After the rubbing treatment, the two substrates 17 and 18 are assembled to face each other to form a cell, a liquid crystal composition 22 is injected into a gap therebetween and sealed, and the glass substrates 23 and 48 of the two substrates 17 and 18 are further sealed. The liquid crystal display device 10 is obtained by attaching the polarizing plates 52 and 53 to the sides. When an image was displayed using the liquid crystal display device 10 having such a configuration, a good display quality without any defects or ghosts was obtained.

With this configuration, the same glass substrate 23
The gate insulating film 30 is formed to be as thick as 300 nm in the display region of the active matrix substrate 17 which is a drive circuit integrated type having a p-type p-SiTFT 13 and an n-type p-SiTFT 14 as drive circuit elements thereon. In addition, while suppressing the occurrence of point defects and obtaining good display quality, in the drive circuit area, the gate insulating film 30 is made as thin as 140 nm, so that it is possible to prevent the drive of the drive circuit element from being lowered, and to prevent ghost and the like. Stable drive characteristics without display defects can be obtained, and high-quality display can be obtained.

The present invention is not limited to the above embodiment, and can be changed without departing from the spirit of the present invention. For example, the thickness of the gate insulating film may be different in the display area. It is sufficient that the gate insulating film is thick enough not to cause a drawback and thin enough not to impair the driving function in the drive circuit region. When the film thickness was kept constant at 140 nm and the film thickness of the gate insulating film in the display region was changed, the defect occurrence rate due to point defects was examined.
As is clear from the graph showing the dependency of the defect occurrence rate due to point defects on the thickness of the gate insulating film in the display region, if the thickness t1 of the gate insulating film in the display region is t1 ≧ 250 nm, Is found to be less than 1%, the thickness of the gate insulating film in the display region is t1
≧ (semiconductor film thickness + 200 nm) is desirable.

On the other hand, in the above embodiment, the thickness of the gate insulating film in the display region is kept constant at 300 nm, and the thickness of the gate insulating film in the drive circuit region is changed.
FIG. 4 shows the result of examining the defect occurrence rate caused by the decrease in the driving ability.
As is clear from the graph showing the gate insulating film thickness dependence of the drive circuit region on the failure occurrence rate due to the reduction in the driving capability,
When the thickness t2 of the gate insulating film in the drive circuit region is t2 ≦ 15
If it is 0 nm, the rate of occurrence of defects due to a decrease in driving capability is 1%.
From the following, it is found that the thickness of the gate insulating film in the drive circuit region is t2 ≦ (semiconductor film thickness + 100 nm)
It is desirable that Note that the semiconductor film thickness is not limited to 50 nm.

The method of forming the gate insulating film is also optional.
For example, as in a first modified example shown in FIG. 5, semiconductor layers 73, 74, and 76 are formed on a glass substrate 71 of an active matrix substrate 70 with an undercoat layer 72 interposed therebetween, and plasma CVD is performed as a gate insulating film 77. 140 nm thick silicon oxide film (SiO _x ) 77a
And a silicon nitride film (SiN _x ) 77b having a thickness of 160 nm
When the drive circuit region is thinned after lamination, both films 77a, 7a
Utilizing the difference in the etching rate of 7b, only the silicon nitride film (SiN _x ) 77b in the drive circuit region is etched to have a thickness of 140 nm in the drive circuit region and 300 nm in the display region. A gate insulating film 77 may be formed. By doing so, reproducibility of the thickness of the gate insulating film 77 in the drive circuit region can be easily and satisfactorily secured. In this first modification, the silicon oxide film (S
After the formation of the iO _x ) 77a, the surface may be cleaned and then the silicon nitride film (SiN _x ) 77b may be formed. Although this increases the number of steps for cleaning the surface,
Occurrence of point defects caused by the film-forming particles attached to the surface can be suppressed, and the display quality can be further improved.

Further, in order to reduce the thickness of the gate insulating film in the drive circuit region, a second modification shown in FIG. 6 may be used. First, as shown in FIG. 6A, an undercoat layer 82 on a glass substrate 81 of an active matrix substrate 80 is formed only of a silicon nitride film (SiN _x ), and a semiconductor layer 8 is formed.
After the formation of 3, 84 and 86, a first-layer gate insulating film 87a made of silicon oxide (SiO _x ) having a thickness of 160 nm is formed. Next, as shown in FIG. 6B, the first-layer gate insulating film 8 is formed in the drive circuit region by a photolithography process.
7a is removed by etching. At this time, the contact hole areas 88a and 88b in the display area are also etched away.
Further, as shown in FIG. 6C, a second-layer gate insulating film 87b made of silicon oxide (SiO _x ) having a thickness of 140 nm.
To form a gate insulating film 87 having a thickness of 140 nm in the drive circuit region and a thickness of 300 nm in the display region. By doing so, the undercoat layer 8
Since the selectivity between the gate insulating film 87 and the gate insulating film 87 is high, the first-layer gate insulating film 87a can be etched with high accuracy.
The reproducibility of the thickness of the gate insulating film 87 in the drive circuit region can be easily and satisfactorily secured without increasing the step between the semiconductor layers 83, 84, 86 and the undercoat layer 82.
In the second modification, the first-layer gate insulating film 87a
After formation and surface cleaning, the second-layer gate insulating film 87b
May be formed. In this way, although the number of steps for cleaning the surface increases, it is possible to suppress the occurrence of point defects caused by the film-forming particles attached to the surface, and to further improve the display quality.

Further, the p-Si film may be manufactured by a solid phase growth method instead of laser annealing the a-Si.
Further, an ion implantation + laser activation method may be performed as a method for activating the source region and the drain region of the semiconductor layer. Here, the method of using a laser for forming the p-Si film and activating the source and drain regions is a low-temperature process, so that an inexpensive glass substrate can be used, which is suitable for mass production of a liquid crystal display device. I have.

[0029]

As described above, according to the present invention, the thickness of a gate insulating film of a TFT of a drive circuit integrated type active matrix substrate having drive circuit elements integrally on the same substrate is reduced. In this case, the thickness is made thicker, and in the drive circuit area, it is made thinner, thereby reducing the occurrence of point defects in the pixel portion to obtain a good display and stabilizing the drive characteristics of the drive circuit elements. In addition, it is possible to prevent a display defect due to a reduction in driving capability and to improve display quality.

[Brief description of the drawings]

FIG. 1 is a partial schematic sectional view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic explanatory view showing a manufacturing process of a p-Si TFT on an active matrix substrate according to an embodiment of the present invention; FIG. 2 (a) is an explanatory view showing a state in which a semiconductor layer is patterned on the glass substrate; (B) is an explanatory view showing a state in which a silicon oxide film (SiOx) is uniformly formed on the semiconductor layer oxidation, (c) is an explanatory view showing a state in which the gate insulating film in the drive circuit region is thinned, (D) shows the p-type p-
Explanatory diagram showing a state in which a source region and a drain region are formed in a semiconductor layer of a SiTFT, (e) is an explanatory diagram showing low-concentration ion doping using the gate electrode as a mask,
(F) is an explanatory view showing a state in which a source region and a drain region are formed in the semiconductor layer of the n-type p-Si TFT, and (g).
FIG. 3 is an explanatory view showing the state when the interlayer insulating film is formed, and FIG.

FIG. 3 is a graph showing the dependency of the rate of occurrence of defects due to point defects on the gate insulating film thickness of the display region, as a result of changing the thickness of the gate insulating film in the display region according to the embodiment of the present invention. It is.

FIG. 4 is a graph showing a dependency of a defect occurrence rate due to a reduction in driving capability on a gate insulating film thickness of a driving circuit region, which is a result of changing a thickness of the gate insulating film in the driving circuit region according to the embodiment of the present invention. FIG.

FIG. 5 is a schematic explanatory view showing a state in which gate insulating films having different thicknesses are formed on an active matrix substrate according to a first modification of the present invention.

FIG. 6 is a schematic explanatory view showing a step of forming a gate insulating film on an active matrix substrate according to a second modification of the present invention, and FIG. 6 (a) shows a first layer on a semiconductor layer on the glass substrate; Explanatory drawing showing a state in which a gate insulating film is formed, (b) is an explanatory view showing a state in which a first-layer gate insulating film in a drive circuit region is removed, and (c) is a drawing showing the second-layer gate insulating film. It is explanatory drawing which shows the state which formed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device 11 ... Pixel electrode 12 ... n-type p-SiTFT 13 ... p-type p-SiTFT 14 ... n-type p-SiTFT 17 ... Active matrix substrate 18 ... Counter substrate 22 ... Liquid crystal composition 23 ... Glass substrate 24 ... Undercoat layer 26, 27, 28 Semiconductor layer 30 Gate insulating film 32, 33, 34 Gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 617U F term (Reference) 2H092 GA59 JA35 JB57 KA04 KA07 KA10 KA12 KA18 KB15 KB24 KB25 MA03 MA13 MA17 MA27 MA30 NA13 NA21 5C094 AA42 AA43 AA55 BA03 BA43 CA19 DA09 DA15 EA03 EA04 EA07 GB01 JA08 5F110 AA17 BB01 BB02 BB04 CC02 DD02 DD13 DD14 DD17 DD24 EE02 EE03 EE04 EE06 EE14 FF02 FF03 J03 HL09 GG03 GG02 NN03 NN23 NN24 NN35 NN78 PP03

Claims (7)

[Claims] An insulating substrate integrally supporting a display region and a driving circuit region, a channel region formed in the display region and the driving circuit region on the insulating substrate, and a source opposed to the channel region with the channel region interposed therebetween. A semiconductor layer having a region and a drain region, a gate insulating film covering the semiconductor layer, and a thin film transistor including a gate electrode disposed on the gate insulating film so as to face the channel region of the semiconductor layer; And a pixel electrode arranged in a matrix and connected to the source region of the thin film transistor, wherein the gate insulating film is formed such that the display region is thicker than the drive circuit region. An active matrix substrate. 2. A thin film transistor comprising: a switching element arranged in a display area to drive a pixel electrode; and a driving circuit element arranged in a driving circuit area to supply a display signal to the switching element. The active matrix substrate according to claim 1. A step of patterning a semiconductor layer in each of a display area and a drive circuit area on the insulating substrate;
In a method for manufacturing an active matrix substrate, comprising a step of forming a gate insulating film on the semiconductor layer and a step of forming a gate electrode on the gate insulating film, the step of forming the gate insulating film includes the step of: Forming an insulating film having the same thickness in both the drive circuit region and the drive circuit region, and reducing the thickness of the insulating film in the drive circuit region. 4. The device according to claim 1, wherein the gate insulating film in the display region has a plurality of layers, and the gate insulating film in the drive circuit region has a smaller number of layers than the plurality of layers. Active matrix substrate. 5. The step of forming a gate insulating film includes: forming a first insulating film and a second insulating film having an etching rate different from that of the first insulating film in both the display region and the drive circuit region; 4. The method according to claim 3, further comprising a step of etching and removing the second insulating film. 6. A step of patterning a semiconductor layer in each of a display region and a drive circuit region on an insulating substrate;
In a method for manufacturing an active matrix substrate, comprising a step of forming a gate insulating film on the semiconductor layer and a step of forming a gate electrode on the gate insulating film, the step of forming the gate insulating film includes the step of: Forming a first insulating film in both the driving circuit region, removing the first insulating film in the driving circuit region, and forming a second insulating film in the display region and the driving circuit region. A method for manufacturing an active matrix substrate, comprising: 7. The thickness t of a gate insulating film in a display region
1 is t1 ≧ (semiconductor film thickness + 200 nm), and the film thickness t2 of the gate insulating film in the drive circuit region
3. The active matrix substrate according to claim 1, wherein t2 ≦ (semiconductor film thickness + 100 nm).