JP2000269793A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust simply the signal timing of a semiconductor device. SOLUTION: At the adjustment of a delay, a select signal ϕS is set to 'H' level, when increasing the delay, a reverse signal ϕR is set to 'H' level and when decreasing the delay, the reverse signal ϕR is set to 'L' level. When the reverse signal ϕR is set to 'H' with the select signal ϕS set to 'H' level, a signal outputted from a delay circuit 2 is inverted by inverters 12-14 and NAND elements 15-17 and outputted to a buffer 18. As a result, since signals applied to a signal line 20 which is a dummy signal line and a signal line 21 has a relation of inverted phases to each other, a stray capacitance Cs in existence between them becomes doubled through the mirror effect thereby increasing the delay. Moreover, since the buffer 18 outputs an in-phase signal to the signal on the line 21 is outputted when the reverse signal ϕR is set to 'L' level, the signal lines 20, 21 has signals which are in phase with each other, resulting in that no stray capacitance is equivalently in existence, thereby decreasing the delay.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device including a plurality of semiconductor elements.

[0002]

2. Description of the Related Art In a semiconductor device handling digital signals,
It is important in design to match the timing of signals between the elements.

Conventionally, for example, when adjusting the timing of a signal output from a certain element, the timing is adjusted by inserting a delay circuit at an appropriate place to delay the timing.

FIG. 5 is a diagram showing an example of a conventional timing adjustment method. In this figure, an output of a semiconductor element (such as a logic element) 1 is supplied to a buffer 3 via a delay circuit 2, and the buffer 3 drives a signal line 4. Since the delay circuit 2 has a predetermined delay time τ, the output of the semiconductor element 1 is delayed by the time τ and supplied to the buffer 3.

As described above, by inserting the delay circuit 2 into the output of the semiconductor element 1, it becomes possible to adjust the timing of the signal transmitted through the signal line.

[0006]

The delay time .tau. Of the delay circuit 2 must be determined at the design stage by, for example, simulation to obtain an optimum value.

However, there is a case where the optimum value of the delay time is different from the initial value due to a change in the circuit of another part or a calculation error. In such a case, in order to change the delay time τ of the delay circuit 2, for example, in a semiconductor device manufactured using a plurality of mask patterns, it is necessary to correct all layers of the mask pattern. There was a problem that it is.

The present invention has been made in view of the above points, and has as its object to provide a semiconductor device capable of easily changing signal timing.

[0009]

According to the present invention, in order to solve the above-mentioned problems, in a semiconductor device including a plurality of semiconductor elements, a first signal line and a first signal line are disposed in close proximity to the first signal line. And a signal applied to one end of the first signal line is non-inverted or inverted to form a second signal line.
And a selecting means for selecting non-inverting or inverting operation of the signal inverting means.

[0010] Here, the first signal line is a signal line for transmitting a signal. The second signal line is a dummy signal line, and is arranged close to the first signal line. The signal inversion means non-inverts or inverts the signal applied to one end of the first signal line and applies the signal to the corresponding one end of the second signal line. The selecting means selects non-inverting or inverting operation of the signal inverting means.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram illustrating a configuration example of an embodiment of the present invention. As shown in the figure, the embodiment of the present invention includes semiconductor switches 10 and 11, inverters 12 to 14, NAND elements 15 to 17, buffer 1
8 and 19.

When the select signal φS is “H”, the semiconductor switches 10 and 11 are turned off, while the semiconductor switches 10 and 11 are turned off.
Is turned ON, the signal at the point P1 (the output signal of the delay circuit 2) is input to the inverter 12.

When the select signal φS is at “L”, the semiconductor switch 10 is turned on and the semiconductor switch 11 is turned off, so that the power supply voltage Vcc is input to the inverter 12. Is done.

The select signal is set to "H" when adjusting the delay amount of the output signal of the delay circuit 2, and is set to "L" when no adjustment is performed.
The inverter 12 inverts the output signal from the semiconductor switches 10 and 11 and supplies the inverted signal to the inverter 13 and the input terminal of the NAND element 15.

The inverter 13 further inverts the output signal from the inverter 12 and supplies the inverted signal to the input terminal of the NAND element 16. NAND element 15 obtains the inverted value of the logical product of the output signal of inverter 12 and reverse signal φR to obtain N.
Output to the input terminal of the AND element 17.

The reverse signal φR becomes “H” when increasing the delay amount of the output signal from the delay circuit 2.
The state is set to "L" when the delay amount is reduced.

Inverter 14 inverts reverse signal φR and supplies the inverted signal to the input terminal of NAND element 16. NAN
D element 16 obtains the inverted value of the logical product of the output signal of inverter 13 and the output signal of inverter 14 and outputs the inverted value to the input terminal of NAND element 17.

The NAND element 17 obtains the inverted value of the logical product of the output signal of the NAND element 15 and the output signal of the NAND element 16 and outputs the inverted value to the input terminal of the buffer 18. The buffer 18 is connected to the signal line 2 according to the output of the NAND element 17.
Drive 0.

The buffer 19 drives the signal line 21 according to the output of the delay circuit 2. The signal lines 20, 21
Are signal lines having substantially the same physical shape and arranged in close physical proximity. The signal line 20 is a dummy signal line, and is not connected to other semiconductor elements, output terminals, or the like. The signal line 21 is a signal line for transmitting a signal, and is connected to another semiconductor element (not shown), an output terminal, or the like.

The buffers 18 and 19 both have the same driving capability. When the lengths of the signal lines 20 and 21 are short, the buffers 18 and 19 can be omitted.

Next, the operation of the above embodiment will be described. FIG. 2 shows the embodiment shown in FIG. 1 in which select signal φS is in the “H” state (a setting state in which the amount of delay of the output of delay circuit 2 is adjusted), and reverse signal φR is in the “H” state. 4 (a setting state when the delay amount of the signal on the signal line 21 is increased).

Now, in the setting state as described above,
It is assumed that the delay circuit 2 outputs a signal as shown in FIG. At this time, the select signal φS becomes “H”.
, The semiconductor switch 10 is turned off, while the semiconductor switch 11 is turned on, and the output signal from the delay circuit 2 is supplied to the inverter 12 via the semiconductor switch 11. Become.

The inverter 12 inverts the output signal of the delay circuit 2 and supplies the inverted signal to the inverter 13 and the NAND element 15. FIG. 2B shows how the signal output from the inverter 12 changes over time. As shown in this figure, the output signal from the inverter 12 is obtained by inverting the signal output from the delay circuit 2.

The drive signal φR is “H” as described above.
(See FIG. 2C), the NAND element 1
5 is an output signal of the inverter 12 (see FIG. 2B)
And a reverse signal φR (see FIG. 2C), and outputs a signal (see FIG. 2D) obtained by inverting the result of calculating the logical product.

The inverter 13 inverts the output of the inverter 12 and supplies the inverted output to one input terminal of the NAND element 16. FIG. 2F shows a temporal change of a signal output from the inverter 13. As shown in this figure, the output signal from the inverter 13 is similar to the signal output from the delay circuit 2.

Inverter 14 outputs a signal obtained by inverting reverse signal φR (see FIG. 2E) to NAND element 16. The NAND element 16 inverts the result of calculating the logical product of the output signal of the inverter 13 (see FIG. 2F) and the output signal of the inverter 14 (see FIG. 2E) (FIG. 2G ) Is output.

The NAND element 17 inverts the result of calculating the logical product of the output signal from the NAND element 15 (see FIG. 2D) and the output signal from the NAND element 16 (see FIG. 2G). A signal (see FIG. 2H) is output. As a result, the signal output from NAND element 17 is a signal obtained by inverting the output signal from delay circuit 2.

The buffer 18 drives the signal line 20 according to the output signal from the NAND element 17 (see FIG. 2H). The buffer 19 drives the signal line 21 according to an output signal from the delay circuit 2 (see FIG. 2A).

Therefore, when the select signal φS is set to the “H” state and the reverse signal φR is set to the “H” state, the buffers 18 and 19
Will have a reverse phase relationship.

By the way, the stray capacitance C exists between the signal lines.
s exists. 2 having such a stray capacitance Cs
When signals of opposite phases are applied to the signal lines, the stray capacitance Cs is equivalently doubled to 2 × Cs due to the Miller effect. When the stray capacitance increases, the time required for charging increases, and as a result, the delay amount can be increased.

In this example, as shown in FIG. 2I, the signal at the end point P9 of the signal line 21 has a delay of time t1 compared to the original signal. FIG. 3 shows that in the embodiment shown in FIG. 1, select signal φS is in an “H” state (a setting state in which the delay amount of the output of delay circuit 2 is adjusted), and reverse signal φR is in an “L” state. 4 (a setting state when the signal delay amount on the signal line 21 is reduced).

Assume that a signal as shown in FIG. 3A is output from the delay circuit 2 in the above-described setting state. At this time, since the select signal φS is in the “H” state, the semiconductor switch 10 is turned off, while the semiconductor switch 11 is turned on, and the output signal from the delay circuit 2 is output from the semiconductor switch 11. Through the inverter 12.

The inverter 12 inverts the output signal of the delay circuit 2 and supplies the inverted signal to the inverter 13 and the NAND element 15. FIG. 3B shows a temporal change of a signal output from the inverter 12. As shown in this figure,
The output signal from the inverter 12 is obtained by inverting the signal output from the delay circuit 2.

Drive signal φR is “L” as described above.
(See FIG. 3C), the NAND element 1
5 outputs a signal (see FIG. 3 (D)) obtained by inverting the result of calculating the logical product of the output of the inverter 12 (see FIG. 3 (B)) and the reverse signal φR (see FIG. 3 (C)). I do.

The inverter 13 inverts the output of the inverter 12 and supplies the inverted output to one input terminal of the NAND element 16. FIG. 3F shows a temporal change of a signal output from the inverter 13. As shown in this figure, the output signal from the inverter 13 is the same as the signal output from the delay circuit 2.

Inverter 14 outputs a signal obtained by inverting reverse signal φR (see FIG. 3E) to NAND element 16. The NAND element 16 inverts the signal (FIG. 3G) obtained by calculating the logical product of the output signal of the inverter 13 (see FIG. 3F) and the output signal of the inverter 14 (see FIG. 3E). ) Is output.

The NAND element 17 inverts the result of calculating the logical product of the output signal from the NAND element 15 (see FIG. 3D) and the output signal from the NAND element 16 (see FIG. 3G). A signal (see FIG. 3H) is output. As a result, the signal output from NAND element 17 is similar to the signal output from delay circuit 2.

The buffer 18 drives the signal line 20 according to the output signal from the NAND element 17 (see FIG. 3H). The buffer 19 drives the signal line 21 according to an output signal from the delay circuit 2 (see FIG. 3A).

Therefore, when the select signal φS is set to “H” and the reverse signal φR is set to “L”, the buffers 18 and 19
Will have an in-phase relationship.

When an in-phase signal is applied to the two signal lines having the stray capacitance Cs, the stray capacitance Cs does not exist equivalently (Cs = 0). As a result, the time required to charge the capacitance is reduced, so that the delay amount of the signal transmitted on the signal line 21 can be reduced. In this example, as shown in FIG. 3I, the signal at the end point P9 of the signal line 21 has a delay of time t2 (<t1) as compared with the original signal.

Finally, in the embodiment shown in FIG.
The operation in the case where the select signal φS is in the “L” state (a setting state in which the delay amount of the output of the delay circuit 2 is not adjusted) and the reverse signal φR is in the “L” state will be described.

In FIG. 1, select signal φS is at "L" level.
In this state, the semiconductor switch 10 is turned on and the semiconductor switch 11 is turned off.
Power supply voltage Vcc is applied to the input terminal of inverter 12. As a result, the output of the inverter 12 becomes "L".

Since the output of the inverter 12 is "L", the output of the inverter 13 is "H".
As described above, since the reverse signal φR is in the “L” state and the output of the inverter 12 is in the “L” state, the output of the NAND element 15 is in the “H” state.

Inverter 14 inverts and outputs reverse signal φR, so that one input terminal of NAND element 16 is at “H”. As a result, the NAND element 16
Since "H" is input to the two input terminals, the output thereof becomes "L".

Since the output of NAND element 15 is in the "H" state and the output of NAND element 16 is in the "L" state, the output of NAND element 17 is in the "H" state. The output also becomes "H".

When the output of the buffer 18 is in the "H" state, the signal line 20 is grounded from the viewpoint of AC, so that the signal line 20 can be regarded as a shield of the signal line 21. Therefore, it is possible to prevent noise from being mixed into the signal line 21 from another signal line or element.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted.

In this embodiment, a buffer 30 and a signal line 22 are added as compared with the case of FIG. Other parts are the same as those in FIG. The buffer 30 is connected to the signal line 22 according to the output of the NAND element 17.
Drive.

The signal line 22 is a dummy signal line provided at a position symmetrical to the signal line 20 with the signal line 21 as a center. The signal line 22 has the same physical shape as the signal line 21.

With such a configuration, when a signal having a phase opposite to that of the signal line 21 is applied to the signal lines 20 and 22, the stray capacitance therebetween is 4 × due to the Miller effect. Cs, the delay amount can be further increased as compared with the case of FIG.

Note that the signal lines 20 and 22 are
When a signal having the same phase as that of the signal line 21 is applied, the value of the stray capacitance Cs becomes “0”, so that the delay amount is the same as that in the case of FIG.

As described above, according to the embodiment of the present invention, it is possible to easily change the amount of delay of a signal transmitted through a signal line, so that it is easy to adjust the timing of a semiconductor device. Can be performed.

Further, in a semiconductor device manufactured using a mask pattern, even when the timing needs to be changed due to a circuit change or a design error, the timing can be adjusted without changing the mask pattern. As a result, the manufacturing cost can be reduced, and the design can be easily changed.

In this embodiment, the semiconductor switches 10 and 11, the inverters 12 to 14, the NAND element 15
17 and the buffer 18 are used to configure a circuit, but the present invention is not limited to such a circuit alone, and it goes without saying that there are various modified embodiments.

In the above embodiment, the delay amount is adjusted for the output signal from the delay circuit. However, the present invention is of course applicable to other elements. .

[0056]

As described above, according to the present invention, in a semiconductor device composed of a plurality of semiconductor elements, a first signal line and a second signal line arranged in close proximity to the first signal line are provided.
Signal inverting means for inverting or inverting a signal applied to one end of the first signal line and applying the signal to a corresponding end of the second signal line, and a non-inverting or inverting operation of the signal inverting means Selection means for selecting the delay time, it is possible to easily change the delay amount of the semiconductor device,
As a result, the manufacturing cost of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of an embodiment of the present invention.

FIG. 2 shows the embodiment shown in FIG. 1, in which a select signal φS is at “H” and a reverse signal φR is at “H”;
5 is a timing chart showing a temporal change of a signal of each part of the circuit in the state of FIG.

FIG. 3 shows the embodiment shown in FIG. 1, in which select signal φS is at “H” and reverse signal φR is at “L”.
5 is a timing chart showing a temporal change of a signal of each part of the circuit in the state of FIG.

FIG. 4 is a circuit diagram showing a configuration example according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an example of a conventional timing adjustment method.

[Explanation of symbols]

1 semiconductor element, 2 delay circuit, 3 buffer, 10, 11 semiconductor switch, 12 to 14 inverter, 15 to 17 NAND element, 18, 19,
30 buffer, 20-22 signal line

Claims (4)

[Claims] 1. A semiconductor device including a plurality of semiconductor elements, wherein: a first signal line; a second signal line disposed close to the first signal line; and the first signal line Signal inverting means for inverting or inverting a signal applied to one end of the second signal line and applying the signal to a corresponding end of the second signal line; and selecting means for selecting non-inverting or inverting operation of the signal inverting means. A semiconductor device characterized by the above-mentioned. 2. The apparatus according to claim 1, wherein the selection unit stops the operation of the signal inversion unit as necessary.
13. The semiconductor device according to claim 1. 3. When the operation of the signal inverting means is stopped by the selecting means, the signal inverting means:
3. The semiconductor device according to claim 2, wherein said second signal line is grounded. 4. The semiconductor device according to claim 1, wherein said second signal line is two signal lines arranged close to both sides of said first signal line.