JP2000349606A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flexibly revise a delay time in a delay circuit for timing adjustment with a simple circuit configuration at a low cost after the completion of the product of the title semiconductor integrated circuit device. SOLUTION: A selection signal control section 4 outputs selection signals I1-I4 on the basis of a setting control signal CS received from a prescribed external terminal to turn ON a transistor(TR) provided to a power supply voltage selection supply section 3, which selects an optional voltage from voltages V1-V4 generated by a power supply voltage generating section 5 and supplies the selected voltage as an operating voltage of a signal delay section 2. A delay time of the signal delay section 2 becomes shorter as receiving a higher voltage and longer as receiving a lower voltage. Then even after the completion of the product of the semiconductor integrated circuit device, the delay time of the signal delay section 2 can flexibly and easily be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for adjusting timing of signals in a semiconductor integrated circuit device, and more particularly to a technique effective when applied to adjustment of delay time in operation data, clock signals, and the like.

[0002]

2. Description of the Related Art According to studies made by the present inventor, a semiconductor integrated circuit device such as a microcomputer is provided with a delay circuit. This delay circuit, for example,
It is provided as a timing adjustment for operation data and clock signals between interfaces between the microprocessor and peripheral circuits.

[0003] The delay circuit is composed of, for example, a plurality of inverters, and performs signal delay by connecting the plurality of inverters in series. Further, the delay circuit may not be able to obtain a delay time as designed due to a variation in a manufacturing process or the like. In such a case, it is necessary to readjust the delay time.

In order to change the delay time, a delay circuit provided with a different delay time is provided by a connection of a wiring layer, or a new delay circuit is provided and replaced.

An example of this type of semiconductor integrated circuit device is described in detail in November 30, 1984.
Published by Ohm Co., Ltd., the Institute of Electronics, Communication and Communication Engineers (ed.), “LSI Handbook” P582, which describes a delay circuit in a digital signal processing LSI.

[0006]

However, it has been found by the present inventors that the following problems are encountered with the above-described timing adjustment technology for a semiconductor integrated circuit device.

That is, when connecting delay circuits having different delay times by changing wiring layers, the semiconductor chip area is required as many as the number of delay circuits provided in advance.
There is a problem that it is difficult to reduce the area of the semiconductor chip.

In addition, when a delay circuit is newly provided and replaced, there is a problem in that the cost of mask change and the number of manufacturing steps associated therewith increase.

An object of the present invention is to provide a semiconductor integrated circuit device capable of flexibly changing a delay time in a delay circuit for timing adjustment after completion of a product with a low-cost and simple circuit configuration. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor integrated circuit device according to the present invention comprises a signal delay section for delaying an input signal by a certain time and outputting the same, a power supply voltage generation section for generating two or more different levels of voltage, A delay control unit comprising a power supply voltage selection supply unit that selects a voltage generated by the power supply voltage generation unit based on a selection signal and supplies the voltage as an operation voltage of the signal delay unit.

Further, in the semiconductor integrated circuit device according to the present invention, the delay control means is provided with a selection signal control section for generating a selection signal based on the input setting control signal and outputting the selection signal while holding the selection signal. It is a thing.

Further, according to the semiconductor integrated circuit device of the present invention,
The selection signal control unit comprises one of a buffer and a register.

As described above, the delay control means
Even after the product of the semiconductor integrated circuit device is completed, the delay time of the signal in the signal delay unit can be changed flexibly and easily, and the man-hour and cost in manufacturing the semiconductor integrated circuit device can be reduced. The area of the semiconductor chip can be reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a delay control circuit provided in a semiconductor integrated circuit device according to one embodiment of the present invention, and FIG. 2 is a diagram showing a selection signal and a delay in the delay control circuit according to one embodiment of the present invention. It is explanatory drawing with time.

In this embodiment, a semiconductor integrated circuit device such as a microcomputer is provided with a plurality of delay control circuits (delay control means) 1 as shown in FIG. The delay control circuit 1 adjusts the timing of operation data and clock signals between the interface between the microprocessor and the peripheral circuit. The peripheral circuit is, for example, a timer, a serial communication interface (SCI), or the like.

The delay control circuit 1 comprises a signal delay section 2, a power supply voltage selection supply section 3, a selection signal control section 4, and a power supply voltage generation section 5. The signal delay unit 2 outputs a signal OUT obtained by delaying the input signal IN by a certain delay time.
Output as

The signal delay unit 2 is a P-channel MOS
(Metal Oxide Semiconductor)
r), an inverter 6 including a transistor T1 and an N-channel MOS transistor T2, and an inverter 7 similarly including a P-channel MOS transistor T3 and an N-channel MOS transistor T4.

The signal delay section 2 forms a delay circuit by connecting the inverter 6 and the inverter 7 in series. In the inverter 6, the other connection of the transistor T1 is connected to one connection of the transistor T2, and the other connection of the transistor T2 is connected to the reference potential V _SS.
Is connected.

The gates of the transistors T1 and T2 are connected so as to receive a delayed signal IN.
One connection of the transistor T1 is connected so that the voltage output from the power supply voltage selection supply unit 3 is input.

The gates of the transistors T1 and T2 are
The other connection part of the transistor T1 to which the input part of the inverter 6 is connected and one connection part of the transistor T2 is connected becomes the output part of the inverter 6.

In the inverter 7 of the signal delay unit 2, the gates of the transistors T3 and T4 are connected to each other, and the other connection of the transistor T3 is connected to one connection of the transistor T4.

The connection between the gate of the transistor T3 and the gate of the transistor T4 is the input of the inverter 7, and the other connection of the transistor T3, to which one connection of the transistor T4 is connected, is Output section. The signal OU delayed from this output
T is output.

The reference potential V _SS is connected to the other connection of the transistor T 4, and the voltage output from the power supply voltage selection / supply unit 3 is input to one connection of the transistor T 3. It is connected.

The power supply voltage selection / supply unit 3 selects and outputs voltages (operating voltages) V1 to V4 generated by the power supply voltage generation unit 5 based on the selection signals I1 to I4 of the selection signal control unit 4. The power supply voltage selection / supply unit 3 includes an N-channel M
It is composed of OS transistors 8 to 11.

The gate of the transistor 8 is connected to receive the selection signal I1 output from the selection signal control unit 4. Similarly, the selection signal I2 output from the selection signal control unit 4 is also applied to the gates of the transistors 9 to 11.
To I4 are input.

The other connecting portions of the transistors 8 to 11 are connected to the transistors T1 and T3 in the signal delaying portion 2.
Are connected in common to one of the connection portions, and are supplied as power to the inverters 6 and 7. Transistor 8 ~
11 are connected to input one of various levels of voltages V1 to V4 generated by the power supply voltage generator 5.

Further, as described above, the selection signal control unit 4
Is composed of a buffer or a register, and the input section of the selection signal control section 4 is connected to a predetermined external terminal.

The selection signal controller 4 generates selection signals I1 to I4 based on the setting control signal CS input from an external terminal, and outputs the selection signals I1 to I4 to the gates of the transistors 8 to 11 while holding the selection signals I1 to I4. I do.

The power supply voltage generator 5 generates voltages V1 to V4 having different voltage levels. The power supply voltage generator 5 includes resistors 12 to 16, which are connected in series between a power supply voltage V _CC , which is an operating voltage of the semiconductor integrated circuit device, and a reference potential V _SS. Have been.

A power supply voltage V _CC is supplied to one connection,
The other connection of the resistor 12 whose other connection is connected to the one connection of the resistor 13 is connected to one connection of the transistor 8 in the power supply voltage selection supply unit 3.
Therefore, the voltage V1 divided by the resistor 12 and the combined resistor of the resistors 13 to 16 is supplied to one connection portion of the transistor 8.

Similarly, one connection of the transistor 9 in the power supply voltage selection supply unit 3 is connected to the other connection of the resistor 13 connected to one connection of the resistor 14. Is connected to a resistor 1
The voltage V2 divided by the combined resistance of the resistors 2 and 13 and the combined resistance of the resistors 14 to 16 is supplied.

The other connection of the resistor 14 connected to one connection of the resistor 15 is connected to one connection of the transistor 10 in the power supply voltage selection / supply unit 3.
One connection of the transistor 10 includes resistors 12 to
The voltage V3 divided by the combined resistance of the resistors 14 and 15 and 16 is supplied.

The other connection of the resistor 15 connected to one connection of the resistor 16 is connected to the power supply voltage selection and supply unit 3.
Is connected to one connection of the transistor 11, and a voltage V4 divided by the combined resistance of the resistors 12 to 15 and the resistor 16 is supplied to the one connection of the transistor 11. In this case, the voltage decreases from the voltage V1 to the voltage V4.

Next, the operation of the present embodiment will be described.

First, in the signal delay section 2, the ON timing of the inverters 6 and 7 is advanced as the voltage supplied to one connection section of the transistors T1 and T3 is increased, so that the delay time is shortened. Therefore, when the voltage V1 is supplied to the signal delay unit 2, the delay time becomes shortest, and when the voltage V4 is supplied to the signal delay unit 2, the delay time becomes longest.

When a setting control signal CS is input to the selection signal control unit 4 from a predetermined external terminal, the setting control signal CS
The selection signal control section 4 is based on the
Select signals I1 to I4 for turning on any one of the transistors 8 to 11 in.

At this time, the selection signals I1 to I4 and the delay times t1 to t4 delayed by the signal delay unit 2 are as shown in FIG.
It becomes as shown in. In FIG. 2, when selecting the delay time t1 having the shortest delay time, the selection signal I1 is set to the high level to turn on the transistor 8, and the selection signals I2 to I2 are selected.
Set I4 to low level and turn off transistors 9-11
Let it.

Here, in the present embodiment, the selection signal I1
Although the transistors 8 to 11 are turned ON / OFF by I4, for example, a circuit may be provided such that a multiplexer is provided at the subsequent stage of the selection signal control unit 4 and only the selected transistor is turned ON.

Therefore, the voltage V1 having the highest voltage level is supplied to the inverters 6 and 7, and the time from when the signal IN is input to the signal delay unit 2 to when the signal OUT is output is the longest delay time. Becomes a short delay time t1.

When selecting the delay time t2 longer than the delay time t1, data is input to the selection signal control section 4 from the external terminal by the setting control signal CS, and the selection signal I2 is set to the high level. By turning on the transistor 9, setting the selection signals I 1, I 3, I 4 to low level and turning off the transistors 8, 10, 11, the voltage V 2 lower than the voltage V 1 is applied to the inverters 6, 7.
, And the time from when the signal IN is input to the signal delay unit 2 to when the signal OUT is output is a delay time t2.

Similarly, by turning on one of the transistors 10 and 11, the delay time of the signal delay unit 2 can be changed to the delay times t3 and t4. Therefore,
The signal delay time in the signal delay unit 2 can be arbitrarily changed only by rewriting the data content of the selection signal control unit 4 by the setting control signal CS.

Thus, in the present embodiment, the delay time of the signal in the signal delay unit 2 can be flexibly changed by the delay control circuit 1 even after the product of the semiconductor integrated circuit device is completed. The man-hour and cost in manufacturing a semiconductor integrated circuit device can be reduced.

Further, since a spare delay circuit is not required,
The area of the semiconductor chip can be reduced, and the size of the semiconductor integrated circuit device can be reduced.

Further, according to the present embodiment, the power supply voltage generator 5 is provided for each delay control circuit 1. For example, as shown in FIG. 3, n signal delay units are provided. When 2 _{1 to} 2 _n are provided, one power supply voltage generation unit 5 and n power supply voltage selection supply units 3 ₁ to 3 n are provided.
3 _n , the delay control circuit 1 by one selection signal control unit 4
a may be configured.

[0048] In this case, the voltage generated by a single power supply voltage generation unit 5 is input to the power supply voltage selection supply means 3 ₁ to 3 _n, setting control signal input from the external terminal to the selection signal control section 4 any voltage source voltage selection supply means 3 ₁ to 3 _n are selected on the basis of the CS is to be supplied to the delay control circuit 1. Thereby, the power supply voltage generator 5
Is sufficient, so that the area of the semiconductor chip can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the power supply voltage generator generates four voltages, and the power supply voltage selector supplies one of these voltages to the signal delay unit. By increasing or decreasing the number of resistors in the voltage generator, the voltage level generated by the power supply voltage generator may be five or more or three or less. By setting five or more voltage levels to be generated, the signal delay time can be set more finely.

In the above-described embodiment, the selection signal is generated by inputting data to the selection circuit control unit in accordance with the setting control signal. However, the selection circuit control unit is not provided, and the selection signal is directly provided from a predetermined external terminal. Alternatively, the transistor of the power supply voltage selection unit may be turned on / off.

In this case, by connecting the gate of the transistor in the power supply voltage selection unit so that a signal from an external terminal can be input, the transistor of the power supply voltage selection unit can be ON / OFF controlled.

[0053]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the power supply voltage selection / supply unit selects the voltage generated by the power supply voltage generation unit based on the selection signal and supplies it as the operating voltage of the signal delay unit.
Even after the product of the semiconductor integrated circuit device is completed, the signal delay time in the signal delay unit can be changed flexibly and easily.

(2) In the present invention, according to the above (1), it is not necessary to change the circuit configuration of the delay circuit or to use a spare delay circuit, so that the semiconductor chip can be reduced in area and the semiconductor integrated circuit device can be reduced in size. The manufacturing cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a delay control circuit provided in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a selection signal and a delay time in a delay control circuit according to one embodiment of the present invention.

FIG. 3 is a circuit diagram of a delay control circuit provided in a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

1,1a delay control circuit (delay control means) 2 signal delay unit 2 ₁ to 2 _n signal delay unit 3 supply voltage selection supply means 3 ₁ to 3 _n supply voltage selection supply means 4 selection signal controller 5 supply voltage generator 6 , 7 Inverter 8-11 Transistor 12-16 Resistance T1-T4 Transistor I1-I4 Selection signal V1-V4 Voltage (operating voltage) CS setting control signal

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroyuki Nakane 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems, Ltd. (reference) 5J001 AA04 AA05 BB00 BB12 DD06

Claims (3)

[Claims] 1. A signal delay section for delaying an input signal by a certain time and outputting the same, a power supply voltage generator for generating two or more different levels of voltage, and a voltage generated by the power supply voltage generator. A semiconductor integrated circuit device, comprising: a delay control unit including a power supply voltage selection supply unit that selects based on a selection signal and supplies the power supply voltage as an operation voltage of the signal delay unit. 2. The semiconductor integrated circuit device according to claim 1, wherein the delay control means generates a selection signal based on a setting control signal input thereto and outputs the selection signal while holding the selection signal. A semiconductor integrated circuit device comprising: 3. The semiconductor integrated circuit device according to claim 2, wherein said selection signal control unit is one of a buffer and a register.