JP2007124582A - Delay detection circuit, synchronizing detection circuit, radio reception apparatus and radio transmission apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a circuit that can be made into one chip even in an architecture for handling high-speed transmission and is capable of controlling a delay amount and a phase suitable for delay detection, and radio communication apparatus using said circuit. <P>SOLUTION: A radio communication apparatus comprises: a distribution means for distributing input signals to a first branch input signal and a second branch input signal; a delay circuit, using a transistor, for delaying a phase of said first branch input signal; and a multiplication means for multiplying said second branch input signal by the phase-delayed first branch input signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a wireless reception device and a wireless transmission device using delay detection or synchronous detection.

In wireless communication systems mounted on mobile devices such as TVs, PCs, and mobile phones,
From conventional audio data, there is an increasing demand for communication of large-capacity data represented by the Internet and moving images. For example, in order to transmit large volumes of data such as moving images in real time, high-speed transmission exceeding 1 Gbps is required, and a wide signal band exceeding 1 GHz is required. In order to provide such a GHz-class wide signal bandwidth, in recent years 60 GHz
Wireless communication systems using millimeter wave bands such as these are drawing attention. In order to provide a wireless communication system with a transmission rate exceeding 1 Gbps to end users, a wireless device configuration in which a transmitter and a receiver can be integrated on a single chip IC is important. To that end, it is essential that the architecture and configuration of the wireless device is simple and suitable for miniaturization, has few external parts, and is easy to mount. In wireless communication using millimeter waves, there are many examples of application of ASK (amplitude shift keying) because of the simplicity of the architecture and the ease of miniaturization in a wireless device. The reason for using ASK for the modulation method is that, on the receiver side, if envelope detection such as square detection is applied,
This is because a local signal is not required and the radio configuration is simplified. However, in consideration of user demands such as expansion of transmission distance and increase in capacity, phase such as PSK (Phase shift keying) and QPSK (Quadrature phase shift keying) that have excellent reception sensitivity characteristics and can be multi-valued. Modulation methods will become more powerful in the future.

Usually, in a high frequency band such as 60 GHz, it is difficult to obtain characteristics of an RF circuit compared to a microwave band, and noise characteristics and distortion characteristics tend to deteriorate. Therefore, it is a matter of course that a simple configuration is required as a wireless device, but an architecture that reduces the influence of deterioration of circuit characteristics is also desired for the architecture. From the above background, in the phase modulation method, DPSK (differential phase-shift keying) with differential coding is used to maintain a simple configuration that eliminates the need for local signals on the receiver side, as with ASK. The delay detection method using the is effective. Since delay detection does not require a local signal on the receiver side, the receiver configuration is simple, the symbol interval decreases as the data rate increases, and the VCO (Voltage Controlled Oscill)
ator) phase noise due to the phase noise can be reduced.

In particular, in the high-speed data transmission exceeding 1 Gbps in the millimeter wave band such as 60 GHz, the effect of mitigating the influence of the VCO phase noise, which has been increased due to the high frequency, can be expected by the delayed detection method.

Delay detection is realized by branching a received signal into two, giving a symbol time T as a delay amount τ to one of the branched received signals, and then multiplying it with the other branched received signal. . As a method of providing this delay amount τ, a method of providing a delay line by a transmission line, a method of forming a delay circuit by an inductor (L) and a capacitor (C), and further described in Patent Document 1 and Patent Document 2. There are methods.
JP-A-6-303261 JP-A-6-104946

The conventional delay detection circuit has the following various problems in high-speed transmission exceeding 1 Gbps such as 60 GHz band millimeter wave transmission.

The delay line by the physical propagation line has a problem that the scale of the receiver configuration becomes large because of the need to ensure the length of the delay line. In order to shorten the propagation path length, there are a method of combining with a varactor diode as a λ / 4 line, and a device to physically switch the transmission path with an FET switch, etc., but even at a transmission rate exceeding 1 Gbps, the delay The line needs to be several centimeters or longer, and it is difficult to construct a receiver with a one-chip IC that is several millimeters square.

The delay line by the LC circuit has a self-resonant frequency of L and C lower than the desired band for millimeter wave bands such as 60 GHz, and cannot provide the characteristics of L and C over a wide band. . Therefore, application as a delay line to a data-modulated broadband signal is difficult.

The delay line using the surface acoustic wave described in Patent Document 1 is difficult to make into a single chip with the circuit of the wireless device, and has to be configured as a wireless device module, which increases the configuration scale. is there. In the case of a high-frequency signal such as a millimeter wave, a propagation loss also appears when the signal interface is transferred within the module, and the reception characteristics deteriorate.

The delay circuit based on digital signal processing after AD conversion described in Patent Document 2 requires high-speed processing at least twice the bit rate based on the sampling theorem, and the high-speed required for signal processing as the data transmission speed increases. There is a problem that the characteristics become extremely severe. Also, since it is necessary to stack received signal waveforms within one symbol time, it is necessary to install a memory, and the receiver scale tends to increase.

In the delay detection, a received signal is branched and one of them is given a symbol time delay, and phase synchronization at the carrier level is required. In any of the above methods, when a fixed delay amount is given to control the phase relationship suitable for delay detection, it is necessary to prepare another phase control means, and there is a problem that the configuration of the receiver becomes large. is there.

In other words, it is difficult to provide such a delay line in a receiver that is required to be simple and small, and further downsizing such that the entire receiver that provides delay detection is integrated in a one-chip IC. There is a problem that cannot be handled.

In view of the above problems, the present invention provides distribution means for distributing an input signal to a first branch input signal and a second branch input signal, a transistor for delaying the phase of the first branch input signal, and the second Multiplication means for multiplying the branch input signal by the first branch input signal delayed in phase;
A delay detection circuit and a wireless communication device are provided.

The present invention also provides a local signal oscillator that oscillates a local signal that is frequency-synchronized with an input signal, a transistor that delays the phase of the local signal, and a multiplication that multiplies the local signal delayed in phase by the input signal. And a synchronous detection circuit and a wireless communication device.

The present invention also relates to a multiplier for transmitting a radio signal using a BPSK (binary phase-shift keying) modulation method, a multiplier that multiplies a baseband signal by a local signal and up-converts the frequency, and the local signal. A wireless communication apparatus comprising: a transistor that delays the phase of the signal; and an adder that adds the local signal delayed in phase to the baseband signal that has been frequency up-converted.

According to the present invention, for example, even in an architecture that handles high-speed transmission exceeding 1 Gbps, the circuit can be made into one chip and can adjust the delay amount and phase suitable for delay detection, and the circuit thereof A wireless communication device using can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram of radio receiver 100 of the present embodiment.

The receiver 100 includes an antenna 1, a bandpass filter 2, a low noise amplifier 3, an interstage amplifier 4, a branching device 5, a delay device 6, a multiplier 7, a lowpass filter 8, a comparator 9, and a reception data processing unit 60.

  The antenna 1 receives the radio signal 50 in which the original information is differentially encoded.

  The band pass filter 2 extracts the signal band by suppressing the interference wave of the radio signal 50.

The signal extracted by the bandpass filter 2 is amplified by the low-noise amplifier 3 and the interstage amplifier 4 to obtain the received signal 51. The interstage amplifier 4 may be constituted by one amplifier as shown in FIG. 1, but may be constituted by connecting a plurality of amplifiers in series as required. The size of the received signal 51 is the following (1)
It can be shown as an equation.

Here, t is time, R ₅₁ (t) is the magnitude of the received signal 51, A (t) is an amplitude component including a fading component, ω is an angular vibration frequency, and θ (t) is differentially encoded. The phase modulation terms are shown. The received signal 51 may be phase modulated or frequency modulated as long as it is differentially encoded, but here it is DPSK (Differential phase-shift keying) using a differential code of phase modulation. Will be described.

The reception signal 51 is branched into a reception signal 52 and a reception signal 53 in the branching unit 5. The received signal 53 is delayed by one symbol time T by the delay device 6 and becomes a delayed received signal 54. The magnitude of the received signal 52 can be expressed as in equation (2). Further, the size of the delayed received signal 54 can be expressed as in equation (3).

Here, R ₁₀₂ (t) is the magnitude of the received signal 52, R ₁₀₄ (t) is the magnitude of the delayed received signal 54, and α is the gain of the receive chain (the received signal branched with respect to the received signal 51 before branching) 52 gain).

The multiplier 7 multiplies the received signal 52 and the delayed received signal 54 given a delay of one symbol time T and outputs the result.

Only the desired band excluding the higher harmonics is extracted from the output of the multiplier 7 by the low-pass filter 8 to obtain the delayed detection signal 55. The delayed detection signal 55 is expressed by equation (4).

Here, R ₅₅ (t) is the magnitude of the delayed detection signal 55, and k is the gain of the reception chain and the reception signal 52.
Is a coefficient depending on the power of A (t) and A (tT). Further, the angular vibration frequency ω and the symbol time T are set so that ωT takes 2nπ (n is an integer value), and can be omitted in the equation (4). Assuming that the fading fluctuation is gentle compared to the symbol time and the amplification in the interstage amplifier 4 amplifies the received signal 52 to a region close to the saturation level, k can be regarded as a constant.

The delay detection signal 55 takes a value from + k to −k according to cos [θ (t) −θ (tT)], but the comparator 9 determines whether the digital information is “0” or “1”. The In the comparator 9,
If necessary, equivalent amplification (Reamplifying), waveform shaping (Reshaping), time jitter suppression (Ret
iming) may also be performed. The reception data processing unit 60 converts a digital signal obtained by being judged as “0” or “1” by the converter 9 into original information, for example, converts it into sound, and performs various application processes.

  FIG. 2 is a block diagram of the delay circuit 6 using transistors.

The reception signal 53 is input to the base terminal of the transistor 11 through the capacitor 10 for AC coupling.

The emitter terminal of the transistor 11 is grounded via the resistor 18. The base terminal is connected to the capacitor 10 and the resistors 13 and 14. Resistor 1 at base terminal
3 is connected to the bias power supply 12. The base terminal is grounded via the resistor 14. With this connection, the bias condition of the base terminal is determined. Here, the configuration is such that the bias condition is adjusted by changing the voltage of the bias power supply 12 in this way, but other circuit configurations may be used as long as the bias condition can be varied.

The collector terminal of the transistor 11 is connected to the V _CC power supply 15 via a resistor 17. Further, the delayed received signal 54 is output via the capacitor 16 connected to the received signal 53 collector terminal.

In FIG. 2, the input side load and the output side load are omitted for simplification of description, but the reception signal 53 may be input to the capacitor 10 via the input side load, for example. . Further, the delay reception signal 54 may be output from the capacitor 16 via the output side load.

Here, the delayed reception signal 54 is transmitted from the reception signal 53 by the transistor 11 to the group delay τ.
Will suffer. Further, the phase of the delayed reception signal 54 is characterized by rotating according to the bias condition determined by the bias power supply 12 applied to the transistor 11. Therefore, the delayed received signal 54 can be expressed as in equation (5).

Here, R ₅₄ ′ (t) is the magnitude of the delayed received signal 54, τ is the group delay amount by the transistor 11,
φ _Vbias indicates a phase amount that rotates depending on the bias condition _Vbias of the transistor 11. As ideal conditions for delayed detection, τ = T and φ _Vbias is 2mπ (m is an integer). However, the group delay τ of the transistor 11 may be out of the ideal condition, and the delay detection signal 5
5 can be expressed as in equation (6).

Here, R ₅₅ ′ (t) is the magnitude of the delayed detection signal 55. The received signal 52 is supplied from the interstage amplifier 4
In consideration of the fact that the signal is amplified to near the saturation level and the fluctuation due to the fading is gradual compared to the symbol time, k is considered to take the same numerical value as in the equation (4). The group delay τ can be considered to change according to the bias power supply 12, but the absolute delay time can be considered to be constant because the change can be considered minute. Ωτ in the equation (6) can be expressed as the equation (7).

Here, γ is τ / T. If τ≈T, it can be ignored as ωτ≈2π. If the phase modulation term θ (t) −θ (t−τ) is also τ≈T, the differential code takes a value of 0 or π. Therefore, the bias power source 12 may be adjusted in consideration of the setting of φ _Vbias that is a phase term. The bias power supply 12 is configured so that the amount of phase rotation that the delayed received signal 54 suffers from the transistor 11 is 2 · n · π (n is an integer) or 2 · (n + 1) · π (n is an integer). Set.

In the case of the phase term φ _Vbias = 2 · (n + 1) · π, the sign of the output of the delayed detection signal 55 is inverted with respect to the modulation term θ (t) −θ (tT).

Inversion of the delayed detection signal 55 can be easily supplemented by the following method. For example,
At the start of communication connection, a signal known to the receiver 100 is transmitted from the transmitter side to the receiver 100 side. The receiver 100 can determine whether or not the sign is inverted by comparing the delay detection signal 55 that has been subjected to the delay processing by receiving the known signal and the known signal. When the sign is inverted, it is possible to insert an inverter in the subsequent stage of the comparator 9 on the receiver 100 side and restore it. In the radio communication system, the sign is inverted. However, it can be complemented and does not become a problem.

FIG. 3 shows the characteristics of the phase rotation amount with respect to the bias power source 12 in the transistor 11. In the graph of FIG. 3, in the circuit using the transistor 11 of FIG. 2, the horizontal axis represents the voltage of the bias power supply 12, and the vertical axis represents the relative phase difference φ _Vbias [degree] ( This shows the phase of the S21 characteristic. However, the group delay amount generated in the transistor 11 is excluded as known here. FIG. 3 is a phase characteristic in a predetermined frequency band when Vbia = 5 V and Vbias is varied from 0 to 5.0 V using the 2SC type transistor in the circuit configuration of FIG. In the transistor 11, the current condition on the base side changes depending on the bias voltage V _Vbias , and the value of capacitive coupling between the input and output of the transistor 11 (emitter-base, base-collector, collector-emitter) varies. As a result, the amount of phase rotation changes. The circuit of FIG. 2 has a configuration of an inverting amplifier, and when the bias power source 12 is sufficiently suppressed as compared with V _CC and the transistor is in the On state, the phase rotation amount is π (18
However, in the area where the bias power supply 12 is near the threshold of the transistor 11 (the bias power supply 12 is not much smaller than V _CC ), the phase rotation amount fluctuates exponentially. . Such a phase change depends on the relationship between the transistor used and the frequency of the transmitted signal. Generally, the phase is greatly rotated when the operation state of the transistor is switched depending on the current flowing through the base or the applied voltage. The principle characteristic of the phase change of the transistor 11 is used for phase adjustment of the delay circuit 6. In the circuit configuration of FIG. 2, since the delayed reception signal 54 is output from the collector side, the inverting amplification type is used. However, the delayed reception signal 54 may be output from the emitter side to be a non-inverting amplification type. Transistors can be either bipolar or FET type, NPN, PNP, NMOS, PMO
The polarity of S may be selected according to the circuit configuration and process.

Using the circuit configuration shown in FIG. 2, the bias voltage V _Vbi is used as the voltage output from the bias power supply 12.
_When adjusting the phase amount φ _Vbias by setting _as , a setting target for the bias voltage V _Vbias is required. In FIG. 4, a circuit configuration for adjusting the phase amount φ _Vbias is shown, and the circuit operation will be described.

FIG. 4 is a diagram showing a configuration in which a control circuit for the bias voltage V _Vbias composed of the branching device 43, the level detector 40, the differentiator 41, and the loop filter 42 is added to the block diagram of FIG. The branching device 43 branches a part of the delayed detection signal 55 in FIG. 1 to the control circuit side.

The delayed detection signal 55 is detected by the level detector 40 at the signal amplitude level. The level detector 40 can be realized, for example, by a combination of a diode 44 and a capacitor 45 as shown in FIGS.

In FIG. 9, the delayed detection signal 55 is input to the diode 44 in the forward direction, and the negative component is cut. The output end of the diode 44 is connected to a capacitor 45 having one end grounded via a resistor 46.
Is connected to the other end. An amplitude level output 56 is taken out from the other end of the capacitor 45.

In FIG. 10, the diode 144 is grounded in the reverse direction from one end of the resistor 146. One end of the capacitor 145 is connected to the other end of the resistor 146, and the other end is grounded. Resistance 1
A delay detection signal 55 is input from one end of 46, and an amplitude level output 56 is extracted from the other end.

The signal amplitude level output 56 becomes a periodic function depending on the phase term φ _Vbias as shown in (a) of FIG. If the phase term φ _Vbias is 0 or π, the delayed received signal 54, which is a delayed detection output, takes the maximum amplitude. Conversely, if the phase term φ _Vbias is ± π / 2, the received signal 52 and the received signal 53 are orthogonal, and the output level is zero in principle. The bias power supply 12 in the delay circuit 6 may be adjusted so that the output level becomes maximum in the graph of (a). In FIG. 4, the signal amplitude level output 56 is changed to the differentiation circuit 2.
Differentiation is performed once at 0, and the relationship between the phase term φ _Vbias and the loop filter output 57 shown in FIG. Here, it becomes possible to control the bias voltage V _Vbias by using the zero-cross point indicated by a circle in FIG. 4B. If the loop filter output 57 outputs a positive numerical value, the bias voltage V _Vbias is increased to increase the phase term φ _Vbias . Conversely, if the loop filter output 57 outputs a negative numerical value, the bias voltage V _Vbias increases. The voltage V _Vbias may be decreased to delay the phase term φ _Vbias . Since the transistor 11 is represented as an NPN type in FIG. 2, the increase / decrease relationship between the bias voltage V _Vbias and the phase term φ _Vbias has been described above.
Needless to say, if the P-type polarity is used, the relationship is reversed.

The loop filter output 57 may be directly applied as a bias voltage supplied from the bias power supply 12. Alternatively, a design is made such that a predetermined reference voltage is added to or subtracted from the loop filter output 57 and supplied to the delay circuit 6 as the bias power source 12.
The bias power supply 12 may supply a bias voltage depending on the loop filter output 57.

Depending on the phase term φ _Vbias , the sign of the delayed received signal 54 may be inverted, but it is possible to reverse the inversion by digital signal processing using known information at the start of wireless communication connection. . In FIG. 4, the branched delayed detection signal 55 may be input to the differentiation circuit 41 without passing through the level detector 40. In that case, similarly, as a known signal, information in which the code is fixed to one of them as one continuous is output from the transmitter, and this is received as a radio signal 50 to receive the delayed detection signal 55. It is good to generate.

In the circuit configuration shown in FIG. 2, if stable delay detection is possible using only the group delay of the transistors (that is, if dynamic adjustment of the phase term φ _Vbias is unnecessary), the bias voltage V
_Vbias may be fixed and phase control may not be performed. Further, in the control of the phase term phi _Vbias from the bias voltage V _Vbias, it will also vary the gain characteristic due to the transistor 11. With respect to gain fluctuations, delays can be achieved by inserting gain compensation amplifiers before or after the circuit of FIG. 2 to compensate for gains, or by inserting limiters that amplify to saturation levels. A combination with means for stabilizing the intensity of the delayed delayed received signal 54 is also conceivable.

  In the control circuit of FIG. 4, several operation methods can be considered.

If the configuration is such that the pass band of the loop filter 42 is sufficiently wide compared to the data rate, while receiving a known signal (for example, a preamble) sent from the transmitter side when starting communication connection. When the bias voltage V _Vbias is set and the data signal is received after receiving the known signal, the bias voltage V _Vbias is fixed to the value set by the known signal so that the phase term φ _Vbias does not move. .

If the band of the loop filter 42 is sufficiently narrower than the data rate and the portion of the delayed detection signal 55 represented by the bit-series data series is not used for adjustment of the bias voltage V _Vbias , the level detection circuit 19 and bypass voltage V _Vbias in the following way
Set.

The delayed detection signal 55 is input to the loop filter 42 without passing through the level detection circuit 19. In this case, the signal input to the loop filter 42 takes both positive and negative values as voltage values. In that case, if the number of -1 data and the number of +1 data in the portion of the delayed detection signal 55 represented by the bit-unit data series is the same, the average of the data in that portion will be zero. . That is, no matter how large the absolute value of the voltage value of the delayed detection signal 55 corresponding to -1 data or +1 data is, the value passing through the loop filter 42 does not become so large.

In order to avoid this, in the transmitter that transmits the radio signal 50 received by the radio receiver 100, the differential encoding θ (t
) -θ (t-τ), data 0 (θ (t) -θ (t-τ) = -π) and 1 (θ (t) -θ (t-τ) = π)
Is set so that the mark rate of “1” is high. By adopting such a data series, the average value in the data series becomes a value deviating from 0, so that the output of the loop filter 42 having a narrow band deviates from 0. As a result, since the magnitude of the loop filter output 57 can be determined, as described above, the phase term φ is determined from the relationship between the phase term φ _Vbias and the output level in FIG.
_The bias power supply 12 can be set under the condition of _Vbias = π.

If the transmission information is streaming such as image information, the data information may be framed and a data series in which the mark rate of “1” is increased in the frame header portion. Alternatively, a dummy block having a high mark rate may be inserted into the frame.

Of course, the operation of the control circuit other than the above also controls the bias voltage V _Vbias and the phase term φ
Any configuration may be used as long as _Vbias adjustment is performed and the delayed reception signal 54 has the maximum amplitude level.

(Modification)
Adjusting the conditions of the phase term phi _Vbias from the bias voltage V _Vbias depends on the frequency of the received signal 53 is an input signal to the transistor 11. That is, at high frequencies, the transistor 1
Depending on the capacitive coupling at the input and output of 1, the phase may not be fully rotated and π may not be obtained as the amount of phase rotation. In order to obtain a sufficient amount of phase rotation even when the reception signal 53 is a high frequency, the delay circuit 6 may be configured by connecting the transistors 11 in multiple stages.

FIG. 5 is a circuit diagram as an embodiment of the delay circuit 6 realized by connecting the transistors 11 in three stages.

The reception signal 53 is supplied from the first stage transistor 1 via the capacitor 10 for AC coupling.
1 to the base terminal.

In the first stage transistor 11, the emitter terminal is grounded via a resistor 18. The base terminal is connected to the capacitor 10 and the resistors 13 and 14. A bias power supply 12 is connected to the base terminal via a resistor 13. The base terminal is grounded via the resistor 14. The collector terminal of the transistor 11 is connected to the V _CC power source 1 via the inductor 19.
A V _CC voltage is supplied from a resistor 17 connected to 5. The collector terminal is connected to the base terminal of the second stage transistor 21 via the capacitor 16.

The emitter terminal of the second stage transistor 21 is grounded via a resistor 28. The base terminal is connected to the capacitor 16 and the resistors 23 and 24. A bias voltage is supplied to the base terminal from the resistor 23 connected to the bias power supply 12 via the inductor 29. The base terminal is grounded via the resistor 24. The collector terminal of the transistor 21 is connected to the V _CC power supply 15 via a resistor 27. The collector terminal is connected to the base terminal of the third stage transistor 31 via the capacitor 26.

The third stage transistor 31 has its emitter terminal grounded via a resistor 38. The base terminal is connected to the capacitor 26 and the resistors 33 and 34. A resistor 33 connected to the bias power supply 12 via the inductor 29 and the inductor 39 is connected to the base terminal.
From the above, a bias voltage is supplied. The base terminal is grounded via the resistor 34. The collector terminal of the transistor 31 is supplied with a V _CC voltage from a resistor 37 connected to the V _CC power supply 15 via an inductor 49. In addition, a capacitor 46 connected to the collector terminal
The delayed reception signal 54 is output via

Although V _CC and Vbias are common to each stage, inductors 19, 29, 39, and 49 are inserted between the stages in order to increase the isolation of each stage.

If the amount of phase change is β [radian] at each stage, connecting 3 stages will result in 3 × β [radia
n] is obtained. By using multiple stages, the delayed received signal 54 is amplified with respect to the received signal 53, but even if it is amplified to a region close to saturation,
In the case of binary or quaternary phase modulation or frequency modulation, even if the amplitude component becomes flat, information remains in the phase or frequency component, so there is no problem in the demodulation function. Conversely, by transmitting the reception signal 53 as the delayed reception signal 54 in a region close to the saturation level, the delay detection signal 55 with a stable output level can be obtained. Normally, in the case of FIG. 2 in which one transistor is provided, the inversion amplification is in an ideal state, and the phase rotation amount is up to π [radian]. For delayed detection, the phase rotation amount is 2 × π (ra
dian] is required, and it is desirable to use a multistage connection of two or three stages. If the number of stages of the circuit using the transistor 11 is two or more in consideration of the function of phase adjustment, 2 × π [radian] can be provided.

Although the first embodiment has been described above, the circuits shown in FIGS. 1 to 5 can all be mounted with semiconductor elements. The delay circuit does not require a physical propagation path length as in the prior art, uses the group delay of the transistor, and also adjusts the phase of the delay received signal 54 by changing the conditions of the bias power supply of the transistor. Is possible. Therefore, the circuits of FIGS. 1 to 5 which are the first embodiment of the present invention can be mounted in one chip as an integrated circuit to provide a delay detection function.

(Second Embodiment)
The second embodiment will be described with reference to FIG. In the first embodiment, the configuration for performing the delay detection using the output of the delay device 6 using the transistor has been described. However, the present invention can also be applied to the synchronous detection.

FIG. 6 shows a radio receiver 20 according to the present embodiment in which the present invention is used for a local signal for synchronous detection.
It is a block diagram of 0.

The receiver 200 includes an antenna 201, a bandpass filter 202, a low noise amplifier 203, an interstage amplifier 204, a branching unit 205, a delay unit 206, a multiplier 207, and a low pass filter 208.
A comparator 209, a level detector 240, a differentiator 241, a loop filter 242, a branching device 243, a local signal generator 222, and a synthesizer 223.

Radio signal 25 modulated by binary binary phase-shift keying (BPSK) modulation method
0 is received by the antenna 201. A received signal 251 is obtained from the radio signal 250 through the bandpass filter 202, the low noise amplifier 203, and the interstage amplifier 204.

A part of the reception signal 251 branched by the branching unit 205 is input to a synthesizer 223 for locking (synchronizing) the frequency of the local signal generated by the local signal generator 222. The local signal 258 frequency-synchronized with the received signal 251 is given a group delay by the delay unit 206 and is input to the multiplier 207. The multiplier 207 mixes the reception signal 251 from the branching unit 205 and the local signal 258 to perform synchronous detection. The demodulated signal 259 is obtained through the low-pass filter 208 that extracts the desired band from the received signal subjected to the synchronous detection.

The demodulated signal 259 is determined to be “0” or “1” by the comparator 209.

Here, the demodulated signal 259 can be expressed as in equation (8).

Here, R ₁₀₉ (t) is the size of the demodulated signal 259, and LPF ₈ [...] Is a low-pass filter function for extracting a desired band, that is, a value greater than or equal to the desired band among the solutions obtained by the expression in []. Indicates that the value is restricted. Α is the gain of the receiving chain, A is the amplitude of the radio signal 250, ω is the angular vibration frequency of the radio signal 250, θ (t) is the phase modulation term (0 or π) of the radio signal 250,
φ _Vbias indicates the phase term of the local signal 258.

Since the radio signal 250 is BPSK modulated, if φ _Vbias, which is the phase term of the local signal 258, is nπ (n is an integer) as a relative phase with respect to the received signal 251, it can be demodulated without deteriorating the receiving sensitivity. It becomes.

When the constant n is an odd number, the sign is inverted. However, it can be inverted in the digital signal processing unit subsequent to the comparator 209 using known information.

Therefore, the delay device 206 that delays the phase of the local signal 258 may function so that the level of the demodulated signal 259 is maximized. The control circuit for adjusting the phase of the delay unit 206 is the same as the configuration shown in FIG. 4 and includes a level detector 240, a differentiator 241 and a low-pass filter 242.
Can be configured. That is, the branching device 243 provided in the subsequent stage of the low-pass filter 208.
From this, a part of the demodulated signal 259 is branched and extracted and input to the level detector 240. Then, the phase of the delay unit 206 is adjusted so that the output of the level detector 240 is maximized.

This adjustment method is the same as that described in FIG.

In the present embodiment, a configuration has been described in which a delay of one symbol time is provided for DPSK phase modulation. Depending on the size of the group delay provided by the transistor, a configuration in which a delay of not more than one symbol time but m symbols (m is a real number of 2 or more) is also possible. In that case, the same reception sensitivity as that of demodulation of 1 symbol delay can be obtained by encoding m symbol delay on the transmitter side. Normally, when m of the m symbol delay increases, the influence of fading becomes strong and the correlation between symbols may be weakened. However, 60 GHz
In wireless communication systems using millimeter-wave, it is also a short-range communication, and LOS (Lin
e of Sight) is often the basis, so even if m increases, it is considered that there is no significant effect on reception sensitivity. The setting of the symbol length to be delayed may be determined based on the balance between the transistor to be used, the RF frequency band, and the bit rate.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG.

In the above embodiment, a configuration in which the present invention is applied to a receiver is shown, but in this embodiment, a configuration applied to a transmitter will be described.

Transmitter 300 according to the present embodiment transmits a transmission signal in which a local signal subjected to phase control is superimposed on a modulation signal using BPSK as a modulation scheme. On the receiver side, local signals are not used, and demodulation is performed with a simple configuration such as square detection. With this configuration, since the synthesizer used in the second embodiment is not necessary, there is an advantage of a simple configuration as a wireless communication system including a transmitter and a receiver. In particular, a synthesizer has a great advantage that it can be deleted because it is difficult to mount at a high frequency around 60 GHz such as millimeter waves.

FIG. 7 is a block diagram of a wireless transmitter 300 according to the present embodiment, in which the present invention is used for phase adjustment of a superimposed local signal.

The transmitter 300 includes an antenna 301, a bandpass filter 302, a power amplifier 303, an interstage amplifier 304, a branching unit 305, a delay unit 306, a multiplier 307, and a bandpass filter 30.
8, an adder 309, a level detector 340, a differentiator 341, a loop filter 342, a branching device 343, a local signal generator 322, and a transmission data generation unit 320.

The transmission data generation unit 320 sets the data “0” or “1” as “BPSK transmission data”.
A transmission data signal (baseband signal) 350 encoded to “−1” or “+1” is output.

The transmission data signal 350 is a part of the local signal 358 output from the local signal generator 322 and branched by the branching device 343, and the RF signal 361 mixed in the multiplier 307 and frequency upconverted to a desired RF band. It becomes.

The RF signal 361 has data information in both sidebands, but the bandpass filter 308 extracts only one sideband. However, the band-pass filter 308 can demodulate even if it passes through both sidebands. Here, description will be made assuming that transmission is performed through one sideband. The RF signal 361 is added to the delayed local signal 354 whose phase is controlled by the delay unit 306 in the adder 309 to be a transmission signal 352. The transmission signal 352 can be expressed as in equation (9).

Where T ₃₅₂ (t) is the magnitude of the transmission signal 352, A is the amplitude of the transmission signal 352, θ (t) is the phase modulation term (takes a value of 0 or π), and ω is the angle of the RF band. The oscillation frequency, φ _Vbias is a term representing the amount of phase change given by the delay device 306 to the local signal 358, that is, the modulation signal A · cos.
The relative phase with respect to {θ (t)} · cos (ωt) is shown.

The transmission signal 352 is amplified by the interstage amplifier 304 and the power amplifier 303, passes through the band-pass filter 302, and is transmitted as a radio signal 351 from the antenna 301. Here, the distributor 305 is inserted after the adder 309, a part of the transmission signal 352 is input to the phase control circuit, and the phase amount given to the local signal 358 by the delay unit 306 (that is, the phase in the equation (9)). Adjust the term φ _Vbias ). This phase control circuit has the same configuration as that shown in FIG. 4, and can be configured with a level detector 340, a differentiator 341, and a low-pass filter 342. The control circuit inputs a part of the transmission signal 352 to the level detector 340, and controls the phase of the delay circuit 306 so that the output of the level detector 340 is maximized. Since the control function is described in the description of FIG. If the level detector 340 is configured to perform envelope detection as shown in FIGS. 9 and 10, for example, the amplitude level output 356, which is the output of the level detector 340, can be expressed as in equation (10).

Here, T ₃₅₆ ′ (t) is the amplitude level output 356. In order to maximize the amplitude level output 356, the phase term φ _Vbias is preferably nπ (n is an integer).

An example of the configuration of the receiver 400 that receives the wireless signal 351 from the transmitter 300 described above will be described with reference to FIG. The receiver 400 includes an antenna 401 and a bandpass filter 40.
2, low noise amplifier 403, interstage amplifier 404, level detector 440, low pass filter 4
08 and a comparator 409.

A radio signal 351 transmitted from the transmitter 300 and received by the antenna 401 is input as a received signal 451 to the level detector 440 via the pan-pass filter 402, the low noise amplifier 403, and the interstage amplifier 404. The level detector 440 may have the same configuration as the level detector 340 in FIG. Only the desired band of the amplitude level output 456, which is the output of the level detector 440, is extracted by the low-pass filter 8, and the detection signal 455 is expressed by Equation (10).
Is equivalent (ie, substantially similar) to the output of the level detector 340 described in the above. Therefore, it is desirable to adjust the phase term φ _Vbias so that the level of the detection signal 455 is maximized,
If the relationship of the phase term φ _Vbias = nπ (n is an integer) can be ensured, it is possible to perform demodulation without deteriorating reception sensitivity.

The detection signal 455 is demodulated into a digital signal of data “0” or “1” by the comparator 409 as in the first embodiment. When the constant n is an odd number, the sign is inverted, but this can be easily inverted in the digital signal processing unit after the comparator 409 using known information.

The local signal generator 322 may lock the frequency with respect to the received signal 451,
Even if it is not locked, there is no problem with the communication function and the synthesizer can be omitted. That is, in this embodiment, there is an advantage that a synthesizer is not necessary on the transmitter side and the receiver side, and a synthesizer is not necessary, and a local signal is not necessary on the receiver side. . Moreover, since these transmitters and receivers can all be composed of semiconductor elements, there is an advantage that integration into a one-chip IC is easy.

Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. For example, as already mentioned, it is needless to say that transistors having different polarities can be used. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

The block diagram of the receiver in 1st Embodiment. FIG. 3 is a block diagram of a delay circuit in the first embodiment. The diagram which shows the characteristic of the amount of phase rotations with respect to the bias power supply of the transistor in 1st Embodiment. The block diagram of the control circuit of the bias power supply in 1st Embodiment. The block diagram of the modification of the delay circuit in 1st Embodiment. The block diagram of the receiver in 2nd Embodiment. The block diagram of the transmitter in 3rd Embodiment. The block diagram of the receiver in 3rd Embodiment. The circuit diagram of an example of the level detector in a 1st embodiment. The circuit diagram of an example of the detector in a 1st embodiment.

Explanation of symbols

1,201,301,401 ... antenna, 2,202,302,402 ... bandpass filter, 3,203 ...
Low noise amplifier, 4,204,304,404 ... Interstage amplifier, 5,205,305 ... Branch, 6,206,306 ・
..Delayer, 7,207,307 ... Multiplier, 8,208,408 ... Low pass filter, 9,209,409
..Comparator, 10,210,310 ... Capacitor, 11,211,311 ... Transistor, 12,2
12,312 ... Bias power supply, 13,213,313 ... Resistance, 14,214,314 ... Resistance, 15,215,315
... VCC power supply, 16,216,316 ... Capacitor, 17,217,317 ... Resistance, 18,218,318 ...
・ Resistance 19,219,319 ・ ・ ・ Inductor 20 ・ ・ ・ Capacitor 21 ・ ・ ・ Transistor 23
... Resistance, 24 ... Resistance, 26 ... Capacitor, 27 ... Resistance, 28 ... Resistance, 29 ...
Inductor, 30 ... capacitor, 31 ... transistor, 33 ... resistor, 34 ... resistor, 36 ... capacitor, 37 ... resistor, 38 ... resistor, 39 ... inductor , 40,240,3
40,440 ... level detector, 41,241,341 ... differentiator, 42,242 ... loop filter, 43
, 243,343 ... Branch, 44,144 ... Diode, 45,145 ... Capacitor, 46,146
・ Resistance, 50,250,351 ... Radio signal, 51,251,451 ... Received signal, 52 ... Received signal, 53
... Received signal, 54 ... Delayed received signal, 55 ... Delayed detection signal, 56,256,356,456 ...
Amplitude level output, 57,257 ... Loop filter output, 58,258,358 ... Local signal,
59,259 ... demodulated signal, 60,460 ... received data processing unit, 100, 200, 300, 400 ... receiver, 222322 ... local signal generator, 223 ... synthesizer, 303 ... power amplifier,
308 ... Band pass filter, 309 ... Adder, 320 ... Transmission data generator, 350 ...
・ Transmission data, 352 ... Transmission signal, 354 ... Delayed local signal, 361 ... RF signal, 45
5: Detection signal.

Claims (16)

Distributing means for distributing the input signal to the first branch input signal and the second branch input signal;
A transistor for delaying the phase of the first branch input signal;
Multiplying means for multiplying the second branch input signal by the first branch input signal delayed in phase;
A delay detection circuit comprising: 2. The delay detection circuit according to claim 1, further comprising bias voltage applying means for controlling an amount of delaying the phase of the first branch input signal by controlling a bias voltage applied to the transistor. 2. The delay detection circuit according to claim 1, wherein the bias voltage applying means increases an amount of delay of the phase of the first branch input signal by increasing an absolute value of a bias applied to the transistor. . The transistor is a bipolar type,
2. The delay detection circuit according to claim 1, further comprising bias voltage applying means for applying a bias voltage to a base terminal of the transistor to which the first branch input signal is input. 5. The delay detection circuit according to claim 4, wherein an emitter terminal of the transistor is grounded, and the first branch input signal having a phase delayed from the collector terminal of the transistor is obtained. The transistor is a FET type,
2. The delay detection circuit according to claim 1, further comprising bias voltage applying means for applying a bias voltage to a source terminal of the transistor to which the first branch input signal is input. The gate terminal of the transistor is grounded and the first phase is delayed from the drain terminal.
7. The delay detection circuit according to claim 6, wherein a branch input signal is obtained. The delay detection circuit according to claim 1, further comprising: another transistor that delays a phase of the first branch input signal whose phase is delayed. A level detector for detecting an amplitude level of the second branch input signal multiplied by the first branch input signal delayed in phase;
A differentiator for differentiating the amplitude level,
The delay detection circuit according to claim 1, wherein a bias voltage of the transistor is controlled based on an output of the differentiator. A differentiator for differentiating the second branch input signal multiplied by the first branch input signal delayed in phase;
The delay detection circuit according to claim 1, wherein a bias voltage of the transistor is controlled based on an output of the differentiator. A receiver for receiving a radio signal;
Distributing means for distributing the output signal of the receiver to a first branch input signal and a second branch input signal;
A transistor for delaying the phase of the first branch input signal;
Multiplying means for multiplying the second branch input signal by the first branch input signal delayed in phase;
Conversion means for converting the output of the multiplication means into a digital signal;
A digital signal processing unit that digitally processes the digital signal and outputs an information signal;
A radio receiving apparatus comprising: A local signal oscillator that oscillates a local signal that is frequency-synchronized with the input signal;
A transistor for delaying the phase of the local signal;
Multiplying means for multiplying the input signal by the local signal delayed in phase;
A synchronous detection circuit comprising: A level detector for detecting an amplitude level of the input signal multiplied by the local signal delayed in phase;
A differentiator for differentiating the amplitude level,
13. The synchronous detection circuit according to claim 12, wherein a bias voltage of the transistor is controlled based on an output of the differentiator. A differentiator for differentiating the input signal multiplied by the local input signal delayed in phase,
13. The synchronous detection circuit according to claim 12, wherein a bias voltage of the transistor is controlled based on an output of the differentiator. A receiver for receiving a radio signal;
A local signal oscillator that oscillates a local signal that is frequency-synchronized with the output signal of the receiver;
A transistor for delaying the phase of the local signal;
Multiplication means for multiplying the output signal by the local signal delayed in phase;
Conversion means for converting the output of the multiplication means into a digital signal;
A digital signal processing unit that digitally processes the digital signal and outputs an information signal;
A radio receiving apparatus comprising: In a wireless transmission device that transmits a wireless signal using a modulation method of BPSK (binary phase-shift keying),
A multiplier that multiplies the baseband signal with the local signal to upconvert the frequency;
A transistor for delaying the phase of the local signal;
An adder for adding the local signal delayed in phase to the baseband signal whose frequency is up-converted;
A wireless transmission device comprising:

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