JPH09289439A - Phase adjusting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the phase adjusting circuit which can freely vary a delay time or phase with an instruction signal from a microcomputer. SOLUTION: The phase adjusting circuit includes two couples of transistors(TR) 31 to 34, capacitors 43 and 44, and an inverter. With a trailing edge of the output signal of the inverter, voltages applied to the capacitors 43 and 44 rise until the output signal of the inverter is inverted and with a rising edge of an input pulse voltage signal, the voltages applied to the capacitors 43 and 44 fall until the output signal of the inverter is inverted. The base potentials of the 1st and 3rd TRs are adjusted with 1st and 2nd DC voltages V1 and V2 for control respectively, and consequently the variation rate of the voltages applied to the capacitors 43 and 44 is adjusted. The point in time when the output signal of the inverter is inverted changes. Consequently, the leading edge and trailing edge of the input pulse voltage signal are delayed by a desired delay time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse voltage delay circuit or a phase adjustment circuit for delaying a pulse voltage signal by a predetermined time, and more specifically, a phase adjustment capable of variably controlling the delay time by an external command signal. Regarding the circuit.

[0002]

2. Description of the Related Art An example of a conventional phase adjusting circuit will be described with reference to FIGS. This is a conventional phase adjusting circuit used in a synchronizing signal generating circuit of a video camera, FIG. 3 is a circuit diagram thereof, and FIG. 4 is a time chart showing waveforms of respective parts of the circuit.

A pulse voltage signal V ₁₀₀ having an amplitude of +5 V as shown in FIG. 4A is inputted from an input terminal 100 and inverted by an inverter or inverting circuit 101 as shown in FIG. 4B. The output signal V ₁₀₁ of the inverter 101 is input to the incomplete integration circuits 102, 103, 104 and 105.
This incomplete integration circuit includes two variable resistors 102 and 103.
And a diode 104 and a capacitor 105.

FIG. 4C shows the output voltage V _{105 of the} incomplete integration circuit.
3 shows the waveforms of FIG. The input pulse voltage is delayed by the incomplete integration circuit. Incomplete integration circuit output voltage V ₁₀₅ at the rising of the input voltage signal V ₁₀₁ is gradually increased, the output voltage V ₁₀₅ at the fall of the input voltage signal V ₁₀₁ gradually decreases. When the output voltage of the incomplete integration circuit, that is, the input voltage V ₁₀₅ of the inverter 106 reaches the threshold voltage + 2.5V of the inverter 106, the output voltage V ₁₁₀ of the inverter 106 is inverted.

FIG. 4D shows the output voltage V of the inverter 106.
_{There are 110} waveforms. In this way, the pulse voltage V ₁₀₅ delayed by the incomplete integration circuit is inverted by the inverter 106, waveform-shaped, and output from the output terminal 110.

When the falling edge of the input pulse voltage signal V ₁₀₀ is t ₁ and the falling edge of the output pulse voltage signal V ₁₁₀ is t ₁ ', the delay time is T ₁ =
t ₁ '-t ₁ . The time point of the rising edge of the input pulse voltage signal V ₁₀₀ is t ₂ , and the output pulse voltage signal V _{110 is}
'When the delay time is T ₂ = t _2' of the time of the rising edge t ₂ is a -t _2. These delay times T ₁ ,
T ₂ (seconds) is the resistance value R of the two resistors 102 and 103
₁₀₂ , R ₁₀₃ and the capacitance C _{105 of the} capacitor 105, which is expressed as follows.

[0007]

## EQU1 ## T ₁ = R ₁₀₂ × C ₁₀₅ T ₂ = R ₁₀₃ × C ₁₀₅

Here, R ₁₀₂ and R ₁₀₃ are resistance values (Ω) of the variable resistors ₁₀₂ and ₁₀₃ , respectively, and C ₁₀₅ is a capacitance (F) of the capacitor 105.

The phase adjustment circuit of this example is composed of a variable resistor 10
By changing the resistance values R ₁₀₂ and R ₁₀₃ of 2 and ₁₀₃ , the delay times T ₁ and T ₂ are changed and the phase of the pulse voltage is adjusted.

[0010]

In the conventional pulse voltage delay circuit or phase adjusting circuit, the delay time can be freely changed by changing the resistance value of the variable resistor. It has the advantage of being simple in construction.

However, this delay circuit cannot be connected to a micro computer and the delay time cannot be controlled by a command signal from the micro computer.

In view of the above problems, it is an object of the present invention to provide a pulse voltage delay circuit or a phase adjustment circuit capable of controlling a delay time by a command signal from a micro computer.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a phase adjustment circuit capable of adjusting the phase by a command signal from a micro-computer.

[0014]

According to the present invention, the first,
The second, third and fourth transistors and the first and third
A capacitor connected between a first connection point connecting the collectors of the transistors and a second connection point connecting the collectors of the second and fourth transistors, and a voltage applied to the capacitor is predetermined. A phase inversion circuit that outputs an output pulse voltage signal from the inverter by delaying the falling edge and the rising edge of the input pulse voltage signal when the output pulse voltage signal is inverted. _So that the base potentials V _B32 and V _{B34 thereof} are different from the base potentials V _B31 and V _{B33 of} the first and third transistors, respectively, to the bases of the second and fourth transistors. When different pulse voltage signals, which are obtained by displacing the voltage signals by a predetermined voltage difference, are applied, At the leading edge, the fourth transistor is turned from on to off, the second transistor is turned from on to on, the voltage applied to the capacitor increases until the output signal of the inverter is inverted, and the input pulse voltage signal At the rising edge, the second
The transistor from ON to OFF, the fourth transistor from OFF to ON, and the voltage applied to the capacitor decreases until the output signal of the inverter is inverted,
The base potential V _{B31 of} the first and third transistors,
V _B33 is adjusted by the first and second control DC voltages V ₁ and V ₂ , respectively, whereby the rate of change of the voltage applied to the capacitor is adjusted, the inversion time of the inverter is adjusted, and The falling edge and the rising edge of the input pulse voltage signal are configured to be delayed by a desired delay time.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a pulse voltage delay circuit or a phase adjusting circuit according to the present invention will be described with reference to FIGS. As shown in FIG. 1, in the circuit of this example, when the pulse voltage signal V ₁₀ is input from the input terminal 10, the pulse voltage signal V ₁₁ delayed by a predetermined time is output from the output terminal 11. The delay time is controlled by the control DC voltage signals V ₁ and V ₂ applied to the terminals 13 and 14.

The circuit of this example includes a diode 21, a single inverter 27, and two pairs of transistors 31, 32, 33, and 3.
4 and a capacitor 41. Control DC voltages V ₁ and V ₂ are applied to the bases of the first and third transistors 31 and 33, respectively. The pulse voltage signal V ₁₀ is applied from the input terminal 10 to the bases of the second and fourth transistors 32 and 34. First and third transistor 3
A capacitor 41 is provided between the connection point 35 of the collectors of 1 and 33 and the connection point 36 of the collectors of the second and fourth transistors 32 and 34.

The operation of this circuit will be described with reference to FIG.
2A shows a pulse voltage signal V ₁₀ supplied to the input terminal 10, and FIG. 2B shows a base voltage V 2 of the second transistor 32.
_B32 , FIG. 2C shows the base voltage V of the fourth transistor 34.
_B34 , FIG. 2D is the collector current I _C32 of the second transistor 32, FIG. 2E is the collector current I _C34 of the fourth transistor 34, FIG. 2F is the voltage V _{41 of the} capacitor ₄₁ , and FIG. 2G.
Is the waveform of the output signal V ₁₁ output to the output terminal 11.

At the time t ₁ at the input terminal 10 as shown in FIG. 2A.
Pulse voltage V _{10 which} rises at time t ₂
Enter In this example, the voltage amplitude of the pulse voltage V ₁₀ is + 3V.

As shown in FIG. 2B, the second transistor 3
The waveform of the base voltage V _B32 of 2 is a waveform obtained by direct-current shifting the voltage signal V ₁₀ to the plus side. As shown in FIG. 2C, the waveform of the base voltage V _B34 of the fourth transistor 34 is a waveform obtained by direct-current shifting the voltage signal V ₁₀ to the negative side.

To the base of the second transistor 32, a constant voltage + 7V is applied via the resistor 52, and the voltage signal V ₁₀ is applied via the resistor 53 and the capacitor 43. As a result, the voltage signal V ₁₀ is DC-shifted to the positive side, and + 3V and 0V are + 4.7V, respectively, as shown in FIG. 2B.
And changes to + 3V. At the base of the fourth transistor 34, a constant voltage of −5V and a resistor 54 are connected via a resistor 55.
And the voltage signal V ₁₀ is applied via the capacitor 44. As a result, the voltage signal V ₁₀ is DC-shifted to the negative side, and + 3V and 0V are −, respectively, as shown in FIG. 2C.
It changes to 0.7V and -2.9V.

Input terminal 10 and two transistors 32,
Since two capacitors 43 and 44 are provided between the bases of 34, the waveforms of the base voltages V _B32 and V _B34 are respectively times t ₁ and t ₂ as shown in FIGS. 2B and 2C.
Then, it suddenly falls and rises. If the two capacitors 43 and 44 are not provided, the waveforms of the base voltages V _B32 and V _B34 do not have steep fall and rise at time points t ₁ and t ₂ , respectively, as shown by the broken line. If the slope of this broken line is large enough to fall sharply at time points t ₁ and t ₂ , and rise, the two capacitors 43, 4
It is not necessary to use 4.

On the other hand, the first and third transistors 31,
To the base of 33, constant control DC voltages V ₁ and V ₂ are applied via terminals 13 and 14. However, the base voltage V _B31 of the first transistor 31 is set to be in the range of the base voltage V _B32 of the second transistor 32. Similarly, the base voltage V of the third transistor 33
_B33 is set to be in the range of the base voltage V _B34 of the fourth transistor 34.

[0023]

## EQU00002 ## 3.0V <V _B31 <4.7V -2.9V <V _B33 <-0.7V

For example, as shown, a constant voltage of + 5V is additionally applied to the base of the first transistor 31,
A constant voltage of −5V may be additionally applied to the base of the third transistor 33.

Up to the time t ₁ , the second transistor 32
Is off and the fourth transistor 34 is on. Therefore, although the collector current I _C32 of the second transistor 32 is zero as shown in FIG. 2D, the current I _C34 flows from the capacitor 41 into the collector of the fourth transistor 34 as shown in FIG. The voltage V ₄₁ of the voltage V. However, due to the action of the diode 21, the voltage V _{41 of the} capacitor 41 does not fall below about 0 V (the forward voltage drop of the diode 21 is ignored).

At time t ₁ , on the contrary, the second transistor 32 is turned on and the fourth transistor 34 is turned off. Therefore, as shown in FIGS. 2D and 2E, the current I _C32 flows through the collector of the second transistor 32, and the collector current I _C34 of the fourth transistor 34 becomes zero.

Base voltage V of the first transistor 31
The difference between the base voltage V _B32 of _B31 and the second transistor 32 appears as it is as the difference of the emitter potentials of the first and second transistors 31 and 32, and the emitter current I ₅₁ flows through the resistor 51. The collector current I _C32 of the second transistor 32 is equal to the emitter current I ₅₁ of the second transistor 32, and is calculated by the following equation.

[0028]

## _EQU3 ## I _C32 = (V _B31 −V _B32 ) / R ₅₁ ≈ (V _B31
-3) / R ₅₁

[0029] Here V_B31, V_B32Is the first and second
Base voltage of the transistors 31, 32, R₅₁Is resistor 51
Is the resistance value. Base voltage of the second transistor 32
V_{B3 Two}Is + 3V as shown in FIG. 2B. Second tiger
Collector current I of transistor 32_C32Is the condenser 41
Flowing in, the voltage of the capacitor 41 as shown in FIG. 2F.
V₄₁Rises. Voltage V₄₁The rate of change of is expressed as
You.

[0030]

[Formula 4] dV ₄₁ / dt = I _C32 / C ₄₁

Where C₄₁Is the capacity of the capacitor 41
You. I_C32Is the collector current of the second transistor 32
Yes, it is constant as shown in the equation (3). Therefore
Pressure V ₄₁The rate of change of is constant.

Voltage V of capacitor 41₄₁Rises and the
When the threshold value of the input gate of the converter 27 is exceeded, the inverter
Output signal V of data 27₁₁Is inverted. Of the inverter 27
The power supply voltage of the input gate threshold is + 3V
Therefore, it is about + 1.5V, which is half of that. Shown in Figure 2G
The voltage V of the capacitor 41₄₁Reaches about + 1.5V
Then, the output signal V of the inverter 27₁₁Is inverted. Time point
t₁From the output signal V of the inverter 27₁₁When is reversed
Point t₁’Time to T₁Is the input pulse voltage V _TenStanding
The delay time of the falling edge, which is expressed as follows.

[0033]

[Formula 5] T ₁ = (C ₄₁ / I _C32 ) × 1.5

After that, the voltage V _{41 of the} capacitor 41 further rises, but does not exceed +3 V due to the action of the diode 21.

At time t ₂ , the second transistor 3
2 is turned off, and the fourth transistor 34 is turned on. This is the same as the state until reaching the time point t ₁ described above.

Base voltage V of the second transistor 32
The difference between the base voltage V _B34 of _B32 and the fourth transistor 34 appears as it is as the difference of the emitter potentials of the second and fourth transistors 32 and 34, and the emitter current I ₅₆ flows through the resistor 56. The collector current I _C34 of the fourth transistor 34 is substantially equal to the emitter current I ₅₆ of the fourth transistor 34, and is _calculated by the following equation.

[0037]

## _EQU6 ## I _C34 = (V _B34 −V _B33 ) / R ₅₆ ≈ (−0.
7-V _B33 ) / R ₅₆

[0038] Here V_B33, V_B34Is the third and fourth
Base voltage of the transistors 33 and 34, R₅₆Is a resistor 56
Is the resistance value. Base voltage of the fourth transistor 34
V_{B3 Four}Is approximately -0.7V, as shown in FIG. 2C.

Similar to the above description, the collector current I _C32 of the second transistor 32 becomes zero, and the collector 41 of the fourth transistor 34 receives the current I _C34 from the capacitor 41.
Flows in and the voltage V _{41 of the} capacitor 41 decreases. The rate of change of the voltage V ₄₁ is expressed as follows.

[0040]

[Formula 7] dV ₄₁ / dt = I _C34 / C ₄₁

When the voltage V _{41 of the} capacitor 41 decreases and becomes smaller than the threshold value of the input gate of the inverter 27 of about +1.5 V, the output signal V ₁₁ of the inverter 27 is inverted. However, due to the action of the diode 21, the voltage V _{41 of the} capacitor 41 does not fall below about 0V.

As described above, the threshold value of the input gate of the inverter 27 is about + 1.5V. As shown in FIG. 2G, when the voltage V ₄₁ of the capacitor 41 reaches about +1.5 V, the output signal V ₁₁ of the inverter 27 is inverted. Time t
_2, the time T ₂ of the up time t ₂ 'of the output signal V ₁₁ of inverter 27 is inverted, the delay time of the rising edge of the input pulse voltage V _10, is expressed as follows.

[0043]

[Formula 8] T ₂ = (C ₄₁ / I _C34 ) × 1.5

As is apparent from the equations (5) and (8), the delay time T of the falling edge of the input pulse voltage V is
₁ is determined by the collector current I _C32 of the second transistor 32, and the rising edge delay time T ₂ is determined by the collector current I _C34 of the fourth transistor 34.

That is, when the collector current I _C32 of the second transistor 32 is large, the delay time T _{1 of the} falling edge of the input pulse voltage V is small, and when the collector current I _C32 of the second transistor 32 is small, the input pulse is small. Voltage V
The delay time T _{1 of the} falling edge of is increased. Similarly, when the collector current I _C34 of the fourth transistor 34 is large, the delay time T ₂ of the rising edge of the input pulse voltage V is small, and when the collector current I _C34 of the fourth transistor 42 is small, the input pulse voltage V is small. The rising edge delay time T ₂ increases.

As is clear from the equation (3), the base voltage V _B31 of the first transistor 31 may be increased in order to increase the collector current I _C32 of the second transistor 32. On the contrary, in order to reduce the collector current I _C32 of the second transistor 32, the base voltage V _B31 of the first transistor 31 may be reduced. The base voltage V _B31 of the first transistor 31 is controlled by changing the control DC voltage V ₁ applied to the terminal 13.

As is clear from the equation (6), in order to increase the collector current I _C34 of the fourth transistor 34, the base voltage V _B33 of the third transistor 33 may be increased. On the contrary, in order to reduce the collector current I _C34 of the fourth transistor 34, the base voltage V _B33 of the third transistor 33 may be reduced. The base voltage V _B33 of the third transistor 33 is controlled by changing the control DC voltage V ₂ applied to the terminal 14.

Thus, according to this example, the terminals 13 and 14 are
Controlling DC voltage V applied₁, V _TwoTo control
Therefore, the falling edge and rising edge of the input pulse voltage
Edge edge delay time T₁, T_TwoTo freely change
Can be. DC power for control applied to terminals 13 and 14
Pressure V₁, V_TwoIs the command signal from the microcomputer
It may be.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these examples, and various modifications can be made within the scope of the invention described in the claims. It will be understood by those skilled in the art.

[0050]

According to the present invention, there is an advantage that the delay time of the input pulse voltage signal can be controlled by the command signal from the micro-computer.

According to the present invention, there is an advantage that the phase of the input pulse voltage signal can be adjusted by the command signal from the micro computer.

According to the present invention, there is an advantage that the delay time of the falling edge and the delay time of the rising edge of the input pulse voltage signal can be independently controlled by the command signal from the micro computer.

According to the present invention, since the phase of the pulse voltage signal can be freely adjusted by the command signal from the micro-computer, the phase of the pulse voltage signal can be adjusted remotely through the communication means. It has the advantage that it can. In addition, there is an advantage that there is no deterioration of reliability due to mechanical error and secular change as in the case of using a conventional mechanical variable resistor. Furthermore, it can be combined with an automatic measuring device during production to perform automatic adjustment and reduce man-hours.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a phase adjustment circuit according to the present invention.

FIG. 2 is a diagram showing a time chart of the phase adjustment circuit of the present invention in FIG.

FIG. 3 is a diagram showing an example of a conventional phase adjustment circuit.

FIG. 4 is a diagram showing a time chart of the conventional phase adjustment circuit of FIG.

[Explanation of symbols]

10 input terminals, 11 output terminals, 13, 14 control DC voltage input terminals, 21 diodes, 27 inverters, 31, 32, 33, 34 transistors, 35, 3
6 connection points, 41, 43, 44 capacitors, 51, 5
2,53,54,55,56 resistors

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03L 7/00 H03K 19/00 101N

Claims (3)

[Claims] 1. A first connection point connecting the first, second, third and fourth transistors to the collectors of the first and third transistors and a collector of the second and fourth transistors. Delaying the falling edge and rising edge of the input pulse voltage signal, including a capacitor connected between the second connection points and an inverter that inverts the output when the voltage applied to the capacitor reaches a predetermined value. In the phase adjusting circuit for outputting the output pulse voltage signal from the inverter, the base potential V _{B32 of} the second and fourth transistors,
The input pulse voltage signal is applied to the bases of the second and fourth transistors with a predetermined voltage difference so that V _B34 has a value different from the base potentials V _B31 and V _{B33 of} the first and third transistors, respectively. Different pulse voltage signals displaced by direct current are applied, and at the falling edge of the input pulse voltage signal, the fourth transistor turns from on to off and the second transistor turns from off to on. The voltage applied to the capacitor increases until the output signal is inverted, and at the rising edge of the input pulse voltage signal, the second transistor turns from on to off and the fourth transistor turns from off to on. The voltage applied to the capacitor decreases until the output signal is inverted, and the voltage of the first and third transistors Base potential V _B31 ,
V _B33 is adjusted by the first and second control DC voltages V ₁ and V ₂ , respectively, whereby the rate of change of the voltage applied to the capacitor is adjusted, the inversion time of the inverter is adjusted, and A phase adjustment circuit configured to delay a falling edge and a rising edge of an input pulse voltage signal by a desired delay time. 2. The phase adjustment circuit according to claim 1, wherein
The base potential V _{B31 of} the first and third transistors,
A phase adjusting circuit characterized in that V _B33 is a value within a variation range of the base potentials V _B32 and V _B34 of the second and fourth transistors, respectively. 3. The phase adjusting circuit according to claim 1, wherein a diode is connected to the capacitor, and a voltage applied to the capacitor does not exceed a predetermined value.