JPS5834844Y2 - phase comparison circuit - Google Patents

phase comparison circuit

Info

Publication number
JPS5834844Y2
JPS5834844Y2 JP11149477U JP11149477U JPS5834844Y2 JP S5834844 Y2 JPS5834844 Y2 JP S5834844Y2 JP 11149477 U JP11149477 U JP 11149477U JP 11149477 U JP11149477 U JP 11149477U JP S5834844 Y2 JPS5834844 Y2 JP S5834844Y2
Authority
JP
Japan
Prior art keywords
terminal
differential pair
switching transistor
voltage
base side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11149477U
Other languages
Japanese (ja)
Other versions
JPS5437017U (en
Inventor
教男 今泉
純次 阪本
達広 鈴木
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP11149477U priority Critical patent/JPS5834844Y2/en
Publication of JPS5437017U publication Critical patent/JPS5437017U/ja
Application granted granted Critical
Publication of JPS5834844Y2 publication Critical patent/JPS5834844Y2/en
Expired legal-status Critical Current

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  • Synchronizing For Television (AREA)

Description

【考案の詳細な説明】 本考案は位相比較回路に係り、特に比較用の電圧波形と
して鋸歯状波電圧を用い基準信号と比較して制御電圧を
得る同回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase comparator circuit, and more particularly to the same circuit that uses a sawtooth wave voltage as a voltage waveform for comparison and compares it with a reference signal to obtain a control voltage.

一般にテレビ受像機における自動周波数制御(AFC)
回路の如く、水平発振回路の発振周波数の制御を自動的
に行う場合、単に差動対トランジスタの一方のベースを
分圧抵抗にて分圧した電位に固定し、他方のベースに比
較用鋸歯状波電圧(第3図イ)を加え、上記差動対トラ
ンジスタの共通エミッタに接続したスイッチングトラン
ジスタに基準信号となる水平同期信号(第3図口)を加
え、上記差動対トランジスタのいずれかのトランジスタ
のコレクタより制御用電圧を導出する構成であり、比較
用鋸歯状波電圧の直流レベルVDOにおいて行われ、位
相比較時間は変化できない。
Generally automatic frequency control (AFC) in television receivers
When automatically controlling the oscillation frequency of a horizontal oscillation circuit such as in a circuit, simply fix one base of the differential pair transistor to a potential divided by a voltage dividing resistor, and connect the other base with a sawtooth shape for comparison. wave voltage (Fig. 3 A) is applied, and a horizontal synchronizing signal (Fig. 3 A) serving as a reference signal is applied to the switching transistor connected to the common emitter of the differential pair transistors. The configuration is such that the control voltage is derived from the collector of the transistor, and the comparison is performed at the DC level VDO of the sawtooth wave voltage for comparison, and the phase comparison time cannot be changed.

そこで、本考案は上記位相時間が設計仕様に応じて大小
に変化できる新規な位相比較回路を提供するものである
Therefore, the present invention provides a novel phase comparator circuit in which the phase time can be changed in size depending on design specifications.

次に本考案を図面に従って説明すると、第1図は本考案
の回路の一実施例、第2図は同回路の他の実施例を示し
、先ず第1図について説明する。
Next, the present invention will be explained with reference to the drawings. FIG. 1 shows one embodiment of the circuit of the present invention, and FIG. 2 shows another embodiment of the same circuit. First, FIG. 1 will be explained.

第1図において1は比較用の鋸歯状波電圧が加えられる
比較電圧端子、2は基準信号印加端子、1は差動対トラ
ンジスタ4,5より成る比較器、6は第1スイツチング
トランジスタ、7は第1分圧抵抗8、第2分圧抵抗9及
び第3分圧抵抗10より成る分圧回路、11は第2スイ
ツチングトランジスタ、12は負荷トランジスタ、13
は出力端子、14はフライバックパルス印加端子を示す
In FIG. 1, 1 is a comparison voltage terminal to which a sawtooth wave voltage for comparison is applied, 2 is a reference signal application terminal, 1 is a comparator consisting of differential pair transistors 4 and 5, 6 is a first switching transistor, and 7 1 is a voltage dividing circuit consisting of a first voltage dividing resistor 8, a second voltage dividing resistor 9, and a third voltage dividing resistor 10; 11 is a second switching transistor; 12 is a load transistor;
indicates an output terminal, and 14 indicates a flyback pulse application terminal.

第1図の動作について説明すると、上記端子1に比較用
鋸歯状波電圧Vsが加わり、端子2に水平同期信号vH
が加わると、第1スイツチングトランジスタ6がオンに
なり、差動対トランジスタ4及び5のエミッタ電位は下
がり、上記水平同期信号VHに対する鋸歯状波電圧Vs
の位相比較を行う。
To explain the operation of FIG. 1, the sawtooth wave voltage Vs for comparison is applied to the terminal 1, and the horizontal synchronizing signal vH
, the first switching transistor 6 is turned on and the emitter potentials of the differential pair transistors 4 and 5 are lowered, causing the sawtooth wave voltage Vs with respect to the horizontal synchronizing signal VH.
Performs a phase comparison.

この場合端子14にフライバックパルスが加わるので、
第2スイツチングトランジスタ11がオンになり、第3
抵抗10の両端は上記トランジスタ11のコレクタ・エ
ミツタ路にて短絡され、基準電圧としての差動対トラン
ジスタ5のベース電位は第4図イの如く下がり、位相比
較時間T1 は従来回路のTに比べ小に即ちT1くTに
設定される。
In this case, a flyback pulse is applied to terminal 14, so
The second switching transistor 11 is turned on, and the third switching transistor 11 is turned on.
Both ends of the resistor 10 are short-circuited at the collector-emitter path of the transistor 11, the base potential of the differential pair transistor 5 as a reference voltage is lowered as shown in FIG. 4A, and the phase comparison time T1 is shorter than T in the conventional circuit. It is set to a small value, that is, T1×T.

次に第2図について説明すると、第2スイツチングトラ
ンジスタ11のコレクタ・エミツタ路は第1抵抗8の両
端に接続し、更に該第2スイツチングトランジスタ11
のベースに第3スイツチングトランジスタ15の出力側
を接続し、端子14に加わるフライバックパルスによっ
てフライバック期間、第3スイツチングトランジスタ1
5がオン、第2スイツチングトランジスタ11がオンに
なるので第5図イの如く、差動対トランジスタ5のベー
ス電位は上昇し、従って位相比較時間T2は従来回路に
比べ犬に即ちT2くTに設定される。
Next, referring to FIG. 2, the collector-emitter path of the second switching transistor 11 is connected to both ends of the first resistor 8;
The output side of the third switching transistor 15 is connected to the base of the third switching transistor 15, and the flyback pulse applied to the terminal 14 causes the third switching transistor 1 to
5 is turned on and the second switching transistor 11 is turned on, the base potential of the differential pair transistor 5 rises as shown in FIG. is set to

以上の通り本考案によれば、第1図又は第2図の実施例
に示す様に、比較器を構成する差動対トランジスタの一
方のベース電位をフライバック期間、変化させることに
よって、位相比較時間を任意に設定することができ、設
計仕様に応じた位相比較回路を提供でき、本考案は構成
が簡単な故、集積回路(IC)化が容易であると共にテ
レビ受像機のAFC回路に極めて有用である。
As described above, according to the present invention, as shown in the embodiment of FIG. 1 or 2, by changing the base potential of one of the differential pair transistors constituting the comparator during the flyback period, The time can be set arbitrarily, and a phase comparator circuit can be provided according to the design specifications.Since the present invention has a simple configuration, it is easy to integrate it into an integrated circuit (IC) and is extremely suitable for AFC circuits of television receivers. Useful.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本考案の位相比較回路、第3図イ2
口は従来の同回路の説明波形図、第4図イ2口及び第5
図イ2口は本考案の同回路の説明波形図を示す。 主な図番の説明、1・・・比較電圧端子、2・・・基準
信号印加端子、3・・・比較器、4,5・・・差動対ト
ランジスタ、6・・・第1スイツチングトランジスタ、
−1−・・・・・・分圧回路、11・・・第2スイツチ
ングトランジスタ。
Figures 1 and 2 show the phase comparator circuit of the present invention, Figure 3 A2
Figures 4 and 5 are explanatory waveform diagrams of the conventional circuit, respectively.
Figure A2 shows an explanatory waveform diagram of the same circuit of the present invention. Explanation of main figure numbers, 1... Comparison voltage terminal, 2... Reference signal application terminal, 3... Comparator, 4, 5... Differential pair transistor, 6... First switching transistor,
-1-... Voltage dividing circuit, 11... Second switching transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 比較用鋸歯状波電圧が印加される比較電圧端子に差動対
トランジスタの一方のベース側を接続すると共に上記差
動対トランジスタの他方のベースを電源と基準電位点と
の間に順次接続された第1、第2.第3抵抗より成る分
圧回路の1分圧点に接続し、上記差動対トランジスタの
共通エミッタと基準電位点との間にコレクタ・エミッタ
間が接続された第1のスイッチングトランジスタのベー
ス側を水平同期信号が印加される基準信号印加端子に接
続し、上記第1抵抗又は第3抵抗に並列にコレクタ・エ
ミッタが接続された第2のスイッチングトランジスタの
ベース側にフライバックパルス印加用の端子を接続し、
上記差動対トランジスタの何れか一方のコレクタに出力
端子を接続したことを特徴とする位相比較回路。
One base side of the differential pair transistors is connected to a comparison voltage terminal to which a comparison sawtooth wave voltage is applied, and the other base side of the differential pair transistors is sequentially connected between the power supply and the reference potential point. 1st, 2nd. The base side of the first switching transistor is connected to one voltage dividing point of the voltage dividing circuit consisting of the third resistor, and the collector-emitter is connected between the common emitter of the differential pair transistors and the reference potential point. A terminal for applying a flyback pulse is connected to a reference signal application terminal to which a horizontal synchronizing signal is applied, and a terminal for applying a flyback pulse is connected to the base side of a second switching transistor whose collector and emitter are connected in parallel to the first resistor or the third resistor. connection,
A phase comparison circuit characterized in that an output terminal is connected to the collector of one of the differential pair transistors.
JP11149477U 1977-08-18 1977-08-18 phase comparison circuit Expired JPS5834844Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11149477U JPS5834844Y2 (en) 1977-08-18 1977-08-18 phase comparison circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11149477U JPS5834844Y2 (en) 1977-08-18 1977-08-18 phase comparison circuit

Publications (2)

Publication Number Publication Date
JPS5437017U JPS5437017U (en) 1979-03-10
JPS5834844Y2 true JPS5834844Y2 (en) 1983-08-05

Family

ID=29059398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11149477U Expired JPS5834844Y2 (en) 1977-08-18 1977-08-18 phase comparison circuit

Country Status (1)

Country Link
JP (1) JPS5834844Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5796028U (en) * 1980-12-05 1982-06-12

Also Published As

Publication number Publication date
JPS5437017U (en) 1979-03-10

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