JP2000022517A - Small power consumption driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of a through current and to reduce power consumption. SOLUTION: Delay parts 13 and 14 for delaying the potential change of a signal input part 3 for a prescribed time and outputting it are provided, a PMOS transistor 11 for control is provided between the PMOS transistor 1 and a signal output part 4 and an NMOS transistor for the control is provided between the NMOS transistor 2 and the signal output part 4. Then, the PMOS transistor 11 for the control is made non-conductive in the case that the output of the delay part 13 for delaying the potential change of the signal input part 3 for the prescribed time has a low level (L level) potential and the NMOS transistor 12 for the control is made non-conductive in the case that the output of the delay part 14 for delaying the potential change of the signal input part 3 for the prescribed time has a high level (H level) potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a low power consumption driver circuit, and more particularly to a low power consumption driver circuit used for a signal input terminal of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, a driver circuit used for a signal input terminal of a semiconductor integrated circuit device has a circuit configuration as shown in FIG. In the figure, 1 is a signal input unit 3
PMO that conducts when a low level (L level) potential is applied to the signal output unit 4 and applies the power supply potential VDD to the signal output unit 4
The S transistor 2 is turned on when a high level (H level) potential is applied to the signal input unit 3, and the S transistor 2 is turned on.
Is an NMOS transistor that applies the ground potential GND to the gate. G indicates a gate of each MOS transistor, S indicates a source, and D indicates a drain.

FIG. 5 is a timing chart showing the operation of a conventional driver circuit. When the potential of the signal input unit 3 changes from the high level to the low level between times T1 and T2, the PMOS transistor 1 is turned off (OFF) and the NMOS transistor 2 is turned on (ON). As a result, the potential of the signal output unit 4 changes from a high level to a low level.

[0004]

However, in such a conventional driver circuit, the inversion operation of the PMOS transistor 1 or the NMOS transistor 2 due to variations in device parameters or the like during a transition period of the potential change of the signal input section. Due to the delay, both transistors are temporarily turned on, causing an excessive through current to flow from the power supply potential VDD to the ground potential GND, thereby increasing the power consumption of the entire semiconductor integrated circuit device. That is, as shown in FIG. 5, the PMOS transistor 1 may be turned off with a delay, although the NMOS transistor 2 is turned on immediately after the time T1.

Accordingly, in such a case, the time T1
Between T2 and T2, a section where both transistors are conductive occurs, and an excessive through current flows. The present invention has been made to solve such a problem, and an object of the present invention is to provide a low power consumption driver circuit capable of suppressing generation of a through current and reducing power consumption.

[0006]

In order to achieve the above object, a low power consumption driver circuit according to the present invention provides a first circuit which delays a potential change of a signal input section by a predetermined time and outputs the delayed signal.
And a second delay unit, a control PMOS transistor is provided between the PMOS transistor and the signal output unit, and a control NMOS transistor is provided between the NMOS transistor and the signal output unit. When the output of the second delay unit is at a high level (H level), the control PMOS transistor is turned off when the output of the second delay unit is at a low level (L level) potential.
The MOS transistor is made non-conductive.

Therefore, even when the PMOS transistor or the NMOS transistor becomes non-conductive with a delay due to the potential change of the signal input portion, the control PMOS transistor and the control NMOS transistor become conductive with a predetermined time delay. And NMO
The period during which the S transistors are turned on at the same time is shortened, or the occurrence of the period is suppressed.

[0008]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a low power consumption driver circuit according to an embodiment of the present invention.
The same or equivalent parts as in FIG. In the figure, reference numerals 13 and 14 denote delay units for delaying a potential change of the signal input unit 3 by a predetermined delay time t and outputting the delayed signal. G indicates a gate of each MOS transistor, S indicates a source, and D indicates a drain.

Reference numeral 11 is provided between the PMOS transistor 1 and the signal output unit 4, and is turned on (O) when the output of the delay unit 13 (first delay unit) is at a high level (H level) potential.
N), and is a control PMOS transistor that is turned off (OFF) when it is at a low level (L level) potential.
Reference numeral 12 is provided between the NMOS transistor 2 and the signal output unit 4, and is turned on when the output of the delay unit 14 (second delay unit) is at a low level (L level) potential, and is set to a high level (H
Level), which is a control NMOS transistor that becomes non-conductive in the case of a potential.

That is, the source S of the PMOS transistor 1 is connected to the power supply potential VDD, and its gate G is connected to the signal input unit 3. The inputs of the delay elements 13 and 14 are connected to the signal input unit 3, the gate G of the control PMOS transistor 11 is connected to the output of the delay element 13,
The drain D is connected to the signal output unit 4, and the source S is connected to the drain D of the PMOS transistor 1.

The source S of the NMOS transistor 2
Is connected to the ground potential GND, and its gate G is connected to the signal input unit 3. The gate G of the control NMOS transistor 12 is connected to the output of the delay element 14, the drain D is connected to the signal output unit 4, and the source S is connected to the drain D of the NMOS transistor 2.

Next, the operation of the present invention will be described with reference to FIG. At time T1, when the potential of the signal input unit 3 starts to change from the high-level potential to the low-level potential, similarly to the above (see FIG. 5), first, the NMOS transistor 2 is turned on, and then the PMOS transistor 1 is turned on. Suppose you did. At this time, the changes of the signal input unit 3 are transmitted to the control PMOS transistor 11 and the control NMOS transistor 12 with delays of a predetermined time t by the delay units 13 and 14, respectively.

Therefore, during the period from the time T1 to the elapse of the predetermined time t, the control PMOS transistor 1
1 conducts, and the control NMOS transistor 12 remains non-conductive. As a result, during a period from the time T1 until a predetermined time t elapses, both the PMOS transistor 1 and the control PMOS transistor 11 are turned on, and the power supply potential VDD remains applied to the signal output unit 4.

In this period, since the control NMOS transistor 12 remains non-conductive, the power supply potential VD
D is no longer connected to the ground potential GND, and the generation of through current is suppressed.

Thereafter, the delayed PMOS transistor 1 becomes non-conductive. Further, after the elapse of the delay time t from the time T1, the outputs of the delay units 13 and 14 change, so that the control PMOS transistor 11 is turned off and the control NMOS transistor 12 is turned on.
Therefore, since the NMOS transistor 2 is already conducting, the ground potential GND is applied to the signal output unit 4, and the potential of the signal output unit 4 changes.

In this way, by appropriately setting the delay time t of each of the delay units 13 and 14 according to the operation delay of the PMOS transistor 1 and the NMOS transistor 2,
PMOS transistor 1 and NMOS transistor 2
Can be shortened at the same time, or the occurrence of such a period can be suppressed. As a result, it is possible to control the period during which a through current is generated, and as a result, it is possible to suppress the generation of the through current, and to reduce the power consumption of the entire semiconductor integrated circuit device.

As the delay time t, the signal input unit 3
PMOS transistor 1 and NM
The time required for the OS transistor 2 to perform the inversion operation is most desirable, and the generation of a through current can be completely suppressed with a minimum delay time as a driver circuit.

The delay units 13 and 14 can be configured using a resistance element or an inductance element, and can be realized by relatively simple circuit elements. In addition,
It may be configured by using a buffer configured by MOS transistors or the like, and can be configured collectively by a manufacturing process of the PMOS transistor 1 or the like.

In the above description, the case where the control PMOS transistor 11 is provided between the PMOS transistor 1 and the signal output unit 4 has been described as an example. However, the present invention is not limited to this. When the control PMOS transistor 11 is provided between the power supply potential VDD and the power supply potential VDD, the same operation and effect as described above can be obtained. The same applies to the control NMOS transistor 12, and even when the control NMOS transistor 12 is provided between the NMOS transistor 2 and the ground potential GND,
The same operation and effect as described above can be obtained.

It should be noted that the delay units 13 and 14 may be capable of adjusting the delay time by selecting a plurality of delay elements having different delay times. Further, as shown in FIG. 3, a plurality of delay elements may be connected in series to adjust the delay time.

FIG. 3A shows that the delay elements are provided with selection elements S, and the selection elements S are switched and controlled to individually select / deselect each delay element to adjust the delay time. It was made. Also, FIG. 3B shows that a switch is provided in parallel with each delay element as a selection element S, and these switches are on / off controlled to individually select / deselect each delay element, thereby reducing the delay time. It is intended to be adjusted.

Further, those delay elements having the same reference delay time t0 may be used, but the delay time of each delay element is 2 ⁿ times the reference delay time t0 (n is a natural number), that is, t0, 2t0, By setting 4t0, 8t0,..., A wider range of delay time can be set with a small number of delay elements. In this way, by selecting an arbitrary delay element in accordance with the variation in the device parameters of the PMOS transistor 1 and the NMOS transistor 2, an optimum operating characteristic as a driver circuit can be obtained.

[0023]

As described above, the present invention provides a PMO
A control PMOS transistor is provided between the S transistor and the signal output unit, and a control NMOS transistor is provided between the NMOS transistor and the signal output unit, so that the output of the first delay unit has a low level (L level) potential. In this case, the control PMOS transistor is turned off, and when the output of the second delay unit is at the high level (H level) potential, the control NMOS transistor is turned off.

Therefore, even when the PMOS transistor or the NMOS transistor becomes non-conductive with a delay due to the potential change of the signal input portion, the control PMOS transistor and the control NMOS transistor become conductive with a delay of a predetermined time. And NMO
The period during which the S transistors are turned on at the same time is shortened, or the occurrence of the period is suppressed. As a result, it is possible to control the period during which a through current is generated, and as a result, it is possible to suppress the generation of the through current, and to reduce the power consumption of the entire semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a low power consumption driver circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram in each section of the embodiment shown in FIG.

FIG. 3 is a block diagram illustrating a configuration example of a delay unit.

FIG. 4 is a block diagram of a conventional driver circuit.

FIG. 5 is a signal waveform diagram in each section of the embodiment shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... PMOS transistor, 2 ... NMOS transistor, 3 ... Signal input part (IN), 4 ... Signal output part (OU
T), 11: control PMOS transistor, 12: control NMOS transistor, 13: delay unit (first delay unit), 14: delay unit (second delay unit).

Claims (5)

[Claims] 1. A low power consumption driver circuit for outputting a potential corresponding to a potential applied to a signal input unit from a signal output unit, wherein a PMOS transistor, a control PMOS transistor, and a control transistor, each output terminal of which is connected in series, are connected in series. NMOS for
A transistor, an NMOS transistor, and first and second delay sections for delaying a potential change of a signal input section for a predetermined time and outputting the delayed signal. The signal input section includes a gate of a PMOS transistor, N
The gate of the MOS transistor is connected to the inputs of the first and second delay units, the source of the PMOS transistor is connected to the power supply potential, and the drain is connected to the source of the control PMOS transistor. The source is connected to the ground potential, the drain is connected to the source of the control NMOS transistor, the gate of the control PMOS transistor is connected to the output of the first delay unit, and the gate of the control NMOS transistor is connected to the second And a drain of the control PMOS transistor and a drain of the control NMOS transistor are connected to the signal output unit. 2. A transistor which conducts when a low-level potential is applied to a signal input unit and applies a power supply potential to the signal output unit.
A MOS transistor, an NMOS transistor that conducts when a high-level potential is applied to the signal input unit, and applies a ground potential to the signal output unit; and a first that delays a potential change of the signal input unit by a predetermined time and outputs the delayed signal. And a second delay section, between the PMOS transistor and the signal output section or the PMO
A control PMOS transistor that is provided between the S transistor and the power supply potential and that is turned on when the output of the first delay unit goes to a low level potential; and between the NMOS transistor and the signal output unit or NMO
A low power consumption driver circuit, comprising: a control PMOS transistor provided between the S transistor and the ground potential, and turned on when the output of the second delay unit becomes a high level potential. 3. The low power consumption driver circuit according to claim 1, wherein the first or second delay unit adjusts the delay time by arbitrarily selecting / deselecting a plurality of delay elements. A low power consumption driver circuit characterized by comprising means. 4. The low power consumption driver circuit according to claim 1, wherein the first or second delay unit includes a plurality of serially connected delay elements and a state in which each delay element is arbitrarily selected / non-selected. A low power consumption driver circuit comprising: 5. The low power consumption driver circuit according to claim 4, wherein each delay element has a delay time of 2 ⁿ times (n is a natural number) of a reference delay time. .