JPH04321320A - Buffer circuit - Google Patents

Abstract

PURPOSE:To optionally adjust the duty of a pulse and the delay time of an input signal. CONSTITUTION:The buffer circuit is provided with rewritable ROMs 10, 11 for many number of times electrically or optically provided in one and the same chip of a semiconductor integrated circuit, and the equivalent conductance of plural P-channel MOS transistors(TRs) 8 inserted between a power supply terminal 1. An output terminal 3 and the equivalent conductance of plural N- channel MOS TRs 9 inserted between a ground terminal and the output terminal 3 are changed optionally by a preset output signal from the ROMs 10, 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to buffer circuits such as input buffers and output buffers provided in semiconductor integrated circuits.

0002

[Prior Art] Conventionally, in this type of buffer circuit, the transistor size is fixed, that is, the driving capacity is fixed.
It had a fixed delay time and fixed rise and fall times.

Furthermore, in order to make the transistor size variable, that is, the driving ability variable, an external terminal for controlling the driving ability is required.

0004

[Problem to be Solved by the Invention] The conventional buffer circuit described above requires redesign and remanufacturing when it becomes necessary to change characteristics such as delay time during evaluation of semiconductor integrated circuits. It had drawbacks.

In particular, the phase difference between input signals, the duty of the internal clock, the phase difference between output signals, the absolute delay time of the output signal, the output clock duty, etc. determine the interface with external circuits and the maximum operating frequency of the semiconductor integrated circuit. Since this is a major factor, there was a strong demand for adjustments and optimization after the evaluation.

[0006]

[Means for Solving the Problems] The buffer circuit of the present invention is inserted between a power supply terminal and an output terminal in a semiconductor integrated circuit in which a ROM that can be electrically or optically rewritten any number of times is provided in the same chip. Multiple P-channel MO
The equivalent conductance of the S transistor and the equivalent conductance of the plurality of N channel MOS transistors inserted between the ground terminal and the output terminal are arbitrarily changed by a preset output signal from the ROM. Features.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention.

In FIG. 1, 1 is a power supply terminal, 2 is an input terminal of a buffer circuit, and 3 is an output terminal. 8 is a P-channel MOS transistor, and 9 is an N-channel MOS transistor, which constitute an inverter type buffer circuit.

[0009] The selector 6 is a ROM 10 on the same chip.
Select either the input signal from the input terminal 2 or the power supply voltage from the power supply terminal 1 by controlling the output terminal 4 of the
Since it is led to the gate terminal of each P-channel MOS transistor 8, the transistor to which the power supply voltage is applied is in a cut-off state, the transistor to which the input signal is applied is controlled by the input signal, and the transistor to which the input signal is applied is in a cut-off state. If there is more than one, they are electrically connected in parallel.

Similarly, the selector 7 selects either the input signal from the input terminal 2 or the ground voltage by controlling the output terminal 5 of the ROM 11 on the same chip, and selects either the input signal from the input terminal 2 or the ground voltage to the gate terminal of each N-channel MOS transistor 9. Therefore, the transistor to which the ground voltage is applied is cut off, and the transistor to which the input signal is applied is controlled by the input signal, and if there are multiple transistors to which the input signal is applied, they are electrically connected in parallel. Connected.

In this way, ROM10,1 on the same chip
By electrically connecting an arbitrary number of P-channel MOS transistors or N-channel MOS transistors constituting the buffer circuit in parallel under the control of the output terminals 4 and 5 of 1, the P-channel M of the buffer circuit can be
It is possible to change the equivalent conductance of OS transistor 8 and N-channel MOS transistor 9.

FIG. 2 is a block diagram of a second embodiment of the invention. In FIG. 2, 1 is a power supply terminal, 2 is an input terminal of the buffer circuit, and 3 is an output terminal. P channel MOS
Transistor 8a and N-channel MOS transistor 9a constitute an inverter type buffer circuit. It becomes possible to arbitrarily set the gate voltage of a plurality of P-channel MOS transistors 8a connected to the output terminal 4 of the ROM 10a on the same chip to a high voltage or a low voltage. As a result, the transistors to which a high voltage is applied are turned off, and the transistors to which a low voltage is applied are turned on, and if a plurality of transistors are turned on, they are electrically connected in parallel.

Similarly, the gate voltages of the plurality of N-channel MOS transistors 9a connected to the output terminal 5 of the ROM 11a on the same chip can be arbitrarily set to a high voltage or a low voltage. As a result, the transistors to which a low voltage is applied are turned off, and the transistors to which a high voltage is applied are turned on, and if a plurality of transistors are turned on, they are electrically connected in parallel.

In this way, the ROM 10a on the same chip,
As in the first embodiment, it is possible to change the equivalent conductance of the P-channel MOS transistor 8a and the N-channel MOS transistor 9a constituting the buffer circuit by controlling the output terminals 4 and 5 of the buffer circuit 11a.

In this way, the buffer circuit of this embodiment can control the conductance, that is, the driving ability, of the P-channel MOS transistor section and the N-channel MOS transistor section by the ROM in the semiconductor integrated circuit, and The signal can be arbitrarily delayed and supplied to the output terminal 3.

Furthermore, since the buffer circuit of this embodiment can change the conductance of the P-channel MOS transistor or the conductance of the N-channel MOS transistor separately, the input threshold voltage and the output rise time and fall time can be changed separately. By controlling this, it can be used as an input pulse duty adjustment circuit.

An example in which the buffer circuit of this embodiment is used as a duty adjustment circuit will be shown below. Generally, it is difficult to equalize the rise time and fall time of the output waveform of a gate circuit, and there is a time difference. Therefore, the duty changes depending on the difference in the rise and fall times after passing through several gates. FIG. 3 shows a duty adjustment circuit 12 using the buffer circuit of this embodiment, and 13
is an inverter type buffer circuit. Figure 4 is Figure 3
These are the waveforms of each part of . Waveform 15 is an input signal to input terminal 2, and what should originally be a 50% duty has changed. Here, in the buffer circuit 12, due to the equivalent conductance of the P-channel MOS transistor, N
It is assumed that the equivalent conductance of the channel MOS transistor is controlled to a greater extent. As a result, the output waveform of the output terminal 3a has a fall time shorter than a rise time, as in the signal 16. When this signal 16 is shaped by an inverter type buffer circuit 13, a signal having an output waveform 17 with a duty of 50% can be obtained.

As described above, when the buffer circuit of this embodiment is used as a delay time control circuit, it can be used for phase adjustment between input signals and output signals of a semiconductor integrated circuit. Furthermore, if there is a part in the semiconductor integrated circuit where the phase difference must be strictly controlled, optimization can be achieved by using this buffer circuit. In addition, when a buffer circuit is used as a duty control circuit, even if a signal with an incorrect duty is applied to the input terminal of a semiconductor integrated circuit, it can be corrected internally, and a signal with a predetermined duty can be output. Even if necessary, it is possible to correct the incorrect duty internally.

Furthermore, by using the buffer circuit of this embodiment, it becomes possible to correct the difference between the design and the actual product, the interface with an external circuit, and the change in characteristics due to manufacturing variations by simply rewriting the ROM.

[0020]

Effects of the Invention As explained above, the present invention provides a method for connecting a plurality of P-channel MOSs inserted between a power supply terminal and an output terminal.
Equivalent conductance of the transistor and multiple N-channel MOS inserted between the ground terminal and the output terminal
By rewriting the equivalent conductance of the transistor in the ROM on the same chip of the semiconductor integrated circuit, the delay time of the input signal and the duty of the pulse can be adjusted as desired.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the invention.

FIG. 2 is a block diagram of a second embodiment of the invention.

FIG. 3 is a block diagram in which the present embodiment is used as a duty adjustment circuit.

FIG. 4 is a waveform diagram of each part in FIG. 3;

[Explanation of symbols]

1 Power supply terminal 2 Input terminal 3 Output terminal 4, 5 ROM output terminal 6, 7 Selector circuit 8, 8a P channel MOS transistor 9,
9a N-channel MOS transistor 10,1
0a, 11, 11a...ROM 12 Buffer circuit 13 Inverter circuit

Claims (1)

[Claims] Claim 1: In a semiconductor integrated circuit in which a ROM that can be electrically or optically rewritten any number of times is provided in the same chip, a plurality of P
Arbitrarily changing the equivalent conductance of a channel MOS transistor and the equivalent conductance of a plurality of N-channel MOS transistors inserted between a ground terminal and the output terminal by a preset output signal from the ROM. A buffer circuit featuring: