JP2000260907A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JP2000260907A JP2000260907A JP11059735A JP5973599A JP2000260907A JP 2000260907 A JP2000260907 A JP 2000260907A JP 11059735 A JP11059735 A JP 11059735A JP 5973599 A JP5973599 A JP 5973599A JP 2000260907 A JP2000260907 A JP 2000260907A
- Authority
- JP
- Japan
- Prior art keywords
- epoxy
- board
- wiring board
- substrate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、メモリーカードや
ＩＣカード，ハードディスク用読み書きモジュール等、
各種情報の記録や読み出しが可能な電子装置に関する。The present invention relates to a memory card, an IC card, a hard disk read / write module, and the like.
The present invention relates to an electronic device capable of recording and reading various information.
【０００２】[0002]
【従来の技術】配線を具備した基板にＩＣチップを樹脂
接着剤により搭載し、ＩＣチップと基板上の所定配線間
に金属細線をボンディングし、そして基板，ＩＣチッ
プ，金属細線の所望部を樹脂モールドした形態の電子部
品は、メモリーカードやＩＣカード，ハードディスク用
読み書きモジュール等、各種情報の記録や読み出しが可
能な電子装置に広く応用されている。2. Description of the Related Art An IC chip is mounted on a substrate provided with wiring by a resin adhesive, a thin metal wire is bonded between the IC chip and a predetermined wiring on the substrate, and a desired portion of the substrate, the IC chip, and the thin metal wire is bonded to a resin. Electronic components in a molded form are widely applied to electronic devices capable of recording and reading various kinds of information, such as memory cards, IC cards, and read / write modules for hard disks.
【０００３】例えば、第１先行技術例としての特開平10
−163367号公報には、銅箔配線を設けたエポキシやベー
クライト等の絶縁性プリント基板上に、半導体素子がエ
ポキシ接着剤により固着され、半導体素子と配線間をＡ
ｌやＡｕワイヤで接続し、半導体素子，配線，ワイヤ，
基板の所定部がエポキシ樹脂で封止された半導体装置が
開示されている。このような構造を採ることにより、信
頼性の高い半導体装置を得ることができる。[0003] For example, Japanese Patent Application Laid-Open No.
Japanese Patent No. -163367 discloses that a semiconductor element is fixed with an epoxy adhesive on an insulating printed circuit board such as epoxy or bakelite provided with a copper foil wiring, and A
l and Au wires to connect semiconductor devices, wiring, wires,
A semiconductor device in which a predetermined portion of a substrate is sealed with an epoxy resin is disclosed. With such a structure, a highly reliable semiconductor device can be obtained.
【０００４】第２先行技術例としての特開平5−139082
号公報には、両面に銅箔配線を設けたガラスクロス入り
ビスマルイミドトリアジン（ＢＴ）樹脂あるいはガラス
エポキシ樹脂からなる配線基板上に、ＩＣチップが固着
され、半導体素子と配線間を金属ワイヤで接続し、ＩＣ
チップ，配線，ワイヤ，基板の所定部が封止樹脂でトラ
ンスファモールドされたモジュールと、このモジュール
が塩化ビニル樹脂板からなるカード基体の凹部に装着さ
れたＩＣカードが開示されている。このような構造を採
る電子装置は、各種情報の記録や読み出しをするための
メモリーカードやＩＣカードとして広く用いられてい
る。ここで、本技術例では不明確であるが、一般的に
は、ＩＣチップはエポキシ接着剤により基板上に固着さ
れ、トランスファモールド用封止樹脂にはエポキシ材が
用いられる。[0004] Japanese Patent Application Laid-Open No. H5-139082 as a second prior art example
In the publication, an IC chip is fixed on a wiring board made of bismalimide triazine (BT) resin containing glass cloth or glass epoxy resin provided with copper foil wiring on both sides, and a metal wire is used between the semiconductor element and the wiring. Connect and IC
There is disclosed a module in which predetermined portions of a chip, wiring, wires, and a substrate are transfer-molded with a sealing resin, and an IC card in which the module is mounted in a concave portion of a card base made of a vinyl chloride resin plate. Electronic devices having such a structure are widely used as memory cards and IC cards for recording and reading various information. Here, although it is unclear in the present technical example, generally, the IC chip is fixed on the substrate with an epoxy adhesive, and an epoxy material is used for the transfer molding sealing resin.
【０００５】[0005]
【発明が解決しようとする課題】上述の先行実施例にお
いて、半導体素子（あるいはＩＣチップ）基体はプリン
ト基板（あるいは配線基板）上にエポキシ接着剤により
固着される。この固着は、上記半導体素子基体とプリン
ト基板間に上記エポキシ接着剤を配置し、これらを１５
０℃の加熱してエポキシ接着剤を硬化させることにより
なされる。第１段階の問題はこの過程で生ずる。具体的
には、１５０℃の熱処理を施した後の冷却時に生ずる。
この冷却過程で、半導体素子基体とプリント基板の熱膨
張率の違いに基づくストレスが上記エポキシ接着剤及び
その近傍に作用し、このストレスが過大になると半導体
素子基体の機械的破損を生ずる。In the above-described embodiment, the semiconductor element (or IC chip) base is fixed on a printed board (or wiring board) by an epoxy adhesive. This fixing is performed by disposing the epoxy adhesive between the semiconductor element substrate and the printed circuit board,
This is done by heating at 0 ° C. to cure the epoxy adhesive. The first stage problem arises in this process. Specifically, it occurs during cooling after a heat treatment at 150 ° C.
During this cooling process, a stress based on the difference in the coefficient of thermal expansion between the semiconductor element substrate and the printed board acts on the epoxy adhesive and its vicinity, and if the stress becomes excessive, the semiconductor element substrate is mechanically damaged.
【０００６】プリント基板上に搭載された半導体素子基
体とプリント基板上の配線間には、ワイヤボンディング
により金属細線が接続される。第２段階の問題はこの過
程で生ずる。半導体素子基体が搭載されたアッセンブリ
は、金属細線の接続を強固にするため１２０〜２５０℃
に加熱されるとともに、ワイヤボンディングのための超
音波振動が印加される。この際の熱的変化及び超音波振
動の印加により、ストレスが上記エポキシ接着剤及びそ
の近傍に作用して半導体素子基体の機械的破損を生ず
る。A thin metal wire is connected by wire bonding between a semiconductor element substrate mounted on a printed board and a wiring on the printed board. The second stage problem arises in this process. The assembly on which the semiconductor element substrate is mounted has a temperature of 120 to 250 ° C. in order to strengthen the connection of the fine metal wires.
And ultrasonic vibration for wire bonding is applied. Due to the thermal change and the application of ultrasonic vibration at this time, stress acts on the epoxy adhesive and its vicinity, causing mechanical damage to the semiconductor element substrate.
【０００７】ワイヤボンディングが施されたアッセンブ
リには、引き続いてエポキシ樹脂のトランスファモール
ド処理がなされる。この際、アッセンブリは１８０℃程
度に加熱される。第３段階の問題はこの過程で生ずる。
この場合の熱的変化もエポキシ接着剤及びその近傍にス
トレスを作用され、半導体素子基体の機械的破損を生ぜ
しめる。[0007] The assembly subjected to the wire bonding is subsequently subjected to epoxy resin transfer molding. At this time, the assembly is heated to about 180 ° C. The third stage problem arises in this process.
The thermal change in this case also applies stress to the epoxy adhesive and its vicinity, and causes mechanical breakage of the semiconductor element substrate.
【０００８】第１段階で半導体素子基体の破損を生じな
い場合でも、後続の第２あるいは３段階で破損する危険
性が存在する。以上の結果、従来の電子装置では製造歩
留りが著しく低く、経済面への悪影響が無視できない程
度に及んでいた。Even if the semiconductor element substrate is not damaged in the first stage, there is a risk of damage in the subsequent second or third stage. As a result, the production yield of the conventional electronic device was extremely low, and the adverse effect on the economy was not negligible.
【０００９】また、上記第１〜３段階での破損を生じな
い場合でも、電子装置が稼働する環境の熱的変化によっ
ても半導体素子基体の破損する危険性が存在する。この
結果、電子装置の信頼性に対する悪影響が無視できない
程度に及んでいた。[0009] Even in the case where the damage is not caused in the first to third stages, there is a risk that the semiconductor element base may be damaged due to a thermal change in the environment in which the electronic device operates. As a result, the adverse effect on the reliability of the electronic device has reached a level that cannot be ignored.
【００１０】本発明の目的は上述の問題点を解決し、製
造時あるいは運転時の熱的変化によるＩＣチップ基体の
機械的破損を防止し、製造歩留りの高い電子装置を提供
することである。An object of the present invention is to solve the above-mentioned problems and to provide an electronic device having a high production yield by preventing the IC chip base from being mechanically damaged due to a thermal change during production or operation.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成する本発
明の電子装置は、ＩＣチップ基体が配線基板上に樹脂接
着剤により固着された部分を有する電子装置において、
前記配線基板がエポキシ配線基板の場合前記樹脂接着剤
のヤング率が２５〜２００kg／mm2 、ガラスエポキシ配
線基板の場合２５〜２４０kg／mm2 、Ｃｕコア／エポキ
シ複合配線基板の場合２５〜３３０kg／mm2 、そしてＣ
ｕ基板の場合２５〜４２０kg／mm2 の範囲に選択された
ことを特徴とする。According to the present invention, there is provided an electronic device having a portion in which an IC chip base is fixed on a wiring substrate with a resin adhesive.
When the wiring board is an epoxy wiring board, the Young's modulus of the resin adhesive is 25 to 200 kg / mm 2 , when the glass epoxy wiring board is 25 to 240 kg / mm 2 , and when the Cu core / epoxy composite wiring board is 25 to 330 kg / mm 2 . mm 2 and C
In the case of a u substrate, it is characterized in that it is selected in the range of 25 to 420 kg / mm 2 .
【００１２】[0012]
【発明の実施の形態】本発明の電子装置３０は、図１に
示す断面図のような形態を有している。ＩＣチップ基体
１は、配線基板１０上に樹脂接着剤２０により固着され
ている。配線基板１０は、ガラスクロス入りビスマルイ
ミドトリアジン（ＢＴ）樹脂，ガラスエポキシ樹脂，エ
ポキシ樹脂，ベークライト樹脂，ポリイミド樹脂等を母
材とする絶縁基板１１に凹部１２を形成し、絶縁基板１
１の凹部１２を形成した側に銅箔層１３そして反対側に
裏面銅箔層１４を形成し、銅箔層１３と裏面銅箔層１４
の間にスルーホール銅１５を設け、銅箔層１３上に金め
っき層１６そして裏面銅箔層１４上に裏面金めっき層１
７を形成したものである。銅箔層１３と金めっき層１６
は表面電極１８を形成し、裏面銅箔層１４と裏面金めっ
き層１７は裏面電極１９を形成している。ＩＣチップ基
体１は凹部１２に配置され、これと表面電極１８の間
は、ＡｕやＡｌ等の金属細線２１の超音波ボンディング
により電気的に接続されている。絶縁基板１１の一部
と、ＩＣチップ基体１，表面電極１８，樹脂接着剤２
０、そして金属細線２１は、エポキシ樹脂２２のトラン
スファモールドにより封止されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic device 30 according to the present invention has a form as shown in the sectional view of FIG. The IC chip base 1 is fixed on the wiring board 10 with a resin adhesive 20. The wiring board 10 is formed by forming a recess 12 in an insulating substrate 11 made of a glass cloth-containing bismalimide triazine (BT) resin, glass epoxy resin, epoxy resin, bakelite resin, polyimide resin, or the like as a base material.
A copper foil layer 13 is formed on the side where the concave portion 12 is formed, and a backside copper foil layer 14 is formed on the opposite side.
A through-hole copper 15 is provided between the copper plating layer 13, the gold plating layer 16 on the copper foil layer 13, and the backside gold plating layer 1 on the backside copper foil layer 14.
7 is formed. Copper foil layer 13 and gold plating layer 16
Forms a front surface electrode 18, and the back surface copper foil layer 14 and the back surface gold plating layer 17 form a back surface electrode 19. The IC chip substrate 1 is disposed in the concave portion 12, and is electrically connected between the concave portion 12 and the surface electrode 18 by ultrasonic bonding of a thin metal wire 21 such as Au or Al. A part of the insulating substrate 11, an IC chip base 1, a surface electrode 18, a resin adhesive 2
0, and the thin metal wires 21 are sealed by transfer molding of an epoxy resin 22.
【００１３】上記の構造を有する本発明電子装置では、
ＩＣチップ基体を配線基板上に固着する樹脂接着剤のヤ
ング率が２５〜１５０kg／mm2 の範囲に選択される。こ
の理由について以下に説明する。In the electronic device of the present invention having the above structure,
The Young's modulus of the resin adhesive for fixing the IC chip base on the wiring board is selected in the range of 25 to 150 kg / mm 2 . The reason will be described below.
【００１４】図２はガラスエポキシ基板１０上にＩＣチ
ップ基体１をエポキシ樹脂接着剤２０により固着した構
造体における最大応力発生部及びクラック発生部を示
す。最大応力発生部はシミュレーションの結果で、１５
０℃での固着後に室温（２０℃）まで冷却した上記第１
段階を想定したものである。ここで、エポキシ樹脂接着
剤層２０の熱膨張率は５３ppm／℃ 、そしてヤング率は
６５０kg／mm2 である。最大応力（１３.５kg／mm2）は
エポキシ樹脂接着剤層２０とＩＣチップ基体１間の界面
の端部で生じている。また、クラック発生部は実試料の
断面観察による結果である。固着後のＩＣチップ基体１
にはクラック４０を生じており、このクラックはエポキ
シ樹脂接着剤２０に極めて近いチップ基体１の領域を進
展している。このクラック発生状況から、クラックはエ
ポキシ樹脂接着剤層２０とＩＣチップ基体１の間の界面
端部付近を起点（Ａ部）にして発生し、そして樹脂接着
剤層２０近傍のＩＣチップ基体１の領域を進展したもの
と考えられる。なお、実試料におけるエポキシ樹脂接着
剤のヤング率は６５０kg／mm2 である。FIG. 2 shows a maximum stress generating portion and a crack generating portion in a structure in which the IC chip substrate 1 is fixed on a glass epoxy substrate 10 by an epoxy resin adhesive 20. The maximum stress generation part is the result of the simulation.
After fixing at 0 ° C., the first material was cooled to room temperature (20 ° C.).
The steps are assumed. Here, the thermal expansion coefficient of the epoxy resin adhesive layer 20 is 53 ppm / ° C., and the Young's modulus is 650 kg / mm 2 . The maximum stress (13.5 kg / mm 2 ) is generated at the end of the interface between the epoxy resin adhesive layer 20 and the IC chip base 1. The crack occurrence part is the result of cross-sectional observation of the actual sample. IC chip base 1 after fixing
Has a crack 40, which propagates in a region of the chip base 1 very close to the epoxy resin adhesive 20. From the cracking situation, the cracks are generated starting from the vicinity of the interface end between the epoxy resin adhesive layer 20 and the IC chip base 1 (part A), and the cracks of the IC chip base 1 near the resin adhesive layer 20 are generated. It is considered that the area has evolved. The Young's modulus of the epoxy resin adhesive in the actual sample is 650 kg / mm 2 .
【００１５】また、ＩＣチップ基体の固着部を超音波探
傷法により観測した。これによると、ガラスエポキシ基
板１０にＩＣチップ基体１をエポキシ樹脂接着剤２０に
より固着する過程（第１段階）では、クラック発生率は
７５％に及んでいる。第１段階でクラック発生が観測さ
れなかった試料でも、その約５０％はＩＣチップ基体と
プリント基板上の配線間にワイヤボンディングする第２
段階で、そして約２５％はトランスファモールド処理が
なされる第３段階でクラックを生じた。Further, the fixed portion of the IC chip base was observed by an ultrasonic flaw detection method. According to this, in the process of fixing the IC chip base 1 to the glass epoxy substrate 10 with the epoxy resin adhesive 20 (first stage), the crack occurrence rate reaches 75%. Approximately 50% of the samples in which cracks were not observed in the first stage were subjected to wire bonding between the IC chip base and the wiring on the printed circuit board.
At the stage, and about 25% cracked at the third stage where the transfer molding process was performed.
【００１６】本発明は以上のような状況に鑑み、クラッ
ク４０の発生を抑えるためになされたものである。The present invention has been made in view of the above situation to suppress the occurrence of cracks 40.
【００１７】図３は各種配線基板１０上にＩＣチップ基
体１をエポキシ樹脂接着剤２０により固着する第１段階
で発生する応力のシミュレーション結果を示す。ここ
で、応力は１５０℃での固着後に室温（２０℃）まで冷
却した段階のもので、最大値を示すエポキシ樹脂接着剤
層２０とＩＣチップ基体１の間の界面端部（Ａ部）にお
ける値である。また、曲線Ａはエポキシ配線基板、Ｂは
ガラスエポキシ配線基板、ＣはＣｕコア／エポキシ複合
配線基板、そしてＤはＣｕ基板の場合についてのもので
ある。応力発生の傾向は、いずれの配線基板を用いた場
合もほぼ同様である。エポキシ樹脂接着剤層２０のヤン
グ率が大きい領域では、発生する応力は大きい値をとっ
ている。これに対し、ヤング率の小さい領域では応力は
小さくなる。このことから、ＩＣチップ基体１の破損を
避けるためには、エポキシ樹脂接着剤２０のヤング率を
なるべく小さい値に選択するのが有効であることを読み
取れる。FIG. 3 shows a simulation result of a stress generated in the first stage of fixing the IC chip base 1 on the various wiring boards 10 with the epoxy resin adhesive 20. Here, the stress is at the stage of cooling down to room temperature (20 ° C.) after fixing at 150 ° C., and the stress at the interface end (A portion) between the epoxy resin adhesive layer 20 and the IC chip substrate 1 showing the maximum value. Value. Curve A is for an epoxy wiring board, B is for a glass epoxy wiring board, C is for a Cu core / epoxy composite wiring board, and D is for a Cu substrate. The tendency of stress generation is almost the same in any of the wiring boards. In the region where the Young's modulus of the epoxy resin adhesive layer 20 is large, the generated stress takes a large value. On the other hand, the stress is small in a region where the Young's modulus is small. From this, it can be seen that it is effective to select the smallest possible value of the Young's modulus of the epoxy resin adhesive 20 in order to avoid breakage of the IC chip base 1.
【００１８】図４は第１段階でＡ部に発生する応力のシ
ミュレーション結果で、エポキシ樹脂接着剤の熱膨張率
による比較を示す。ここで、曲線Ａはエポキシ樹脂基板
そしてＢはＣｕ基板の場合について示している。熱膨張
率を５３ppm／℃から３０ｐｐｍ／℃と小さくした場合
は、応力発生量はわずかに低下するけれども、さほど大
きな低減効果は見られない。この結果から、ＩＣチップ
基体１の破損を避けるためには、エポキシ樹脂接着剤２
０の熱膨張率を調整するよりも、そのヤング率を選択す
ることの方が有効である。FIG. 4 is a simulation result of a stress generated in the portion A in the first stage, and shows a comparison based on a coefficient of thermal expansion of the epoxy resin adhesive. Here, curve A shows the case of an epoxy resin substrate and B shows the case of a Cu substrate. When the coefficient of thermal expansion is reduced from 53 ppm / ° C. to 30 ppm / ° C., the amount of stress generation slightly decreases, but no significant reduction effect is observed. From this result, in order to avoid breakage of the IC chip base 1, the epoxy resin adhesive 2
It is more effective to select the Young's modulus than to adjust the coefficient of thermal expansion to zero.
【００１９】図５は第１段階におけるクラック発生率と
Ａ部に発生する応力との相関を示す。クラック発生率は
発生応力７ｋｇ／mm2 までは０％に保たれている。しか
し、これ以上の応力が生ずる状態になるとクラック発生
率は逐次増大する。この結果は、第１段階でのクラック
発生を抑えるためには、発生応力を７kg／mm2 以下に制
御する必要性を示唆する。FIG. 5 shows the correlation between the crack generation rate in the first stage and the stress generated in the portion A. The crack occurrence rate is kept at 0% up to a stress of 7 kg / mm 2 . However, when the stress becomes higher than this, the crack generation rate gradually increases. This result suggests that it is necessary to control the generated stress to 7 kg / mm 2 or less in order to suppress crack generation in the first stage.
【００２０】図３を参照すると、発生応力を７kg／mm2
以下に制御するためには、エポキシ樹脂接着剤２０のヤ
ング率はエポキシ配線基板の場合２０５kg／mm2 以下，
ガラスエポキシ配線基板の場合２７０kg／mm2 以下、そ
してＣｕコア／エポキシ複合配線基板の場合３３０kg／
mm2 以下、そしてＣｕ配線基板の場合４３０kg／mm2以
下にそれぞれ選択する必要がある。Referring to FIG. 3, the generated stress is 7 kg / mm 2.
In order to control below, the Young's modulus of the epoxy resin adhesive 20 is 205 kg / mm 2 or less in the case of an epoxy wiring board,
270 kg / mm 2 or less for glass epoxy wiring board and 330 kg / mm for Cu core / epoxy composite wiring board
mm 2 or less, and 430 kg / mm 2 or less in the case of a Cu wiring board.
【００２１】ここで、図６は配線基板の母材の形態を説
明する図である。（ａ）はエポキシ基板１１であり、エ
ポキシ樹脂のマトリックス１１１中にシリカ，アルミナ
等のセラミックスフィラ１１２を分散したものである。
（ｂ）はガラスエポキシ基板１１であり、エポキシ樹脂
のマトリックス１１１中にガラス繊維１１３を埋め込ん
だ状態のものである。（ｃ）はＣｕコア／エポキシ複合
基板１１であり、Ｃｕコア板１１４の両面にエポキシ樹
脂層１１１を設けた形態のものである。（ｄ）はＣｕ基
板でありＣｕ板１１４に絶縁層としてのエポキシ樹脂層
１１１を設けたものである。これらは、母材の両面に所
望の金属配線を設けて使用される。FIG. 6 is a view for explaining the form of the base material of the wiring board. (A) is an epoxy substrate 11 in which a ceramic filler 112 such as silica or alumina is dispersed in an epoxy resin matrix 111.
(B) is a glass epoxy substrate 11 in which glass fibers 113 are embedded in a matrix 111 of epoxy resin. (C) shows a Cu core / epoxy composite substrate 11 in which an epoxy resin layer 111 is provided on both surfaces of a Cu core plate 114. (D) is a Cu substrate having a Cu plate 114 provided with an epoxy resin layer 111 as an insulating layer. These are used by providing desired metal wiring on both surfaces of the base material.
【００２２】なお、ＩＣチップ基体１のクラック発生を
抑える観点では、エポキシ樹脂接着剤２０のヤング率は
可及的に小さい値であることが望ましい。しかしなが
ら、ヤング率が過度に小さい場合は、ＩＣチップ基体１
にワイヤボンディングを施こす際にワイヤボンディング
ツールの超音波振動とともにＩＣチップ基体１も振動す
る。この結果、金属細線が強固に接続されにくくなる。
このような制約から、ヤング率が２５kg／mm2 未満のエ
ポキシ樹脂接着剤２０は、その使用を避けることが望ま
しい。From the viewpoint of suppressing the occurrence of cracks in the IC chip base 1, it is desirable that the Young's modulus of the epoxy resin adhesive 20 be as small as possible. However, if the Young's modulus is excessively small, the IC chip substrate 1
When wire bonding is performed, the IC chip base 1 vibrates together with the ultrasonic vibration of the wire bonding tool. As a result, it becomes difficult for the thin metal wires to be firmly connected.
From such restrictions, it is desirable to avoid using the epoxy resin adhesive 20 having a Young's modulus of less than 25 kg / mm 2 .
【００２３】以上の構成を、図面を用いて説明する。The above configuration will be described with reference to the drawings.
【００２４】（実施例）本実施例では、ガラスエポキシ
配線基板上にＩＣチップを搭載した電子装置３０及びこ
れを用いたＩＣカード５０について説明する。(Embodiment) In this embodiment, an electronic device 30 having an IC chip mounted on a glass epoxy wiring board and an IC card 50 using the same will be described.
【００２５】ＩＣチップを搭載した電子装置３０は、図
１に示すような断面構造を有している。ＩＣチップ基体
１（チップサイズ：６×６×０.２５mm ）は、配線基体
１０上に厚さ２５μｍそしてヤング率６５kg／mm2 のエ
ポキシ樹脂接着剤２０により固着されている。この固着
は１５０℃×１ｈの熱処理によりなされている（第１段
階）。配線基板１０は、ガラスエポキシ樹脂を母材とす
る絶縁基板１１に凹部１２を形成し、絶縁基板１１の凹
部１２を形成した側に銅箔層１３（厚さ：１８μｍ）そ
して反対側に裏面銅箔層１４（厚さ：１８μｍ）を形成
し、銅箔層１３と裏面銅箔層１４の間にスルーホール銅
１５を設け、銅箔層１３上に金めっき層１６（厚さ：５
μｍ）そして裏面銅箔層１４上に裏面金めっき層１７
（厚さ：５μｍ）を形成したものである。銅箔層１３と
金めっき層１６は表面電極１８を形成し、裏面銅箔層１
４と裏面金めっき層１７は裏面電極１９を形成してい
る。The electronic device 30 on which the IC chip is mounted has a sectional structure as shown in FIG. The IC chip substrate 1 (chip size: 6 × 6 × 0.25 mm) is fixed on the wiring substrate 10 with an epoxy resin adhesive 20 having a thickness of 25 μm and a Young's modulus of 65 kg / mm 2 . This fixation is performed by a heat treatment at 150 ° C. × 1 h (first stage). The wiring substrate 10 has a concave portion 12 formed on an insulating substrate 11 made of glass epoxy resin as a base material, a copper foil layer 13 (thickness: 18 μm) on the side of the insulating substrate 11 where the concave portion 12 is formed, and a backside copper on the opposite side. A foil layer 14 (thickness: 18 μm) is formed, a through-hole copper 15 is provided between the copper foil layer 13 and the backside copper foil layer 14, and a gold plating layer 16 (thickness: 5
μm) and the backside gold plating layer 17 on the backside copper foil layer 14.
(Thickness: 5 μm). The copper foil layer 13 and the gold plating layer 16 form the front surface electrode 18,
4 and the backside gold plating layer 17 form a backside electrode 19.
【００２６】ＩＣチップ基体１は凹部１２に配置され、
これと表面電極１８の間は、Ａｕ細線２１（直径：２５
μｍ）の超音波ボンディングにより電気的に接続されて
いる。このワイヤボンディングでは、試料は２３０℃に
加熱された（第２段階）。絶縁基板１１の一部と、ＩＣ
チップ基体１，表面電極１８，樹脂接着剤２０、そして
金属細線２１は、エポキシ樹脂２２（熱膨張率：１４pp
m／℃ ，ヤング率：１５００kg／mm2 ）のトランスファ
モールドにより封止されている。このトランスファモー
ルドは、１８０℃のもとで実施された（第３段階）。The IC chip base 1 is disposed in the recess 12,
An Au thin wire 21 (diameter: 25) is provided between this and the surface electrode 18.
μm) by ultrasonic bonding. In this wire bonding, the sample was heated to 230 ° C. (second stage). A part of the insulating substrate 11 and an IC
The chip base 1, the surface electrode 18, the resin adhesive 20, and the fine metal wire 21 are made of epoxy resin 22 (thermal expansion coefficient: 14 pp).
m / ° C., Young's modulus: 1500 kg / mm 2 ). This transfer mold was performed at 180 ° C. (third stage).
【００２７】上記の構造を有する本実施例電子装置３０
では、ＩＣチップ基体１を配線基板１０上に固着する樹
脂接着剤２０のヤング率が６０kg／mm2 に選択されてい
る。表１は電子装置３０の組み立て過程におけるチップ
破損率を示す。第１〜３段階のいずれの工程でも、ＩＣ
チップ１の破損は観測されていない。この効果は上述し
たように、エポキシ樹脂接着剤２４のヤング率が６０kg
／mm2 と適正に調整されていることに基づく。The electronic device 30 of this embodiment having the above structure
In this case, the Young's modulus of the resin adhesive 20 for fixing the IC chip base 1 on the wiring board 10 is selected to be 60 kg / mm 2 . Table 1 shows the chip breakage rate in the process of assembling the electronic device 30. In any of the first to third steps, the IC
No breakage of chip 1 was observed. As described above, this effect is obtained when the Young's modulus of the epoxy resin adhesive 24 is 60 kg.
/ Mm 2 based on proper adjustment.
【００２８】[0028]
【表１】 [Table 1]
【００２９】また、本実施例電子装置３０には、−５５
〜１５０℃の温度サイクルが印加された。この試験を１
０００回実施した後の、ＩＣチップ１のクラック発生率
は０％であった。一方、ヤング率が６５０kg／mm2 のエ
ポキシ樹脂接着剤でＩＣチップを固着した、同様構造の
比較例試料のクラック発生率は１００％であった。上記
両者の比較から、本実施例電子装置３０は使用過程にお
ける信頼性の点でも格段に優れていることが確認され
る。The electronic device 30 of the present embodiment has -55
A temperature cycle of １５０150 ° C. was applied. This test is 1
The crack occurrence rate of the IC chip 1 after performing the test 000 times was 0%. On the other hand, the crack generation rate of the comparative example sample having the same structure in which the IC chip was fixed with an epoxy resin adhesive having a Young's modulus of 650 kg / mm 2 was 100%. From the comparison between the two, it is confirmed that the electronic device 30 of the present embodiment is remarkably excellent also in terms of reliability in the use process.
【００３０】図７は電子装置３０をカード基体に組み込
んだＩＣカード５０の断面図を示す。電子装置３０は方
形の薄いカード基体４１の凹部４２にシリコーン接着剤
４３により固着されている。電子装置３０の裏面電極１
９は、ＩＣチップ５０が実用される際に外部との情報授
受するための端子となる。ここで、電子装置３０はカー
ド基体４１に固着される際に、シリコーン接着剤４３を
硬化させるための熱処理（１５０℃×１ｈ）を受ける。
この熱処理によっても、ＩＣチップ１のＡ部には応力が
作用する。しかし、本実施例においては、クラックの発
生は全く認められない。このことも、エポキシ樹脂接着
剤２０のヤング率が適正な値に選択されていることによ
る。FIG. 7 is a sectional view of an IC card 50 in which the electronic device 30 is incorporated in a card base. The electronic device 30 is fixed to a concave portion 42 of a rectangular thin card base 41 with a silicone adhesive 43. Back electrode 1 of electronic device 30
Reference numeral 9 denotes a terminal for exchanging information with the outside when the IC chip 50 is put to practical use. Here, when the electronic device 30 is fixed to the card base 41, it is subjected to a heat treatment (150 ° C. × 1 h) for curing the silicone adhesive 43.
Stress is also applied to the portion A of the IC chip 1 by this heat treatment. However, in the present embodiment, no crack was observed. This is also because the Young's modulus of the epoxy resin adhesive 20 is selected to an appropriate value.
【００３１】以上までに、本発明の実施例について説明
した。本発明において、基板１０に搭載される半導体基
体になり得る素材は、Ｓｉ：４.２ppm／℃，Ｇｅ：５.
８ppm／℃，ＧａＡｓ：６.５ppm／℃，ＧａＰ：５.３pp
m／℃，ＳｉＣ：３.５ppm／℃等である。これらの素材
からなる半導体素子を搭載することに何らの制約もな
い。The embodiments of the present invention have been described above. In the present invention, the material that can be a semiconductor substrate mounted on the substrate 10 is Si: 4.2 ppm / ° C., Ge: 5.
8 ppm / ° C, GaAs: 6.5 ppm / ° C, GaP: 5.3 pp
m / ° C, SiC: 3.5 ppm / ° C, etc. There are no restrictions on mounting semiconductor elements made of these materials.
【００３２】[0032]
【発明の効果】本発明によれば、製造時あるいは運転時
に生ずる熱歪を低減し、破壊の恐れがなく、信頼性に優
れた電子装置を提供することができる。According to the present invention, it is possible to provide an electronic device which is reduced in thermal strain during manufacturing or operation, has no risk of destruction, and has excellent reliability.
【図１】本発明電子装置の断面図である。FIG. 1 is a cross-sectional view of an electronic device according to the present invention.
【図２】最大応力発生部及びクラック発生部を示す断面
図である。FIG. 2 is a cross-sectional view showing a maximum stress generating portion and a crack generating portion.
【図３】各種配線基板上にＩＣチップ基体をエポキシ樹
脂接着剤により固着する第１段階で発生する応力を示す
グラフである。FIG. 3 is a graph showing a stress generated in a first stage of fixing an IC chip base on various wiring boards with an epoxy resin adhesive.
【図４】第１段階でＡ部に発生する応力のシミュレーシ
ョン結果を説明するグラフである。FIG. 4 is a graph illustrating a simulation result of a stress generated in a portion A in a first stage.
【図５】第１段階におけるクラック発生率とＡ部に発生
する応力との相関を示すグラフである。FIG. 5 is a graph showing a correlation between a crack generation rate in a first stage and a stress generated in a portion A.
【図６】配線基板の母材の各形態を説明する断面図であ
る。FIG. 6 is a cross-sectional view illustrating each form of a base material of the wiring board.
【図７】電子装置をカード基板に組み込んだＩＣカード
の断面図である。FIG. 7 is a cross-sectional view of an IC card in which an electronic device is incorporated in a card substrate.
１…ＩＣチップ基体、１０…配線基板、１１…絶縁基
板、１２，４２…凹部、１３…銅箔層、１４…裏側銅箔
層、１５…スルーホール銅、１６…金めっき層、１８…
表面電極、１９…裏面電極、２０…樹脂接着剤、２１…
金属細線、２２…エポキシ樹脂、３０…電子装置、４０
…クラック、４１…カード基体、４３…シリコーン接着
剤、５０…ＩＣカード。DESCRIPTION OF SYMBOLS 1 ... IC chip base, 10 ... Wiring board, 11 ... Insulating board, 12 and 42 ... Depression, 13 ... Copper foil layer, 14 ... Back side copper foil layer, 15 ... Through-hole copper, 16 ... Gold plating layer, 18 ...
Front electrode, 19 ... Back electrode, 20 ... Resin adhesive, 21 ...
Thin metal wire, 22: epoxy resin, 30: electronic device, 40
... crack, 41 ... card base, 43 ... silicone adhesive, 50 ... IC card.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 遠藤 恒雄 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 山浦 正志 埼玉県入間郡毛呂山町旭台15番地 日立東 部セミコンダクタ株式会社内 Ｆターム(参考） 5B035 AA07 BA03 BB09 CA02 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsuneo Endo 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. Address F-term in Hitachi Tobu Semiconductor Co., Ltd. (reference) 5B035 AA07 BA03 BB09 CA02
Claims (1)
により固着された部分を有する電子装置において、前記
配線基板がエポキシ樹脂基板の場合前記樹脂接着剤のヤ
ング率が２５〜２０５kg／mm2 、ガラスエポキシ配線基
板の場合２５〜２７０kg／mm2、Ｃｕコア／エポキシ複
合配線基板の場合２５〜３３０kg／mm2、そしてＣｕ基
板の場合２５〜４３０kg／mm2 の範囲に選択されたこと
を特徴とする電子装置。In an electronic device having an IC chip base having a portion fixed on a wiring substrate with a resin adhesive, when the wiring substrate is an epoxy resin substrate, the resin adhesive has a Young's modulus of 25 to 205 kg / mm 2. , characterized in that the case of a glass epoxy wiring substrate 25~270kg / mm 2, Cu core / epoxy composite wire the substrate 25~330kg / mm 2, and was selected range when 25~430kg / mm 2 of Cu substrate Electronic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11059735A JP2000260907A (en) | 1999-03-08 | 1999-03-08 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11059735A JP2000260907A (en) | 1999-03-08 | 1999-03-08 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000260907A true JP2000260907A (en) | 2000-09-22 |
Family
ID=13121780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11059735A Pending JP2000260907A (en) | 1999-03-08 | 1999-03-08 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000260907A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002323391A (en) * | 2001-04-26 | 2002-11-08 | Kyocera Corp | Package for pressure detector |
| JP2006237231A (en) * | 2005-02-24 | 2006-09-07 | Ngk Spark Plug Co Ltd | Compound wiring board structure |
-
1999
- 1999-03-08 JP JP11059735A patent/JP2000260907A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002323391A (en) * | 2001-04-26 | 2002-11-08 | Kyocera Corp | Package for pressure detector |
| JP2006237231A (en) * | 2005-02-24 | 2006-09-07 | Ngk Spark Plug Co Ltd | Compound wiring board structure |
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