JP2003204020A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thinned semiconductor device with an excellent thermal cycle resistance property, in which heat resistance is suppressed. <P>SOLUTION: This semiconductor device is provided with an insulation substrate with a front surface and a back surface and a circuit pattern and a back surface pattern respectively formed on the front surface and the back surface by using a copper plate. A semiconductor chip is loaded on the circuit pattern, the insulation substrate is composed of aluminum nitride (Si<SB>3</SB>N<SB>4</SB>) and has the thickness of 0.25 mm to 0.35 mm, and the circuit pattern and the back surface pattern have the thickness of 0.3 mm to 0.5 mm. Thus, since solder distortion loaded on solder joining the semiconductor device onto a heat sink is reduced, lead free solder is adopted while maintaining high reliability (thermal cycle resistance property). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an insulating substrate having a front surface and a back surface, and a circuit pattern and a back surface pattern formed on the front surface and the back surface using a copper plate, respectively. The present invention relates to a power semiconductor device having a semiconductor chip mounted thereon.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described with reference to FIGS. A conventional semiconductor device 101 generally includes an insulating substrate 110 made of aluminum nitride (AlN),
On the front surface 111 and the back surface 112, a circuit pattern 113 and a back surface pattern 114 made of a copper plate joined by using an active metal brazing material (not shown) are provided. Insulating substrate 110, circuit pattern 113, and back surface pattern 1
The thicknesses of 14 are 0.635 mm and 0.3 m, respectively.
m and 0.15 mm. Further, a power semiconductor chip (element) 116 is bonded onto the circuit pattern 113 using a solder 115 containing lead as a component (hereinafter, simply referred to as “lead-containing solder”).

As shown in FIG. 9, in this semiconductor device 101, in order to efficiently dissipate the heat generated by the power semiconductor chip 116, a lead is provided on a heat sink 102 made of a metal material having high thermal conductivity such as copper. Bonding is performed using the contained solder 103.

By the way, after the product using such a semiconductor device 101 is discarded, the lead-containing solder contained in the product is melted due to acid rain, and lead, which is a harmful metal, flows out to pollute the environment. However, there is an urgent need to develop so-called environmentally friendly products.

Therefore, a lead-free solder (hereinafter, simply referred to as "lead-free solder") as a substitute for the lead-containing solder.
However, since the lead-containing solder and the lead-free solder have different physical characteristics, they cannot be easily replaced.

In order to show that the lead-containing solder cannot be easily replaced by the lead-free solder, a semiconductor device bonded on the heat sink 102 using the lead-containing solder and a semiconductor device bonded on the heat sink 102 using the lead-free solder. A case where a thermal cycle test is repeatedly performed on the semiconductor device will be described. These semiconductor devices have exactly the same configuration except the material of the solder used. As shown in the graph of FIG. 10, in any semiconductor device, the number of thermal cycles (N: hereinafter, simply referred to as “number of life thermal cycles”) when solder cracks are generated by thermal shock to reach the product life is Solder strain under the insulating substrate (ε, thermal stress of solder)
Increases, it decreases monotonically. However, solder distortion (ε)
Semiconductor devices using lead-free solder when they are the same
The number of lifetime thermal cycles (N ₁ ) of 01 is only about 1/3 of the number of lifetime thermal cycles (N ₂ ) of the semiconductor device 101 using the solder containing lead (N ₁ ≅⅓ × N ₂ ). That is, the reliability of solder joining in the semiconductor device 101 joined on the heat sink 102 using lead-free solder is
It is expected to be significantly reduced.

In other words, the life cycle of lead-free solder
Number of times (N₁) Is the number of life cycles of lead-containing solder (N
_Two), To maintain the same level as
The solder strain (ε₁), Including lead
Yes Solder strain applied to solder (ε ₀) About 60%
Must be (ε₁≒ 0.6 × ε₀).

[0008] Therefore, according to the semiconductor device 101 in a conventional technique for reducing solder strain (epsilon) loaded on the solder 103 for connecting to the heat sink 102, the solder 103 itself thickness of _{(t h)} or thicker, or have thicker thickness of the circuit patterns 113 and the back-side pattern 114 of the insulating substrate 110 _{(t p).}

[0009]

[SUMMARY OF THE INVENTION However, in order to reduce the solder strain (epsilon), when the thickness of the solder 103 itself thickness (t _h), as shown in FIG. 6, the solder 103
The thermal resistance (R _h ) of the circuit pattern 113 increases.
When the thickness (t _p ) of the back surface pattern 114 is increased, similarly, as shown in FIG.
The thermal resistance (R _p ) of 3,114 increases.
Thermal resistance (R _h ) of solder 103 or patterns 113, 1
When the thermal resistance (R _p ) of 14 increases, the semiconductor device 101
The heat dissipation effect obtained by joining the heat sink 102 to the heat sink 102 is impaired.

Further, while the thermal resistance (R _h ) of the solder 103 and the thermal resistance (R _p ) of the patterns 113 and 114 are increased, the insulating substrate 110 is thinned to reduce its thermal resistance (R _s ). Accordingly, an attempt has been made to reduce the thermal resistance of the semiconductor device 101 as a whole. However,
As shown in FIG. 3, when the insulating substrate 110 made of aluminum nitride (AlN) has a small thickness, the degree (C) of cracking due to thermal shock increases, and the long-term reliability of the insulating substrate 110 is impaired. was there.

Therefore, the present invention has been made in order to solve these problems, and it is possible to reduce the heat resistance by reducing the wall thickness.
It is an object of the present invention to provide a semiconductor device having good heat cycle resistance. With this, using lead-free solder,
Even when the semiconductor device is bonded to the heat sink, the solder strain applied to the lead-free solder can be reduced, so that the thermal cycle resistance of the lead-free solder can be improved and high reliability can be realized.

[0012]

According to the present invention as set forth in claim 1, an insulating substrate having a front surface and a back surface, and a circuit pattern and a back surface pattern formed on the front surface and the back surface using a copper plate, respectively. And a semiconductor device having a semiconductor chip mounted on a circuit pattern, the insulating substrate is made of aluminum nitride (Si ₃ N ₄ )
It is possible to provide a semiconductor device having a thickness of mm to 0.35 mm and the circuit pattern and the back surface pattern having a thickness of 0.3 mm to 0.5 mm. In this way, by using a ceramic material having high toughness, it is possible to realize a semiconductor device which has a thinner insulating material and suppresses thermal resistance, and which has good thermal cycle resistance. Further, in this semiconductor device, since its thermal resistance is small, it is possible to reduce the solder strain applied to the solder bonded on the heat sink. Therefore, even if this semiconductor device is joined to the heat sink using not only lead-containing solder but also lead-free solder, good reliability (heat cycle resistance) as a semiconductor device can be maintained.

According to the second aspect of the present invention, it is possible to provide a semiconductor device in which the thickness of the circuit pattern is equal to or thinner than the thickness of the back surface pattern. Accordingly, during the reflow process, the semiconductor device can be curved so as to have a downward convex shape, and bubbles generated in the solder can be easily removed from the solder.

According to the third aspect of the present invention, it is possible to provide a semiconductor device further including a conductive bonding member arranged on the back surface pattern so as to be bonded on a metal substrate. Thereby, the semiconductor device can be bonded to the heat sink via the conductive bonding member (solder).

According to the fourth aspect of the present invention, it is possible to provide a semiconductor device in which the conductive joining member is made of lead-free solder. As a result, as described above, since the semiconductor device has a low thermal resistance, lead-free solder can be used as the solder to be bonded onto the heat sink while maintaining good reliability (heat cycle resistance).

According to the present invention described in claim 5, it is possible to provide a semiconductor device in which bumps having a predetermined size are included in the conductive adhesive member. This allows
The thickness of the solder between the back surface pattern and the heat sink can be made constant. Therefore, it is possible to prevent the occurrence of solder cracks in the thin peripheral portion of the solder due to the uneven thickness of the solder.

According to the present invention described in claim 6, it is possible to provide a semiconductor device in which the conductive adhesive member has a thickness of 0.25 mm to 0.40 mm. Thereby, the thickness of the solder can be made as thick as possible so as to reduce the solder distortion within the range where the thermal resistance of the solder is allowed.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device according to the present invention will be described below with reference to FIGS.
This semiconductor device 1 is generally composed of an insulating substrate 10 made of silicon nitride (Si ₃ N ₄ ), and a copper plate joined on its front surface 11 and back surface 12 by using an active metal brazing material (not shown). The thickness of the insulating substrate 10 having the circuit pattern 13 and the back surface pattern 14 is 0.25 mm to 0.3.
When the thickness is 5 mm, both the circuit pattern 13 and the back surface pattern 14 have a thickness of 0.30 mm to 0.50 mm. In addition, lead-free solder (composition: Sn
The power semiconductor chip (element) 16 is bonded onto the circuit pattern 13 by using 2 to 4 Ag 0.5 to 0.75 Cu) 15.

Further, as shown in FIG. 2, this semiconductor device 1 is mounted on a heat sink 2 made of a metal material such as copper having high thermal conductivity in order to efficiently dissipate the heat generated by the power semiconductor chip 16. , Using the lead-free solder 3 having the above composition.

The solder for joining the power semiconductor chip 16 onto the circuit pattern 13 is the semiconductor chip joining solder 15, and the solder for joining the semiconductor device 1 onto the heat sink 2 is the semiconductor device joining solder 3 In the following description, the “solder” refers to the semiconductor device bonding solder 3 unless otherwise specified.

In the present invention, the thickness of the insulating substrate 10 is
The reason for setting 0.25 mm to 0.35 mm is as follows.
Explained below. Silicon nitride (Si of the present invention_ThreeN_Four) From
The bending strength of the insulating substrate 10 is about 700.
At 800MPa, from conventional aluminum nitride (AlN)
Bending strength of the insulating substrate 110 (about 350 to 400
2 times higher than the (MPa). Similarly, the insulating substrate 1 of the present invention
The flexure resistance of 0 is about 4 times that of the conventional insulating substrate 110.
High degree. That is, the insulating substrate 10 (Si
_ThreeN_Four) Is compared with the conventional insulating substrate 110 (AlN)
The fracture toughness is very high, so cracking
Without, it can be made thinner.

Further, the insulating substrate 10 (Si
₃ N ₄ ) has a thermal conductivity (λ ₁ ) of about 50 to 100 W / (m
.K), and the thermal conductivity (λ ₂ ) of the conventional insulating substrate 110 made of aluminum nitride (AlN) is about 130 to 180 W.
/ (M · k). In general, the thermal resistance (R), thickness (t), and thermal conductivity (λ) of the insulating substrate satisfy the following relational expression, as shown in FIG. (Formula 1) R = t / λ Therefore, the insulating substrate 10 made of silicon nitride (Si ₃ N ₄ ) of the present invention is the same as the conventional insulating substrate 110 (t ₂ = 0.635 mm) made of aluminum nitride (AlN). Or the insulating substrate 10 of the present invention so as to have a smaller thermal resistance (R).
The upper limit of the thickness (t ₁ ) of the was set to 0.35 mm. Also,
When the thickness of the insulating substrate 10 is reduced, its withstand voltage is lowered, but in order to secure a sufficient withstand voltage, the lower limit value of the thickness (t ₁ ) of the insulating substrate 10 is set to 0.25 mm.

As described above, since the insulating substrate 10 of the present invention is composed of silicon nitride (Si ₃ N ₄ ), it maintains good reliability in the practical range (0.25 mm to 0.35 mm). However, it is possible to reduce the heat resistance by making it thinner. By suppressing the thermal resistance of the insulating substrate 10, the thermal resistance of the entire semiconductor device 1 can be reduced and the solder strain (ε) applied to the solder 3 can be relaxed. Therefore, lead-free solder can be used as the solder 3 for joining the semiconductor device 1 to the heat sink 2.

The copper patterns forming the circuit pattern 13 and the back surface pattern 14 of the present invention both have a thickness of 0.30 mm to 0.50 mm, as described above.
And the backside pattern 1
4 is designed thicker than the conventional one.

As shown in FIG. 4, the thickness (t
Since _p) and the solder 3 solder strain (epsilon _h) has a negative correlation, in order to mitigate the solder 3 solder strain (epsilon _h) is better to more increase the thickness (t _p) of the copper pattern Is preferred.
Further, as is clear from FIG. 5, when the copper pattern is made thicker, the linear expansion coefficient of the entire insulating substrate 10 including the copper patterns 13 and 14 becomes higher.
The difference from the coefficient of linear expansion of No. 3 becomes small, and similarly, the solder strain (ε) of the solder 3 can be reduced.

On the other hand, on the other hand, the thickness (t
_{Since p 1} ) and its thermal resistance (R _p ) have a positive correlation as shown in FIG. 4, it is preferable that the back surface pattern 14 is thin in order to lower the thermal resistance (R _p ). Further, if the back surface pattern 14 is too thick, the stress on the insulating substrate 10 becomes excessive.

Therefore, in FIG. 4, the thickness of the copper pattern is set to 0.30 mm to 0.50 mm as a range in which the solder strain (ε _h ) of the solder 3 is reduced without increasing the thermal resistance (R _p ) too much. did.

By the way, the insulating substrate 10 is connected through the solder 3.
When heating in the reflow process to bond the solder to the heat sink 2, bubbles (voids) are generated in the solder 3. However, when the semiconductor device 1 is bent downward (toward the heat sink 2) so as to have a convex shape during heating, the bubbles are likely to escape from the solder 3. Therefore, in the above description, the circuit pattern 13 and the back surface pattern 14 are described as having the same thickness, but during the reflow process,
It is more preferable that the thickness of the circuit pattern 13 is made smaller than the thickness of the back surface pattern 14 so that the semiconductor device 1 has a convex shape in the downward direction so that bubbles can easily escape from the solder 3.

Further, as shown in FIG. 6, the solder 3 in the thickness (t _h) is between the thermal resistance (R _h) have a positive correlation, between the solder strain (epsilon _h) Has a negative correlation with. Accordingly, the solder 3 in the thickness _{(t h),} to the extent that the heat resistance _{(R h)} is permitted, must be as thick as possible to reduce the solder strain (epsilon _h), about 0.25
It is set to mm to 0.4 mm.

When the semiconductor device 1 of the present invention is bonded to the heat sink 2 via the solder 3, the semiconductor device 1 may be bonded with an inclination with respect to the thickness direction of the solder 3. In this case, the thickness of the solder 3 becomes non-uniform, the thin peripheral edge (corner) of the solder 3 is more vulnerable to thermal shock, and solder cracks easily occur at this peripheral edge. Therefore,
It is necessary to make the thickness of the solder 3 uniform so that the solder 3 is not cracked. Therefore, as shown in FIG. 7, it is extremely possible to form the wire bumps 17 made of aluminum (Al) on the back surface pattern 14 of the insulating substrate 10 to make the thickness of the solder 3 between the back surface pattern 14 and the heat sink 2 constant. desirable.

[0031]

According to the present invention as set forth in claim 1, by using a ceramic material having high toughness, the insulating material can be made thinner and the thermal resistance can be suppressed, and the semiconductor having good heat cycle characteristics. The device can be realized. Further, in this semiconductor device, since its thermal resistance is small, it is possible to reduce the solder strain applied to the solder bonded on the heat sink. Therefore, not only lead-containing solder but also lead-free solder can be used to bond this semiconductor device to a heat sink, and still maintain good reliability (heat cycle resistance) as a semiconductor device.

According to the second aspect of the present invention, during the reflow process, the semiconductor device can be curved so as to have a downward convex shape, and bubbles generated in the solder can be easily removed from the solder.

According to the third aspect of the present invention, the semiconductor device can be bonded to the heat sink via the conductive bonding member (solder).

According to the fourth aspect of the present invention, as described above, since the semiconductor device has a small thermal resistance, the solder to be joined on the heat sink while maintaining good reliability (heat cycle resistance). As for, lead-free solder can be adopted.

According to the fifth aspect of the present invention, the thickness of the solder between the back surface pattern and the heat sink can be made constant. Therefore, it is possible to prevent the occurrence of solder cracks in the thin peripheral portion of the solder due to the uneven thickness of the solder.

According to the sixth aspect of the present invention, it is possible to make the thickness of the solder as thick as possible so as to reduce the solder distortion within a range where the thermal resistance of the solder is allowed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device and a heat sink according to one embodiment of the present invention, showing a state before joining them.

FIG. 2 is a cross-sectional view after joining the semiconductor device and the heat sink shown in FIG.

FIG. 3 is a graph showing a correlation between the thickness of an insulating substrate and thermal resistance and the degree of crack occurrence due to thermal cycling.

FIG. 4 is a graph showing a correlation between a copper pattern and thermal resistance and solder strain.

FIG. 5 is a graph showing the linear expansion coefficient of each component of the semiconductor device according to the present invention and the prior art.

FIG. 6 is a graph showing a correlation between solder thickness and solder strain and thermal resistance.

FIG. 7 is a cross-sectional view similar to FIG. 2, showing wire bumps formed in solder that joins a semiconductor device to a heat sink.

FIG. 8 is a cross-sectional view of a semiconductor device and a heat sink according to the prior art, showing a state before joining them.

9 is a cross-sectional view after the semiconductor device and the heat sink shown in FIG. 8 have been joined.

FIG. 10 is a graph showing the correlation between the number of thermal cycles (logarithmic scale) and solder strain that reach the product life due to solder cracks.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Heat sink, 3 ... Solder for joining semiconductor devices, 10 ... Insulating substrate, 11 ... Board front surface, 12 ... Board back surface, 13 ... Circuit pattern, 14 ... Back surface pattern, 1
5 ... Solder for joining semiconductor chips, 16 ... Semiconductor chips (elements) for power, 17 ... Wire bumps.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasumi Uegai             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F-term (reference) 5E322 AA01 AA11 AB02 AB07                 5F036 AA01 BB08 BC06 BD01 BD14

Claims (6)

[Claims] 1. A semiconductor device having an insulating substrate having a front surface and a back surface, a circuit pattern and a back surface pattern formed on the front surface and the back surface using a copper plate, and mounting a semiconductor chip on the circuit pattern. In, the insulating substrate is made of aluminum nitride (Si ₃ N ₄ ),
A semiconductor device having a thickness of 0.25 mm to 0.35 mm, wherein the circuit pattern and the back surface pattern have a thickness of 0.3 mm to 0.5 mm. 2. The semiconductor device according to claim 1, wherein the thickness of the circuit pattern is equal to or thinner than the thickness of the back surface pattern. 3. The semiconductor device according to claim 1, further comprising a conductive bonding member arranged on the back surface pattern so as to be bonded on a metal substrate. 4. The semiconductor device according to claim 3, wherein the conductive joining member is made of lead-free solder. 5. The semiconductor device according to claim 3, wherein bumps having a predetermined size are included in the conductive adhesive member. 6. The semiconductor device according to claim 3, wherein the conductive adhesive member has a thickness of 0.25 mm to 0.40 mm.