JP2000243802A - Manufacture and equipment of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing equipment which is capable of manufacturing a semiconductor device in a shorter time and ensuring it of a high yield. SOLUTION: A manufacturing equipment is quipped with a first processing unit 200 which comprises a first processing chamber 221 and a second processing chamber 231 that are hermetically connected together through the intermediary of a first common chamber 201 and a first substrate loading/unloading chamber 221, a second processing unit 300 which comprises a third processing chamber 321 and a fourth processing chamber 331 which are hermetically connected together through the intermediary of a second common chamber 301 and a second loading/unloading chamber 311, a third common chamber 110 which is located between the substrate loading/unloading chambers 211 and 311 and hermetically connected to them, a third substrate loading chamber 111 which loads a processed substrate that is fed from outside into the third common chamber 110, and a transfer means 113 which transfers the processed substrate arranged inside the third common chamber 110 to the first to third loading/ unloading chamber, 111, 211, and 311.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method and an apparatus for manufacturing a semiconductor device such as a thin film transistor.

[0002]

2. Description of the Related Art A technique for forming a semiconductor device such as a thin film transistor (TFT) on an insulating substrate such as glass or quartz has been used in various fields including an active matrix type liquid crystal display device, and has attracted attention.

In a conventional TFT, a hydrogenated amorphous silicon (a-Si: H) thin film or the like is used for an active layer.
Source and drain electrodes are arranged on an i: H thin film via an ohmic contact layer such as an n ⁺ a-Si: H thin film. In recent years, TFTs for switches
Not only that, since part of the signal processing circuit is composed of TFTs, the mobility of electrons and holes is high, and the n-channel
Polycrystalline silicon (p-Si) capable of p-channel operation
A TFT using a thin film as an active layer is used.

An example of a method for manufacturing such a p-Si thin film transistor will be briefly described. For example, an amorphous silicon (a-Si) thin film is formed on a transparent glass substrate to a desired thickness under reduced pressure plasma CVD (Chemical Vapor Deposition).
ELA (Excimer Laser Anneali)
ng) to form a polycrystalline silicon (p-Si) thin film. And this p-Si
After patterning the thin film, a gate insulating film is deposited thereon, and a metal film such as an Al alloy is further deposited.

A resist pattern is provided on the metal film, and the metal film is subjected to RIE (Re
Active ion etching) or the like is performed to form a gate electrode. After the resist pattern is removed by ashing, the p-Si thin film in the source / drain region is ion-doped with impurities using the gate electrode as a mask.

Thereafter, the doped impurities are electrically activated by performing a heat treatment at a temperature of 500 ° C. Then, an interlayer insulating film is deposited thereon, contact holes are respectively formed in the gate insulating film and the interlayer insulating film on the source and drain regions by wet etching, and a drain electrode electrically connected to the drain region.
A source electrode electrically connected to the source region is formed, thereby completing a thin film transistor.

[0007]

According to the above-described method of manufacturing a thin film transistor, each of the film forming step, the polycrystallization step, the patterning step, the ion doping / activating step, and the complicated inspection step are performed individually. Done in the device. For this reason, the manufacture of a semiconductor device typified by a thin film transistor requires an expensive individual device that requires a large and clean area, and further requires a long manufacturing time.

In order to secure and maintain this clean area, it is necessary to construct a vast clean room, and in order to maintain cleanness (cleanliness) and optimum temperature and humidity, enormous energy and cost are required for air conditioning power. It is the present situation.

In addition, semi-finished products remain between the manufacturing apparatuses, and this undesired retention causes adhesion of fine particles in the air and adsorption of moisture and organic gas on the surface of the element region of the substrate.
This causes a reduction in manufacturing yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned technical problems, and has a method and a method for manufacturing a semiconductor device capable of significantly reducing the time required for manufacturing, the number of expensive devices, and the costly clean room area. It is intended to provide a device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and an apparatus for manufacturing a semiconductor device, which reduce undesirable stagnation of semi-finished products in the course of manufacturing and thereby achieve a high manufacturing yield.

Further, according to the present invention, by performing an inspection during manufacturing, the flow of defective products into the next process can be suppressed,
It is an object of the present invention to provide a method and an apparatus for manufacturing a semiconductor device with improved productivity. Another object of the present invention is to provide a method and an apparatus for manufacturing a semiconductor device in which costs such as power required for maintaining cleanness are sufficiently reduced.

[0013]

According to the first aspect of the present invention,
Forming a non-single-crystal silicon thin film on an insulating substrate in a first process chamber among first to third process chambers which are hermetically connected to each other via a common chamber; and moving the substrate to a second process chamber. Irradiating the non-single-crystal silicon thin film with light energy to form a recrystallized silicon thin film; and moving the substrate to a third process chamber and non-contactly inspecting film physical properties such as a crystallization state of the recrystallized silicon thin film And a method of manufacturing a semiconductor device.

According to a fifth aspect of the present invention, a thin film formed on an insulating substrate is patterned into a desired shape in a first process chamber of first and second process chambers which are hermetically connected to each other via a common chamber. And a step of moving the substrate to a second process chamber and inspecting the shape and characteristics of the patterned thin film.

According to a sixth aspect of the present invention, there is provided a first processing unit including first and second process chambers and a first substrate loading / unloading chamber hermetically connected to each other via a first common chamber; Third and fourth airtightly connected to each other via a common chamber
A second processing unit including a process chamber and a second substrate loading / unloading chamber; a third common chamber airtightly communicated between the first and second substrate loading / unloading chambers; A third substrate loading / unloading chamber to be loaded into the third common chamber; and transfer means disposed in the third common chamber for transferring the substrate to be processed between the first to third loading / unloading chambers. An apparatus for manufacturing a semiconductor device, comprising:

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to an example of manufacturing an array substrate for a TFT-LCD. FIG. 1 shows a manufacturing apparatus 10 used in this embodiment.
0 is a schematic configuration diagram of a pentagonal substrate transfer chamber 110.
And a first vacuum processing unit 200 that communicates with one side of the substrate transfer chamber 110 in a state where cleanliness is maintained, and a second vacuum processing unit 300 that similarly communicates with the other side.
And a resist processing unit 4 similarly communicated with the other side.
00 and a wet processing unit 500 similarly connected to the other side.

The substrate transfer room 110 is a clean room maintained and managed in class 100 in this embodiment.
The cassette C containing substrates is transferred from the AGV to the substrate transfer chamber 1
The cassette station 111 has a three-position position that allows loading and unloading to and from the cassette 10. Of the three-position cassette stations 111, one cassette C sends out the substrate 10 before processing, one cassette C receives the substrate 10 after processing, and the other cassette C loads and unloads the substrate. It is for buffers that can be used. Here, it is possible to increase the number of cassettes C.
The number is desirably 5 or less. Further, the substrate transfer chamber 110
Inside, a double arm type robot arm 113 for transporting a substrate from each cassette C to each processing unit.
Is arranged.

The first vacuum processing unit 200 has an octagonal common chamber 201 provided with a transfer robot 202 at substantially the center.
A load / unload chamber 211 disposed between the common chamber 201 and the substrate transfer chamber 110 to control the loading / unloading of substrates; and seven process chambers 221 and 231 airtightly connected to the common chamber 201, respectively. , 241, 251, 26
1,271,281.

Process chambers 221, 231, 251, 27
1 and 281 have substantially the same configuration. For example, as shown in FIG. 2, a susceptor 141 for supporting the substrate 10, a vacuum chamber 143 for accommodating the susceptor 141, and a vacuum chamber A pump 145 communicating with the vacuum chamber 143 and maintaining a vacuum in the chamber 143; a gas supply system 147 communicating with the vacuum chamber 143 and supplying a desired gas into the chamber 143;
A dielectric 149 made of ceramic or the like airtightly arranged on the upper surface facing the susceptor 141
An antenna 151 for applying a high-frequency wave arranged on the antenna 49;
First high frequency source 153 for applying high frequency to antenna 151
And a second high frequency source 155 connected to the susceptor 141
And a control unit 157 for controlling the first and second high-frequency sources 153 and 155. The other process chambers 231, 251, 271 and 281 have substantially the same configuration.
Hereinafter, description will be made using the same reference numerals. If the process chamber functions as ion implantation instead of ion doping, a mass separation function may be added to the process chamber.

The process chamber 241 includes, as shown in FIG.
A susceptor 141 that movably supports the substrate 10, a vacuum chamber 143 that houses a laser irradiation unit 161 that irradiates a strip of laser light, and an ELA chamber that communicates with the vacuum chamber 143 and maintains a vacuum in the chamber 143. And a laser source 163 communicating with the vacuum chamber 143 and guiding the laser light. The process chamber 241 may be processed in a normal pressure state or a positive pressure state in addition to the processing in a reduced pressure state.

The process room 261 is an inspection room,
Here, the crystallization state and the like can be inspected.
Thereby, the first vacuum processing unit 200 constitutes a multi-cluster unit for forming and processing a silicon thin film and an inorganic insulating film such as film formation, etching, ashing or ion doping, and further inspection.

The second vacuum processing unit 300 includes a heptagonal common chamber 301 provided with a transfer robot 302 at substantially the center.
And a load / unload chamber 311 arranged between the common chamber 301 and the substrate transfer chamber 110 to control the loading and unloading of substrates, and six process chambers 321 and 331 airtightly connected to the common chamber 301, respectively. , 341, 351, 36
1 and 371.

The process chambers 321, 331, and 371 have substantially the same configuration as the process chamber 211 of the first vacuum processing unit 200 and the like, and a description thereof will not be repeated. The process chamber 341 is an annealing chamber, and the process chamber 351 constitutes an inspection chamber like the process chamber 261 of the first vacuum processing unit 200 described above. The process chamber 361 is a sputter deposition chamber.

The resist processing unit 400 includes a common chamber 401 provided with a transfer robot 402 at substantially the center, and a load / unloader disposed between the common chamber 401 and the substrate transfer chamber 110 for controlling the loading and unloading of substrates. A load chamber 411,
The resist coating chambers 421a and 421b, which are arranged on both sides of the common chamber 401 and are configured by spin processing units, and the exposure chamber 4
31a and 431b, and developing chambers 441a and 441b composed of spin processing units.

The wet processing unit 500 includes a common chamber 501 having a transfer robot 502 at substantially the center,
A load / unload chamber 51 which is arranged between the common chamber 501 and the substrate transfer chamber 110 and controls loading and unloading of substrates.
1 and a wet processing chamber 521 and a wet etching chamber 531 disposed on both sides of the common chamber 501.

In the manufacturing apparatus 100 of this embodiment, each processing unit 200, 30 is placed in a pentagonal substrate transfer chamber 110.
0, 400, and 500 are connected in a state where the cleanliness is maintained, and in the substrate transfer chamber 110, each processing unit 20 is connected.
Since the substrate is transported between 0, 300, 400, and 500, a region requiring cleanliness can be extremely reduced. The introduction of the manufacturing apparatus 100 reduces the construction cost of a clean room, and further, the power (water, electricity, gas, etc.) cost for maintaining and managing cleanliness and maintaining and managing temperature and humidity. Was almost halved.

Further, according to the apparatus 100, the residence time of the substrate between the steps is reduced, and furthermore, the substrate is kept in an environment of class 1000 or less, for example, class 100, between the steps. The effect was significantly reduced.

Further, according to the apparatus 100, the residence time of the substrate between the processes is reduced, and further, the substrate is always kept in a class 100 environment between the processes, so that the influence of contamination and the like is extremely reduced. We were able to.

In this embodiment, the substrate transfer chamber 110 is
Each processing unit 200, 300, 40
Although 0,500 is communicated, a plurality of processing units may be further communicated in a state where the cleanliness is maintained, and such apparatuses may be similarly connected.

In the above example, the process chamber 221
Although the antenna 151 for applying a high frequency is disposed outside the vacuum chamber 143 with the dielectric 149 therebetween, the antenna 151 may be disposed in the vacuum chamber 143 as shown in FIG.
That is, with the configuration using the antenna-insertion-type inductively-coupled plasma, high-density plasma can be generated at low pressure, and power consumption can be further reduced.

Then, the process chambers 221, 231, 251, 271, 281 and 32 of the manufacturing apparatus 100 described above.
1, 331, 371 are formed and etched (CDE,
RIE), ashing, or ion doping. Therefore, depending on the type of product to be relocated, the respective process chambers 221, 231, 25
1 for different uses or each process room 22
For example, a plurality of processes are continuously performed in each of 1, 1, 31 and 251. Thus, the ability to respond to a change in the manufacturing process is high, the setup loss can be reduced, and a manufacturing line with high productivity can be realized.

Next, taking an example of a method of manufacturing a thin film transistor having a MOS structure by the above-described device 100, a method of manufacturing an array substrate for a p-Si TFT-LCD integrated with a drive circuit will be described.
This will be described with reference to the drawings.

First, the cassette C transported by the AGV is placed in the cassette station 111 which is shielded from the inside of the substrate transfer chamber 110. The substrate 10 housed in the cassette C has an outer dimension of 500 mm × 600 mm.
And a transparent glass substrate 10 having a thickness of 0.7 mm,
A two-dimensional barcode indicating the specification is written by laser light at the end of each substrate so that the product specification of the TFT-LCD to be made can be determined. The cassette station 111 is shielded from the outside and communicates with the inside of the substrate transfer chamber 110.

Next, the gate valve 211a of the load lock chamber 211 of the first vacuum processing unit 200 is opened, and the substrate 10 previously cleaned by the robot arm 113 is carried from the cassette C into the load lock chamber 211.

Then, the gate valve 211a is closed, and the pressure in the load lock chamber 211 is reduced to, for example, 10 mTorr, which is substantially equal to that of the common chamber 201. Thereafter, the gate valve 211b is opened, the substrate 10 in the load lock chamber 211 is loaded onto the susceptor 141 of the process chamber 221 by the transfer robot 203, the gate valve 221a of the process chamber 221 is closed, and the process chamber 221 is airtightly closed. maintain.

The process chamber 221 functions as a film forming chamber. As shown in FIG. 5A, a 50 nm-thick amorphous silicon (a-S
i) The thin film 20 is deposited by a low pressure plasma CVD method at a substrate temperature of 420 ° C. Specifically, the first high-frequency source 15
A high frequency of 13.56 MHz at 150 W was applied to the sample No. ₃ and SiH ₄ was supplied at 100 scc from the gas supply system 147.
5,000 sccm of m and Ar gas are supplied to stabilize the plasma discharge. Then, the a-Si thin film 20 was deposited by a so-called reduced pressure plasma CVD method. At this time, the a-Si: H thin film 2 was used to prevent contamination from the glass substrate 10.
Silicon oxide (SiO ₂ ) as an undercoat layer
A film or a silicon nitride (SiNx) film may be formed continuously by changing the gas type and the high frequency power.

After the inside of the process chamber 221 is evacuated, the gate valve 221a is opened, and the glass substrate 10 is loaded onto the susceptor 140 of the process chamber 231 by the transfer robot 202. Further, the gate valve 231a of the process chamber 231 is opened. Close and keep this process chamber 231 airtight.

The process chamber 231 is provided with an ion doping (I / I) for doping impurity ions into the a-Si thin film 20 for controlling the threshold value Vth of the thin film transistor.
D) Function as a room. That is, the first high-frequency source
After applying a high frequency of 13.56 MHz at 000 W and supplying 20 sccm of B ₂ H ₆ from the gas supply system 147 to stabilize the plasma discharge, the second high frequency source 155 to 1500 W from the second high frequency source 155 based on the control of the control unit 157. At 2M
A high frequency of Hz is applied to the susceptor 141. The B ₂ H ₆ gas is ionized or radicalized by the plasma, and the substrate 1
0 is drawn toward the substrate 10 by a self-bias of about −200 V, and boron (B) ions and radicals are
The thin film 20 is ion-doped. The doping amount was controlled by the processing time.

After once exhausting the residual gas in the process chamber 231, the gate valve 231 a is opened and the transfer robot 2
02 through the common chamber 201 and the above process chamber 23
1 to the process chamber 241. Then, the gate valve 241a of the process chamber 241 is closed,
In this process chamber 241, as shown in FIG.
-Si thin film 20 is coated with ELA (Excimer Laser Annealin).
g) to form a polycrystalline silicon (p-Si) thin film 22. That is, the process chamber 241 functions as a crystallization chamber, and lamp annealing or the like may be used instead of ELA. In this embodiment, the ELA
In this method, a long beam of 0.3 × 400 mm was used, and the beam was scanned at a pitch of 15 μm to perform crystallization.

Then, the gate valve 241a is opened, and the substrate is carried into the process chamber 261 which functions as the inspection room by the transfer robot 202, and the p-Si thin film 22 is removed by using an optical measuring instrument such as a spectroscopic ellipsometer. Inspect the crystallization state. That is, when it is determined that crystallization is insufficient based on the measured value of the reflection spectral intensity that changes depending on the size of the crystal grain, recrystallization is performed again in the process chamber 241. After the inspection is completed, the substrate 10 is carried into the load lock chamber 211, the gate valve 211b is closed, the load lock chamber 211 is set to the atmospheric pressure, the gate valve 211a is opened, and the loading of the resist processing unit 400 is performed by the robot arm 113. The substrate 10 is carried into the lock chamber 411.

The substrate 10 is carried into the resist coating chamber 421a by the robot arm 402, and the resist is spin-coated. Next, the exposure chamber 43 is moved by the robot arm 402.
The substrate 10 is carried into the substrate 1a, and a desired pattern is exposed based on a predetermined process photomask based on the barcode of the substrate 10. The fact that the predetermined exposure process has been completed in parallel
Record in a dimensional barcode. The substrate 10 is carried into the developing chamber 441a by the robot arm 402, and is subjected to development processing to form resist patterns 31 and 41. Thereafter, the substrate 10 is carried into the load lock chamber 411 of the resist processing unit 400 by the robot arm 402.

The substrate 10 is transferred to the first processing unit 20 again.
The wafer is carried into the process chamber 251 functioning as an etching chamber of the “0”. The gate valve 25 of the process chamber 251
1a, the process chamber 251 is kept airtight, and as shown in FIG.
Using the p-Si thin film 22 as a mask, CF ₄ and O
Patterning into island-like p-Si thin films 30 and 40 by CDE (Chemical Dry Etching) using _two gases,
Further, the flow ratio is changed, and subsequently, the resists 31 and 41 are removed by ashing. That is, the first high-frequency source 153 has 20
While applying a high frequency of 13.56 MHz at 00 W,
The gas supply system 147 supplies CF ₄ at 120 sccm and O ₂ gas at 300 sccm to stabilize the plasma discharge. At this time, the self-bias of the substrate 10 is substantially zero,
The p-Si thin film 22 is patterned in a CDE mode based on CF ₄ and O ₂ gas ionized or radicalized by plasma. The first high-frequency source 153 receives 200
While applying a high frequency of 13.56 MHz at 0 W, 50 sccm of CF ₄ and 950 sccm of O ₂ gas are supplied from the gas supply system 147, and the resists 31 and 41 are subsequently supplied.
Ashing was performed.

Then, the substrate 10 is carried into a process chamber 271 functioning as a film forming chamber, and the substrate 10 is set as shown in FIG.
A TEOS film 50 and a silicon nitride (SiNx) film are successively deposited on the Si thin films 30 and 40 as a diffusion barrier layer 55 by a plasma CVD method as a gate insulating film. Specifically, the first high-frequency source
A high frequency of 3.56 MHz was applied, and TEOS of 70 sccm and O ₂ of 5000 s were supplied from the gas supply system 147.
ccm to stabilize the plasma discharge. Then, a TEOS thin film 50 is deposited to a thickness of 200 nm by a so-called low-pressure plasma CVD method, and a SiH ₄
Is supplied at 200 sccm, NH ₃ is supplied at 4500 sccm, and N ₂ is supplied at 5,000 sccm, and the diffusion barrier layer 55 of SiNx is supplied.
Was deposited to a thickness of 50 nm.

Thereafter, the substrate 10 is again carried into the load lock chamber 411 of the resist processing unit 400 via the load lock chamber 211, and the resist is applied in the resist coating chamber 421b, and the bar code of the substrate 10 is exposed in the exposure chamber 431b. Exposure of a desired pattern based on a predetermined photomask and development in a developing chamber 441b to form a resist pattern (not shown), and then a substrate is placed in a load lock chamber 311 of the second processing unit 300. 10 is carried in. The completion of the predetermined exposure step is recorded in a two-dimensional barcode in parallel with the above exposure.

The gate valve 211a of the atmospheric pressure load lock chamber 311 of the second vacuum processing unit 300 is closed, and the pressure of the load lock chamber 311 is reduced to, for example, 10 mTorr, which is substantially equal to that of the common chamber 301. And the gate valve 31
1b is opened, and the substrate 10 in the load lock chamber 311 is moved by the transfer robot 303 to the susceptor 14 in the process chamber 321.
1 and the gate valve 321 of the process chamber 321
is closed to keep the process chamber 321 airtight.

The process chamber 321 functions as an etching chamber. Similar to the process chamber 251, the diffusion barrier layer 55 is patterned based on the above-described resist pattern, and the resist pattern is removed by ashing. The diffusion barrier layer 57 is selectively formed as shown in FIG.

Then, the substrate 10 is transported to the wet processing unit 500, and a silane-based coupling material is spray-sprayed on the surface of the substrate 10 in the wet processing chamber 521 to perform a surface treatment, so that a material other than the diffusion barrier layer 57 is formed. The surface of the region is selectively silanized.

Again, the substrate 10 is carried into the process chamber 331 of the second vacuum processing unit 300 functioning as a film forming chamber. Then, a Cu layer is selectively deposited on the diffusion barrier layer 57 by decomposing the organic Cu compound by a low-pressure plasma CVD method at a substrate temperature of 200 ° C. Then, heat treatment is performed in a process chamber 341 functioning as an annealing chamber, and a gate wiring 59 made of Cu is formed as shown in FIG.

Then, the substrate 10 is transferred to a process chamber 351 functioning as an inspection room, and the gate wiring 59 is inspected, that is, the resistance of the Cu film and the presence or absence of disconnection are electrically determined. The inspection is performed by comparing the contour with a previously stored pattern.

Thereafter, the resist processing unit 400 is added to the substrate 10 determined to be non-defective as described above.
A resist pattern 60 is selectively formed on the p-Si thin film 40 by using the process chamber 281 functioning as an ion doping (I / D) chamber of the first vacuum processing unit 200.
Carry in. In the process chamber 281, the first high-frequency source 15
After applying a high frequency of 13.56 MHz at 2000 W to ₃ and supplying 20 sccm PH ₃ from the gas supply system 147 to stabilize the plasma discharge, the second high frequency source 155 to 1500 W from the second high frequency source 155 based on the control of the control unit 157. 2
A high frequency of MHz is applied to the susceptor 141. The PH ₃ gas is ionized or radicalized by the plasma, and the substrate 1
It is pulled into the substrate 10 side by a self-bias of about -200 V of 0, thereby achieving ion doping. In this example, the dose of phosphorus (P) ions was controlled to 1 × 10 ¹⁵ ions / cm ² by controlling the time. This allows
In the p-Si thin film 30, source and drain regions 31, 3
3 and a channel region 35 were formed.

Then, the residual gas in the process chamber 281 is exhausted, and the first high-frequency source 153 is supplied with 13.56 M at 2000 W.
While applying a high frequency of Hz, 50 sccm of CF ₄ and 950 sccm of O ₂ are supplied from the gas supply system 147 to stabilize the plasma discharge. At this time, the self-bias of the substrate 10 is substantially zero, and the resist 60 is removed by ashing in the CDE mode based on CF ₄ and O ₂ gas ionized or radicalized by plasma.

Thereafter, the residual gas in the process chamber 281 is exhausted, the gate valve 231a is opened, and the substrate 10 is carried out to the load lock chamber 211 via the common chamber 201 by the transfer robot 202. Further, the substrate 10 is conveyed to the resist processing unit 400, selectively forms a resist pattern 61 on the p-Si thin film 30, and is carried into the process chamber 231 of the first vacuum processing unit 200.

With the gate valve 231a closed and the process chamber 231 kept airtight, a high frequency of 13.56 MHz at 2000 W is applied to the first high frequency source 153, and B ₂ H _{6 of} 20 sccm is supplied from the gas supply system 147. After supplying and stabilizing the plasma discharge, the second high-frequency source 155 outputs 2500M at 1500W under the control of the control unit 157.
A high frequency of Hz is applied to the susceptor 141. The B ₂ H ₆ gas is ionized or radicalized by the plasma, and the substrate 1
It is pulled into the substrate 10 side by a self-bias of about -200 V of 0, thereby achieving ion doping. In this embodiment, the time is controlled in the same manner as described above to reduce the dose of boron (B) ions to 1 × 10 ¹⁵ ions / cm ^2.
Was controlled. As a result, in the p-Si thin film 40, FIG.
As shown in (h), the source and drain regions 41, 4
3. A channel region 45 sandwiched between the source and drain regions 41 and 43 was formed.

Then, the residual gas in the process chamber 231 is exhausted, and is supplied to the first high-frequency source 153 at 2000 W and 13.56 MH.
z and a gas supply system 147
50 sccm of F ₄ and 950 sccm of O ₂ are supplied,
Stabilizes plasma discharge. At this time, the self-bias of the substrate 10 is substantially zero, and the resist 61 is removed by ashing in the CDE mode based on CF ₄ and O ₂ gas ionized or radicalized by plasma.

After that, the residual gas in the process chamber 231 is exhausted, the gate valve 231a is opened, and the substrate 10 is transferred by the transfer robot 202 to the process chamber 271 functioning as a film forming chamber through the common chamber 201. Then, in this process chamber 271, a silicon nitride (SiNx) film is deposited as an interlayer insulating film by a low pressure plasma CVD method. Specifically, the first high-frequency source 153 is supplied with 1
A high frequency of 3.56 MHz was applied, and 160 sccm of SiH ₄ and 3 N ₂ O gas were supplied from the gas supply system 147.
000 sccm, Ar gas is supplied at 5000 sccm,
Plasma discharge is stabilized at a substrate temperature of 350 ° C. Then, an interlayer insulating film 63 having a thickness of 500 nm was deposited by a so-called reduced pressure plasma CVD method.

After the residual gas in the process chamber 271 is exhausted, the substrate 10 is transported to the resist processing unit 400, and the resist processing unit 40
0, a resist pattern (not shown) is formed, and the resist pattern is formed in an etching chamber 531 of the wet processing apparatus 500.
FIG. 6 (i) by wet etching based on the pattern
A contact hole 64 is formed in the gate insulating film 50 and the interlayer insulating film 63 as shown in FIG.

Thereafter, in the process chamber 361 of the second vacuum processing unit 300, Al for source / drain electrode wiring is formed.
An Nd alloy film is deposited by a sputtering method. Then, in the same manner as described above, the resist processing unit 400
After forming a resist pattern (not shown) in the first vacuum source unit 153 in the process chamber 371 of the second vacuum processing unit 300 functioning as an etching chamber,
A high frequency of 13.56 MHz is applied with W, and 500 sccm of Cl ₂ and 500 sc are supplied from the gas supply system 147.
cm of BCl ₃ to stabilize the plasma discharge, and then control the second high-frequency source 155 under the control of the control unit 157.
And a 200 MHz high frequency of 6 MHz is applied to the susceptor 141. C ionized and radicalized by plasma
The l ₂ and BCl ₃ gases are rapidly drawn into the substrate side by a self-bias of about −10 V of the substrate 10, and the Al—Nd alloy film is patterned substantially vertically based on the RIE mode, as shown in FIG. So that the drain regions 31 and 4
Then, drain electrodes 81 and 83 electrically connected to 1 and source electrodes 85 and 87 electrically connected to the source region are formed to complete a thin film transistor.

As described above, in the present embodiment, the first vacuum processing unit 200 forms the a-Si / p-Si functional film.
An apparatus unit for processing, formation / processing of an insulating film, an ion doping step for forming a source / drain region, a second vacuum processing unit 300 is an apparatus unit for forming a gate electrode, a source / drain electrode wiring, and a resist processing unit 400 is The resist coating / exposure / development and wet processing units 500 are used for silane coupling processing and contact hole formation processing. The units are connected by a clean substrate transfer chamber 110 of class 100 or less, and the transfer robot 113 uses the two-dimensional barcode or the like to directly perform the transfer on the substrate 10 based on the specification product number or history provided on the substrate 10.
Is transported between the units 200, 300, 400, 500.

Therefore, according to this embodiment, the substrate is continuously processed in a vacuum environment or a clean environment of class 100, whereby a thin film transistor is completed on the substrate. And the productivity and the production yield were able to be improved.

Further, since the crystallization by ELA and the formation of the gate insulating film are performed continuously without being exposed to the atmosphere, a thin film transistor having a small variation in threshold value may be used, probably because a good interface is formed. I got it.

Further, according to the above-described embodiment, since each of the first and second vacuum processing units 200 and 300 includes the process chambers 261 and 351 functioning as an inspection room, the post-process of the defective product is performed. Inflow to the substrate can be effectively prevented, and the production yield can be greatly improved by continuously reprocessing possible substrates.

By the way, depending on the product to be manufactured,
The number of wet processing steps, the number of ion doping steps, and the number of other film forming steps increase. In this case, the manufacturing apparatus 100 shown in FIG. 1 is directly connected to another substrate transfer chamber 110. Or may be connected by AGV. Alternatively, the process flow or the processing capacity may be adjusted by increasing or decreasing the number of process chambers of each processing unit, and the present invention is not limited to the above embodiment.

According to this embodiment, even when maintenance of a process chamber is required, for example, the type of gas and the type of high frequency to another process chamber having substantially the same configuration can be adjusted, By controlling the temperature, it is easy to convert different types of films, ion doping, etching, etc., so that continuous production can be performed without significantly impairing the operation rate of the entire production line .
The above embodiments are merely examples of the present invention, and can be applied to semiconductor devices other than thin film transistors.

[0064]

According to the method and apparatus for manufacturing a semiconductor device of the present invention, a large clean room for transferring the apparatus and the substrate can be dispensed with, and the construction cost and the manufacturing cost can be greatly reduced. In addition, since the number of washing steps and cassette transport steps can be reduced, the total processing time required for manufacturing and the number of apparatuses can be significantly reduced.

Further, according to the present invention, undesired retention of semi-finished products during the production is reduced, thereby achieving a high production yield. Further, according to the present invention, by performing the inspection during the production, the flow of the defective product to the next process is suppressed, thereby improving the productivity and the production yield.

As described above, according to the present invention, it is possible to reduce the construction cost of a building or a clean room in the production of semiconductor devices, the running cost (power cost) of production, and to improve the production yield and performance of semiconductor devices. It is.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a manufacturing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of one process chamber in FIG. 1;

FIG. 3 is a schematic configuration diagram of one process chamber in FIG. 1;

FIG. 4 is a schematic configuration diagram of a modified example of the process chamber in FIG. 1;

FIG. 5 is a diagram for explaining a manufacturing process of the thin film transistor according to one embodiment of the present invention.

FIG. 6 is a view for explaining a manufacturing process of the thin film transistor performed subsequently to FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Glass substrate 20 ... a-Si: H thin film 30, 40 ... p-Si thin film 100 ... Manufacturing apparatus 110 ... Substrate transfer chamber 200, 300 ... Vacuum processing unit 400 ... Resist processing apparatus 500 ... Wet processing unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 29/78 627B 627G F term (Reference) 2H092 JA24 JA37 JA47 KA02 KA04 KA10 MA08 MA09 MA12 MA17 MA27 MA29 MA30 MA35 NA29 NA30 4M106 AA10 BA04 CB30 DH11 DH12 DJ38 5F045 AA06 AA09 AB03 AB04 AB32 AB33 AC01 AC09 AC12 AC16 AE01 AF07 CA15 CB01 DP03 DP04 DQ17 EH02 EH11 EN04 GB11 HA18 5F052 AA02 BA01 BA02 DD01 DD13 DD14 EE02 EE45 FF02 FF03 FF30 GG02 GG13 GG25 GG32 GG45 HJ01 HJ04 HJ13 HL23 NN02 NN24 NN35 PP03 PP06 QQ04

Claims (12)

[Claims] Forming a non-single-crystal silicon thin film on an insulating substrate in a first process chamber among first to third process chambers hermetically connected to each other through a common chamber; Moving the substrate to a non-single-crystal silicon thin film and irradiating the non-single-crystal silicon thin film with light energy to form a recrystallized silicon thin film; And a manufacturing method of the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said substrate is moved to said second process chamber and irradiated with light energy when said substrate is determined to be defective in said inspection step. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said inspecting step electrically and optically measures physical and optical characteristics of said crystalline silicon thin film. 4. The method according to claim 1, wherein the recrystallized silicon thin film is a polycrystalline silicon thin film. 5. A step of patterning a thin film formed on an insulating substrate into a desired shape in a first process chamber of a first process chamber and a second process chamber airtightly connected to each other via a common chamber, and Moving the semiconductor device to a second process chamber and inspecting a shape of the patterned thin film. 6. A first processing unit including first and second process chambers and a first substrate loading / unloading chamber airtightly connected to each other via a first common chamber, and airtightly connected to each other via a second common chamber. A second processing unit including the third and fourth process chambers and the second substrate loading / unloading chamber connected to each other, a third common chamber hermetically connected between the first and second substrate loading / unloading chambers, A third substrate loading / unloading chamber which takes in the supplied substrate to be processed into the third common chamber, and a transfer which is disposed in the third common chamber and transfers the substrate to be processed among the first to third loading / unloading chambers. A semiconductor device manufacturing apparatus, comprising: mounting means. 7. At least the first common chamber, the first process chamber, and the first substrate loading / unloading chamber of the first processing unit are configured to be capable of reducing pressure, and the first processing chamber holds the substrate to be processed. And a susceptor that can be set to a predetermined potential, gas supply means for supplying a reactive gas into the first processing chamber, and plasma generation means for generating plasma in the first processing chamber. An apparatus for manufacturing a semiconductor device according to claim 6. 8. The first common chamber deposits a thin film based on the reactive gas on the substrate to be processed, performs ion doping on the substrate to be processed based on the reactive gas, or the substrate to be processed. 8. The apparatus for manufacturing a semiconductor device according to claim 7, wherein said etching is performed based on said reactive gas. 9. The apparatus for manufacturing a semiconductor device according to claim 6, wherein at least the first process chamber of the first processing unit includes irradiation means for irradiating the processing target substrate with light energy. 10. The third and fourth process chambers of the second processing unit may be a coating chamber for applying a resist on the substrate to be processed, an exposure chamber for exposing the resist, or a developing chamber for developing the resist. 7. The apparatus for manufacturing a semiconductor device according to claim 6, wherein the apparatus is any one. 11. The semiconductor device manufacturing apparatus according to claim 6, wherein the third and fourth process chambers of the second processing unit are etching chambers for etching the substrate to be processed with a chemical. 12. An apparatus for manufacturing a semiconductor device, wherein the third common chamber is at atmospheric pressure and is set to at least class 1000 or less.