JPH0239523A - Method of forming film on semiconductor substrate - Google Patents
Method of forming film on semiconductor substrateInfo
- Publication number
- JPH0239523A JPH0239523A JP19039088A JP19039088A JPH0239523A JP H0239523 A JPH0239523 A JP H0239523A JP 19039088 A JP19039088 A JP 19039088A JP 19039088 A JP19039088 A JP 19039088A JP H0239523 A JPH0239523 A JP H0239523A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- high frequency
- processed
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims description 36
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004140 cleaning Methods 0.000 claims abstract description 28
- 238000000992 sputter etching Methods 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims description 46
- 239000010409 thin film Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 13
- 239000012535 impurity Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002052 molecular layer Substances 0.000 description 2
- 229910021642 ultra pure water Inorganic materials 0.000 description 2
- 239000012498 ultrapure water Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002362 mulch Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) 本発明は、半導体への成膜方法に関する。[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention relates to a method for forming a film on a semiconductor.
(従来の技術)
従来より、半導体製造プロセスにおけるS1エピタキシ
ヤル成膜や窒化膜等の成膜処理では、成膜処理の前処理
として、半導体ウエノ1等の被処理基板表面に形成され
た有機物等の吸着不純物層や自然酸化膜層を除去するた
めのクリーニング処理が行われている。(Prior art) Conventionally, in film forming processes such as S1 epitaxial film formation and nitride film in semiconductor manufacturing processes, organic substances, etc. formed on the surface of the substrate to be processed, such as semiconductor wafer 1, are used as a pretreatment for the film forming process. A cleaning process is performed to remove the adsorbed impurity layer and natural oxide film layer.
従来行われているクリーニング処理方法としては、ウェ
ットエツチング方法があり、このウェットエツチング方
法としては、以下のような方法かある。A conventional cleaning treatment method is a wet etching method, and the wet etching method includes the following methods.
■H2so、:H202−4: 1の液に5分間浸ンj
二;
■超純水で10分間洗浄
■HF : H2O−1+100の液に 1分間浸漬■
超純水で10分間洗浄
■乾燥工程
こうして処理した被処理基板を成膜装置まで搬送して成
膜処理を行っていた。■H2so, :H202-4: Soak in solution 1 for 5 minutes.
2; ■Cleanse with ultrapure water for 10 minutes■Immerse in HF: H2O-1+100 solution for 1 minute■
Washing with ultrapure water for 10 minutes - Drying process The substrate to be processed thus treated was transported to a film forming apparatus and subjected to film forming processing.
ところが、上述したようなりリーニング処理では、クリ
ーニング処理を施した被処理基板が成膜装置まで搬送さ
れる際に大気中にさらされるため、空気中の02による
自然酸化膜や、N、aや(CH2)n等の不純物の吸着
分子層が再び形成されてしまうという聞届があり、この
ような薄膜が形成された状態で成膜処理を行うと、形成
された薄膜と被処理基板との密着性が悪く、LSIデバ
イス作成の場合には界面として使用できないという問題
があった。また、成膜装置までの搬送作業をクリーンル
ーム内で行っても、被処理基板への塵埃の付着を完全に
防止することができず、歩留りの低下を招く原因となっ
ていた。However, in the above-mentioned cleaning process, the cleaned substrate is exposed to the atmosphere when it is transported to the film forming apparatus. It has been reported that an adsorbed molecular layer of impurities such as CH2)n is formed again, and if a film formation process is performed with such a thin film formed, the formed thin film and the substrate to be processed may come into close contact with each other. There was a problem in that it had poor properties and could not be used as an interface in the production of LSI devices. Further, even if the transportation work to the film forming apparatus is performed in a clean room, it is not possible to completely prevent dust from adhering to the substrate to be processed, which causes a decrease in yield.
そこで、これら問題を解決するために、成膜装置内にク
リーニング処理を行うための処理室を設けて、クリーニ
ング処理した被処理基板を同一装置筐体内で大気に接触
させることなくクリーニング処理−成膜処理を行うよう
にした処理装置が開発されている。Therefore, in order to solve these problems, a processing chamber for performing cleaning processing is provided in the film forming apparatus, and the cleaning processing and film forming process are performed without exposing the cleaned processed substrate to the atmosphere within the same apparatus housing. Processing devices have been developed to perform the processing.
このような成膜装置として、同−雰囲気例えば真空容器
内に複数の処理室(チャンバ)を備えた枚葉式のいわゆ
るマルチチャンバ方式のCVD処理装置が開発されてお
り、このCVD装置は、クリーニング処理用チャンバに
て被処理基板をクリニングした後、この被処理基板を成
膜用チャンバに搬送して処理を行うように構成されてい
る。As such a film forming apparatus, a single-wafer type so-called multi-chamber type CVD processing apparatus has been developed, which is equipped with a plurality of processing chambers (chambers) in the same atmosphere, for example, a vacuum container. After the substrate to be processed is cleaned in the processing chamber, the substrate to be processed is transported to the film-forming chamber for processing.
(発明が解決しようとする課題)
しかしながら、上述した従来のマルチチャンバ方式の成
膜処理装置における被処理基板のクリニング処理は、高
エネルギーのプラズマエツチング処理や、チャンバ内を
酸素雰囲気にして被処理基板を高温例えば800℃まで
昇温し紫外線を照射しながら処理を行う等の処理が行わ
れており、いずれの場合も熱や飛翔イオンによる被処理
基板ダメージが発生し、歩留りを低下させるという問題
があった。(Problem to be Solved by the Invention) However, in the conventional multi-chamber type film forming processing apparatus described above, cleaning processing of the processing target substrate is performed using high-energy plasma etching processing or an oxygen atmosphere inside the chamber to clean the processing target substrate. Processing is carried out by raising the temperature to a high temperature, for example 800°C, and irradiating it with ultraviolet rays.In both cases, the problem is that the substrate to be processed is damaged by heat and flying ions, and the yield is reduced. there were.
本発明は、上述した問題点を解決するためになされたも
ので、同−雰囲気内で、クリーニング処理と成膜処理を
行うとともに、クリーニング処理を低エネルギースパッ
タエツチングにより行うことで、被処理基板へのダメー
ジを防止しつつ良質の成膜が行える半導体基板への成膜
方法を提供することを目的とするものである。The present invention was made in order to solve the above-mentioned problems, and in addition to performing a cleaning process and a film forming process in the same atmosphere, the cleaning process is performed by low-energy sputter etching, so that the substrate to be processed can be etched. It is an object of the present invention to provide a method for forming a film on a semiconductor substrate, which can form a high-quality film while preventing damage to the semiconductor substrate.
[発明の構成]
(課題を解決するための手段)
本発明の半導体基板への成膜方法は、被処理基板表面の
不要な薄膜をクリーニング処理する工程と、このクリー
ニング処理された被処理基板上に所定の薄膜を形成する
成膜工程とからなる半導体基板への成膜方法において、
前記クリーニング工程と前記成膜工程とを同−雰囲気内
で行うとともに、前記クリーニング工程を前記不要な薄
膜と前記被処理基板との結合エネルギーと略等しいエネ
ルギーのイオンによるスパッタエツチング処理により行
うことを特徴とするものである。[Structure of the Invention] (Means for Solving the Problems) The method of forming a film on a semiconductor substrate of the present invention includes a step of cleaning an unnecessary thin film on the surface of the substrate to be processed, and a step of cleaning the unnecessary thin film on the surface of the substrate to be processed after the cleaning process. In a method for forming a film on a semiconductor substrate, the method includes a film forming step of forming a predetermined thin film on a semiconductor substrate.
The cleaning step and the film forming step are performed in the same atmosphere, and the cleaning step is performed by sputter etching using ions having approximately the same energy as the bonding energy between the unnecessary thin film and the substrate to be processed. That is.
(作 用)
本発明は、同一装置筐体内で、クリ−エン6グ処理と成
膜処理を行うとともに、クリーニング処理を低エネルギ
ースパッタエツチングにより行うことで、被処理基板へ
のダメージを防止しつつ良質の成膜を行うことが可能と
なる。(Function) The present invention performs a cleaning process and a film forming process in the same device housing, and also performs a cleaning process by low energy sputter etching, thereby preventing damage to the substrate to be processed. It becomes possible to form a film of high quality.
(実施例)
以下、本発明をStエピタキシャル成長用のマルチチャ
ンバ型CVD装置に適用した一実施例について図を参照
して説明する。(Example) Hereinafter, an example in which the present invention is applied to a multi-chamber type CVD apparatus for St epitaxial growth will be described with reference to the drawings.
真空ロードロック室1を中心としてほぼ90度の角度間
隔をおいて複数例えば3つのチャンバ2.3.4が、夫
々ゲートバルブ5を介して同円周状に配設されている。A plurality of chambers 2.3.4, for example, three chambers, are arranged around the vacuum load-lock chamber 1 at angular intervals of about 90 degrees, each via a gate valve 5, in the same circumferential shape.
これらチャンバ2.3.4の構成は、被処理基板上に形
成された自然酸化膜等の不要な薄膜を低エネルギーのス
パッタエツチングにより除去するクリーニング処理チャ
ンバ2と、このクリーニング処理された被処理基板に成
膜処理例えばSiエピタキシャル成膜を行う成膜処理チ
ャンバ3と、この薄膜が形成された被処理基板を必要に
応じてさらに処理、例えばN2ガス等の雰囲気で熱処理
する熱処理チャンバ4等から構成されている。These chambers 2.3.4 are composed of a cleaning processing chamber 2 that removes unnecessary thin films such as natural oxide films formed on the substrate to be processed by low energy sputter etching, and a cleaning processing chamber 2 for removing unnecessary thin films such as natural oxide films formed on the substrate to be processed, and the substrate to be processed that has been cleaned. It is composed of a film formation processing chamber 3 for performing film formation processing, for example, Si epitaxial film formation, and a heat treatment chamber 4 for further processing the substrate to be processed on which the thin film is formed, for example, heat treatment in an atmosphere of N2 gas, etc. ing.
半導体基板等の被処理基板6は、図示を省略した搬送機
構により、真空ロードロック室1内に搬送され、ここで
処理内容に応じた手順例えばチャンバ1→チヤンバ2→
チヤンバ3→チヤンバ4の手順で搬送されて所定の処理
を施される。The substrate 6 to be processed, such as a semiconductor substrate, is transported into the vacuum load lock chamber 1 by a transport mechanism (not shown), where it is transferred through a procedure according to the processing content, for example, from chamber 1 → chamber 2 →
It is transported in the order of chamber 3 → chamber 4 and subjected to predetermined processing.
ところで、上記クリーニング処理チャンバ2は・被処理
基板6を低エネルギースパッタエツチングするためのチ
ャンバで、その構成は第2図に示すように、チャンバ2
内に収容された高周波電極7と、この高周波電極7に対
向して配置され被処理基板6の載置台となる下部電極8
と、高周波電極7に所定の高周波を印加する高周波電源
つと、下部電極8に直流の基板電圧を印加するための直
流電源10とから構成されている。By the way, the cleaning processing chamber 2 is a chamber for performing low energy sputter etching on the substrate 6 to be processed, and its configuration is as shown in FIG.
a high-frequency electrode 7 housed therein, and a lower electrode 8 disposed opposite to the high-frequency electrode 7 and serving as a mounting table for the substrate 6 to be processed.
, a high frequency power supply for applying a predetermined high frequency to the high frequency electrode 7 , and a DC power supply 10 for applying a DC substrate voltage to the lower electrode 8 .
エツチング制御は、高周波電力により処理ガスイオンの
密度を制御し、また基板電圧により被処理基板6に入射
するイオンエネルギーを制御することにより行われる。Etching control is performed by controlling the density of processing gas ions using high frequency power and controlling the ion energy incident on the substrate 6 to be processed using the substrate voltage.
また、高周波電極7近傍のチャンバ壁にはエツチング処
理ガス例えばArガス導入用のガス導入口11が設けら
れており、一方下部電極8近傍のチャンバ壁にはガス排
気口12が設けられており、ガス導入口11からチャン
バ2内に導入されたArガスは、ガス排気口12から図
示を省略した真空機構へと排気される。Further, a gas inlet 11 for introducing an etching gas such as Ar gas is provided in the chamber wall near the high-frequency electrode 7, and a gas exhaust port 12 is provided in the chamber wall near the lower electrode 8. Ar gas introduced into the chamber 2 from the gas inlet 11 is exhausted from the gas exhaust port 12 to a vacuum mechanism (not shown).
このチャンバ2による低エネルギースパッタエツチング
方法について以下に説明する。A low energy sputter etching method using this chamber 2 will be explained below.
まず、所定の真空度例えば10”Torrを保持しなが
らガス導入口11から処理ガス例えばArガスを導入す
る。このとき、高周波電極7には所定の筒周波例えばL
OOMHzの高周波電力を印加し、一方下部電極10に
は所定の基板電圧例えば−15〜+15Vの範囲内で電
圧を印加する。First, a processing gas such as Ar gas is introduced from the gas inlet 11 while maintaining a predetermined degree of vacuum, e.g. 10" Torr. At this time, a predetermined cylindrical frequency e.g.
A high frequency power of OOMHz is applied, while a predetermined substrate voltage, for example, a voltage within the range of -15 to +15V is applied to the lower electrode 10.
こうして、導入されたArガスは、高周波によりプラズ
マ化され、このプラズマ領域m中のA「イオンを被処理
基板表面に照射することにより、エツチングが行われる
。In this way, the introduced Ar gas is turned into plasma by high frequency waves, and etching is performed by irradiating the surface of the substrate to be processed with A' ions in this plasma region m.
また、本実施例方法では、基板電圧を一15〜+15V
の低電圧としたため、被処理基板6に入射するA「イオ
ンのエネルギーは低エネルギー例えば数10eVとなる
。In addition, in the method of this embodiment, the substrate voltage is -15 to +15V.
Since the voltage is set to be low, the energy of the A' ions incident on the substrate 6 to be processed is low, for example, several tens of eV.
一般に、半導体基板と5102膜や吸着不純物分子層と
の原子間結合エネルギーは、約数10eVであるため、
この結合エネルギーに近いエネルギーを有する低エネル
ギーイオンによりスパッタエツチングすることで、被処
理基板に損傷を与えることなく5i02膜等の不要な薄
膜の除去が行える。Generally, the interatomic bonding energy between the semiconductor substrate and the 5102 film or adsorbed impurity molecular layer is about several tens of eV, so
By performing sputter etching with low energy ions having energy close to this bond energy, unnecessary thin films such as the 5i02 film can be removed without damaging the substrate to be processed.
こうして、チャンバ2でクリーニング処理を行った後、
被処理基板6を真空ロードロック室1内に搬出し、この
後チャンバ3へ搬入して成膜処理例えばStエピタキシ
ャル成膜を行う。そして、再びロードロック室へと被処
理基板6を搬出した後、必要とあればチャンバ4内へ被
処理基板6を搬入しここで所定の処理を行う。After performing the cleaning process in chamber 2 in this way,
The substrate 6 to be processed is carried out into the vacuum load-lock chamber 1, and then carried into the chamber 3, where a film formation process, for example, St epitaxial film formation is performed. Then, after carrying out the substrate 6 to be processed into the load lock chamber again, if necessary, the substrate 6 to be processed is carried into the chamber 4 and predetermined processing is performed there.
このように、被処理基板6を低エネルギーのスパッタエ
ツチングによりクリーニング処理した後、この被処理基
板6を大気に接触させることなく成膜処理することで、
被処理基板6上に形成された自然酸化膜や吸着不純物層
を完全に除去して成膜が行え、良質な成膜処理か可能と
なる。さらに、低エネルギースパッタエツチングにより
クリーニング処理を行うので、クリーニング処理時の被
処理基板6へのダメージを防止でき、歩留りの向上が図
れる。In this way, after the substrate 6 to be processed is cleaned by low-energy sputter etching, the substrate 6 to be processed is subjected to a film forming process without being exposed to the atmosphere.
Film formation can be performed by completely removing the natural oxide film and adsorbed impurity layer formed on the substrate 6 to be processed, and high-quality film formation processing is possible. Furthermore, since the cleaning process is performed by low-energy sputter etching, damage to the substrate 6 to be processed during the cleaning process can be prevented, and the yield can be improved.
[発明の効果]
以上説明したように、本発明の半導体基板への成膜処理
方法によれば、被処理基板上に形成された自然酸化膜や
吸着不純物層を半導体基板に損傷を与えることなく完全
に除去して成膜処理が行えるので、良質な成膜が処理が
でき、歩留りの向上が図れる。[Effects of the Invention] As explained above, according to the method for forming a film on a semiconductor substrate of the present invention, the natural oxide film and adsorbed impurity layer formed on the substrate to be processed can be removed without damaging the semiconductor substrate. Since the film formation process can be performed with complete removal, a high quality film can be formed and the yield can be improved.
第1図は本発明方法の一実施例を適用するモルチチャン
バ型CVD装置の構成を示す図、第2図は第1図の実施
例のクリーニング処理チャンバの構成を示す図である。
l・・・・・・真空ロードロック室、2・・・・・・低
エネルギースパッタエツチング用処理チャンバ、3.4
・・・・・成膜用チャンバ 6・・・・・・被処理基板
、7・・・・・・高周波電極、8・・・・・・下部電極
。FIG. 1 is a diagram showing the configuration of a mulch chamber type CVD apparatus to which an embodiment of the method of the present invention is applied, and FIG. 2 is a diagram showing the configuration of the cleaning processing chamber of the embodiment of FIG. 1. 1...Vacuum load lock chamber, 2...Processing chamber for low energy sputter etching, 3.4
. . . Chamber for film formation 6 . . . Substrate to be processed, 7 . . . High frequency electrode, 8 . . . Lower electrode.
Claims (1)
程と、このクリーニング処理された被処理基板上に所定
の薄膜を形成する成膜工程とからなる半導体基板への成
膜方法において、 前記クリーニング工程と前記成膜工程とを同一雰囲気内
で行うとともに、前記クリーニング工程を前記不要な薄
膜と前記被処理基板との結合エネルギーと略等しいエネ
ルギーのイオンによるスパッタエッチング処理により行
うことを特徴とする半導体基板への成膜方法。[Claims] A method for forming a film on a semiconductor substrate, which comprises a step of cleaning an unnecessary thin film on the surface of a substrate to be processed, and a film forming step of forming a predetermined thin film on the cleaned substrate. The cleaning step and the film forming step are performed in the same atmosphere, and the cleaning step is performed by sputter etching using ions having an energy substantially equal to the bonding energy between the unnecessary thin film and the substrate to be processed. Characteristic method for forming films on semiconductor substrates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19039088A JPH0239523A (en) | 1988-07-29 | 1988-07-29 | Method of forming film on semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19039088A JPH0239523A (en) | 1988-07-29 | 1988-07-29 | Method of forming film on semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0239523A true JPH0239523A (en) | 1990-02-08 |
Family
ID=16257365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19039088A Pending JPH0239523A (en) | 1988-07-29 | 1988-07-29 | Method of forming film on semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0239523A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03236255A (en) * | 1990-02-14 | 1991-10-22 | Hitachi Ltd | Method for removing charge from electrostatic chuck |
JPH05259146A (en) * | 1992-03-09 | 1993-10-08 | Hitachi Ltd | Semiconductor manufacturing apparatus |
US5478195A (en) * | 1991-12-20 | 1995-12-26 | Hitachi, Ltd. | Process and apparatus for transferring an object and for processing semiconductor wafers |
US5795399A (en) * | 1994-06-30 | 1998-08-18 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing apparatus, method for removing reaction product, and method of suppressing deposition of reaction product |
US6650409B1 (en) * | 1991-04-02 | 2003-11-18 | Hitachi, Ltd. | Semiconductor device producing method, system for carrying out the same and semiconductor work processing apparatus included in the same system |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58194342A (en) * | 1982-05-10 | 1983-11-12 | Toshiba Corp | Preparation of plasma cvd semiconductor device |
JPS61270817A (en) * | 1985-05-24 | 1986-12-01 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor element |
JPS63458A (en) * | 1986-06-19 | 1988-01-05 | Nissin Electric Co Ltd | Vacuum arc vapor deposition device |
JPS63138722A (en) * | 1986-12-01 | 1988-06-10 | Seiko Epson Corp | Vapor growth apparatus |
-
1988
- 1988-07-29 JP JP19039088A patent/JPH0239523A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58194342A (en) * | 1982-05-10 | 1983-11-12 | Toshiba Corp | Preparation of plasma cvd semiconductor device |
JPS61270817A (en) * | 1985-05-24 | 1986-12-01 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor element |
JPS63458A (en) * | 1986-06-19 | 1988-01-05 | Nissin Electric Co Ltd | Vacuum arc vapor deposition device |
JPS63138722A (en) * | 1986-12-01 | 1988-06-10 | Seiko Epson Corp | Vapor growth apparatus |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03236255A (en) * | 1990-02-14 | 1991-10-22 | Hitachi Ltd | Method for removing charge from electrostatic chuck |
JPH07109855B2 (en) * | 1990-02-14 | 1995-11-22 | 株式会社日立製作所 | Electrostatic chuck electrostatic charge removal method |
US6650409B1 (en) * | 1991-04-02 | 2003-11-18 | Hitachi, Ltd. | Semiconductor device producing method, system for carrying out the same and semiconductor work processing apparatus included in the same system |
US5478195A (en) * | 1991-12-20 | 1995-12-26 | Hitachi, Ltd. | Process and apparatus for transferring an object and for processing semiconductor wafers |
JPH05259146A (en) * | 1992-03-09 | 1993-10-08 | Hitachi Ltd | Semiconductor manufacturing apparatus |
US5795399A (en) * | 1994-06-30 | 1998-08-18 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing apparatus, method for removing reaction product, and method of suppressing deposition of reaction product |
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