JP2000235791A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2000235791A5 JP2000235791A5 JP1999035946A JP3594699A JP2000235791A5 JP 2000235791 A5 JP2000235791 A5 JP 2000235791A5 JP 1999035946 A JP1999035946 A JP 1999035946A JP 3594699 A JP3594699 A JP 3594699A JP 2000235791 A5 JP2000235791 A5 JP 2000235791A5
- Authority
- JP
- Japan
- Prior art keywords
- delay
- unit
- output
- clock
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000644 propagated effect Effects 0.000 claims description 13
- 230000001360 synchronised effect Effects 0.000 claims description 10
- 230000001934 delay Effects 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 4
- 230000001902 propagating effect Effects 0.000 claims 2
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11035946A JP2000235791A (ja) | 1999-02-15 | 1999-02-15 | クロック同期遅延制御回路 |
| TW089102417A TW459245B (en) | 1999-02-15 | 2000-02-14 | Clock synchronous delay control circuit |
| US09/503,000 US6198690B1 (en) | 1999-02-15 | 2000-02-14 | Clock control circuit with an input stop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11035946A JP2000235791A (ja) | 1999-02-15 | 1999-02-15 | クロック同期遅延制御回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000235791A JP2000235791A (ja) | 2000-08-29 |
| JP2000235791A5 true JP2000235791A5 (OSRAM) | 2005-06-30 |
Family
ID=12456167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11035946A Pending JP2000235791A (ja) | 1999-02-15 | 1999-02-15 | クロック同期遅延制御回路 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6198690B1 (OSRAM) |
| JP (1) | JP2000235791A (OSRAM) |
| TW (1) | TW459245B (OSRAM) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000286386A (ja) * | 1999-03-30 | 2000-10-13 | Toshiba Corp | クロック同期遅延制御回路 |
| KR100326809B1 (ko) * | 1999-04-09 | 2002-03-04 | 박종섭 | 딜레이 동기회로 |
| US6323705B1 (en) * | 2000-04-25 | 2001-11-27 | Winbond Electronics Corporation | Double cycle lock approach in delay lock loop circuit |
| KR100527402B1 (ko) * | 2000-05-31 | 2005-11-15 | 주식회사 하이닉스반도체 | 디디알 동기식메모리의 지연고정루프 장치 |
| JP4005779B2 (ja) * | 2001-07-03 | 2007-11-14 | 株式会社東芝 | クロック同期回路 |
| JP3699920B2 (ja) * | 2001-10-25 | 2005-09-28 | 株式会社東芝 | 遅延回路および同期型遅延装置 |
| US6711092B1 (en) * | 2002-04-30 | 2004-03-23 | Virage Logic Corp. | Semiconductor memory with multiple timing loops |
| US7095261B2 (en) | 2004-05-05 | 2006-08-22 | Micron Technology, Inc. | Clock capture in clock synchronization circuitry |
| US7276946B2 (en) * | 2004-07-16 | 2007-10-02 | Micron Technology, Inc. | Measure-controlled delay circuits with reduced phase error |
| JP2019053444A (ja) * | 2017-09-13 | 2019-04-04 | 東芝メモリ株式会社 | 半導体集積回路及び半導体装置 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0558079B1 (en) * | 1992-02-28 | 1998-04-15 | Sony Corporation | Semiconductor memory device with address transition detector |
| JP2771464B2 (ja) * | 1994-09-29 | 1998-07-02 | 日本電気アイシーマイコンシステム株式会社 | ディジタルpll回路 |
| US5870445A (en) | 1995-12-27 | 1999-02-09 | Raytheon Company | Frequency independent clock synchronizer |
| JP3410922B2 (ja) * | 1996-04-23 | 2003-05-26 | 株式会社東芝 | クロック制御回路 |
| US5923613A (en) | 1998-03-18 | 1999-07-13 | Etron Technology, Inc. | Latched type clock synchronizer with additional 180°-phase shift clock |
-
1999
- 1999-02-15 JP JP11035946A patent/JP2000235791A/ja active Pending
-
2000
- 2000-02-14 TW TW089102417A patent/TW459245B/zh not_active IP Right Cessation
- 2000-02-14 US US09/503,000 patent/US6198690B1/en not_active Expired - Lifetime
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001014847A5 (OSRAM) | ||
| JP2000235791A5 (OSRAM) | ||
| US6292412B1 (en) | Clock control circuit | |
| WO2005011118A3 (en) | A digital pulse width modulator | |
| JP2003283332A5 (OSRAM) | ||
| JPH0433056B2 (OSRAM) | ||
| TW201001435A (en) | Semiconductor memory device and reset control circuit of the same | |
| TW328133B (en) | Column select line enable circuit of semiconductor memory device | |
| CN109478760B (zh) | 激光脉冲发生器和用于产生激光脉冲的方法 | |
| KR101128961B1 (ko) | 반도체 장치 | |
| JP2001514452A (ja) | プログラム可能な遅延ラインのためのパルススタフィング回路 | |
| US20250038742A1 (en) | Pwm circuit, apparatus including the same | |
| JP2000235791A (ja) | クロック同期遅延制御回路 | |
| US7253667B2 (en) | Clock adjusting method and electronic device with clock adjusting function | |
| JP2003015764A5 (OSRAM) | ||
| US5512851A (en) | Circuit synchronization when switching between multiple clock signals using a variable advance controller | |
| JP5660922B2 (ja) | シリアル通信装置 | |
| JP4190217B2 (ja) | クロック生成装置及びオーディオデータ処理装置 | |
| RU2042264C1 (ru) | Управляемый генератор импульсной последовательности | |
| WO2006100626A3 (en) | Electronic circuit wherein an asynchronous delay is realized | |
| WO2006067393A3 (en) | Programmable digital delay | |
| JPS6131438Y2 (OSRAM) | ||
| TWI226753B (en) | Multi-channel minimum time lag PWM generator and its generation and synchronization method | |
| CN120188356A (zh) | 激光脉冲发生器及产生激光脉冲的方法 | |
| SU438057A1 (ru) | Многоканальное программное реле времени |