JP2000223714A5 - - Google Patents

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Publication number
JP2000223714A5
JP2000223714A5 JP1999331794A JP33179499A JP2000223714A5 JP 2000223714 A5 JP2000223714 A5 JP 2000223714A5 JP 1999331794 A JP1999331794 A JP 1999331794A JP 33179499 A JP33179499 A JP 33179499A JP 2000223714 A5 JP2000223714 A5 JP 2000223714A5
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JP
Japan
Prior art keywords
impurity region
thin film
film transistor
conductive layer
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1999331794A
Other languages
English (en)
Japanese (ja)
Other versions
JP4159713B2 (ja
JP2000223714A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP33179499A priority Critical patent/JP4159713B2/ja
Priority claimed from JP33179499A external-priority patent/JP4159713B2/ja
Publication of JP2000223714A publication Critical patent/JP2000223714A/ja
Publication of JP2000223714A5 publication Critical patent/JP2000223714A5/ja
Application granted granted Critical
Publication of JP4159713B2 publication Critical patent/JP4159713B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP33179499A 1998-11-25 1999-11-22 半導体装置 Expired - Fee Related JP4159713B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33179499A JP4159713B2 (ja) 1998-11-25 1999-11-22 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP33366598 1998-11-25
JP10-333665 1998-11-25
JP33179499A JP4159713B2 (ja) 1998-11-25 1999-11-22 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005301223A Division JP4160072B2 (ja) 1998-11-25 2005-10-17 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2000223714A JP2000223714A (ja) 2000-08-11
JP2000223714A5 true JP2000223714A5 (enrdf_load_stackoverflow) 2005-12-02
JP4159713B2 JP4159713B2 (ja) 2008-10-01

Family

ID=26573968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33179499A Expired - Fee Related JP4159713B2 (ja) 1998-11-25 1999-11-22 半導体装置

Country Status (1)

Country Link
JP (1) JP4159713B2 (enrdf_load_stackoverflow)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2256808A2 (en) 1999-04-30 2010-12-01 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device and manufacturing method therof
JP4850328B2 (ja) * 2000-08-29 2012-01-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5046452B2 (ja) * 2000-10-26 2012-10-10 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2002151698A (ja) * 2000-11-14 2002-05-24 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
TW525216B (en) 2000-12-11 2003-03-21 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
JP4737828B2 (ja) * 2000-12-21 2011-08-03 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4926321B2 (ja) * 2001-01-24 2012-05-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4939690B2 (ja) * 2001-01-30 2012-05-30 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4801262B2 (ja) * 2001-01-30 2011-10-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4693257B2 (ja) * 2001-02-21 2011-06-01 株式会社半導体エネルギー研究所 半導体装置の作製方法
SG142160A1 (en) 2001-03-19 2008-05-28 Semiconductor Energy Lab Method of manufacturing a semiconductor device
JP4926329B2 (ja) 2001-03-27 2012-05-09 株式会社半導体エネルギー研究所 半導体装置およびその作製方法、電気器具
JP4338934B2 (ja) * 2001-03-27 2009-10-07 株式会社半導体エネルギー研究所 配線の作製方法
SG116443A1 (en) 2001-03-27 2005-11-28 Semiconductor Energy Lab Wiring and method of manufacturing the same, and wiring board and method of manufacturing the same.
KR100983525B1 (ko) 2003-12-26 2010-09-24 삼성전자주식회사 상보형 박막트랜지스터 형성방법과 이에 의한 상보형박막트랜지스터
JP2006003493A (ja) * 2004-06-16 2006-01-05 Nikon Corp 形状転写方法
WO2009123127A1 (ja) 2008-04-02 2009-10-08 Ｎｅｃ液晶テクノロジー株式会社 半導体装置及びその製造方法、並びに液晶表示装置及び電子機器
JP5520911B2 (ja) * 2011-10-12 2014-06-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
US9786793B2 (en) 2012-03-29 2017-10-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising oxide semiconductor layer including regions with different concentrations of resistance-reducing elements

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