JP2000201300A - Solid-state image pickup device, image input device and reset method for solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a device that excellently performs photoelectric conversion by inputting a pulse signal, which turns on a reset switch which applies a reset voltage to an input terminal and turns on a transferring switch transferring electric charges to the input terminal, to the reset switch and the transferring switch. SOLUTION: A high level signal is applied to the gate of a transfer switch Q1, which is turned on. Light signal electric charges which is accumulated at a photoelectric conversion part PD are read out to a diffusion area FD through the transfer switch Q1. Then, a low level signal is applied to the gate of the transferring switch Q1 is turned off. Here, a high level signal is applied to a reset switch Q2, which is turned on to reset the diffusion area FD. Moreover, the transferring switch Q1 is turned on and the photoelectric conversion PD is reset. The potential energy of the diffusion area FD is lower than that of the photoelectric conversion part PD so that all the remaining electric charges are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital camera,
The present invention relates to a solid-state imaging device used for an image input device such as a video camera, an image scanner, or an AF sensor, and a reset method thereof.

[0002]

2. Description of the Related Art A typical example of a solid-state image pickup device is a CCD image sensor and a non-CCD image sensor. The former has a photoelectric conversion unit including a photodiode and a CCD shift register, and the latter includes a photodiode or a phototransistor. And a scanning circuit including a MOS transistor.

[0003] Among the non-CCD image sensors, an APS comprising a photodiode and a MOS transistor is used.
(Active Pixel Sensor).

APS is a photodiode, M for each pixel.
Includes an OS switch, an amplifier circuit for amplifying the signal from the photodiode, etc., such as "XY addressing"
There are many merits such as "integration of sensor and signal processing circuit into one chip". On the other hand, since the number of elements in one pixel is large, it is relatively difficult to reduce the chip size for determining the size of the optical system. Therefore, the CCD image sensor still occupies most of the solid-state imaging device market. ing.

[0005] However, in recent years, the technology for miniaturization of MOS transistors has been improved and "sensors and signal processing circuits have been integrated into one chip".
APS is also called a CMOS sensor or the like, and is attracting attention because of increasing demands such as a low power consumption.

FIG. 23 is a schematic diagram for explaining the structure and operation of a pixel portion of a conventional APS.

In FIG. 23, the photoelectric conversion unit PD is
This is the same buried photodiode as that used for D and the like. The buried photodiode suppresses dark current generated on the SiO ₂ surface by providing a p ⁺ layer having a high impurity concentration on the surface, and is generated between the n layer of the accumulation portion and the p ⁺ layer on the surface. The amount of saturation charge of the photodiode can be increased by the junction capacitance.

The operation is as follows. Gate RST
To reset the diffusion region FD to the reference voltage. After that, an off pulse is input to the gate RST,
The accumulation is started with the diffusion region in a floating state. After a lapse of a predetermined time, an ON pulse is input to the gate TX, and the photoelectric conversion unit P
The optical signal charges accumulated in D are read out to the floating diffusion region FD, which is the input terminal of the amplification unit, via the transfer unit TX composed of a MOS transistor. The signal charge Q _sig by capacitance C _FD of the floating diffusion region FD and a voltage converted to Q _sig / C _FD, reads the signal through the source follower circuit to the input terminal of the floating diffusion region FD.

When a reverse bias voltage is applied to the buried photodiode, the p-type voltage on the surface depends on the bias voltage.
^From the PN junction with the ⁺ layer and the PN junction with the P-type well PWL of the substrate, a depletion layer extends vertically in the n-layer. At this time, the number of electrons in the n-layer of the photodiode is substantially equal to the number of electrons in the neutral region sandwiched between both depletion layers, and decreases in proportion to the width of the depletion layer. The number of electrons in the neutral region when the reverse bias voltage is 0 Volt corresponds to the saturation charge Qsat. When both depletion layers extend due to the reverse bias and the two depletion layers come into contact with each other, the inside of the photodiode is completely depleted, and the neutral region disappears.

The reverse bias voltage at this time is hereinafter referred to as a depletion voltage Vdp.

When a larger reverse bias voltage is applied, the electron concentration in the n-layer of the photodiode decreases exponentially with respect to the reverse bias.

In the APS described above, if the inside of the n-layer of the photodiode is depleted at the time of reading, the charge generated by the light is almost completely transferred to the floating diffusion region FD, and the electrons in the photodiode are reset. Achieved.
Hereinafter, such a transfer method in which the charges of the photodiode are completely transferred is referred to as depletion transfer.

In FIG. 24, the floating diffusion region FD when the saturated charge is read out with respect to the saturated charge amount of the photodiode is shown.
Are shown as X and Y, and the depletion voltage with respect to the saturation charge amount is shown as Z.

The voltage value V _FDsat of the floating diffusion region FD is given by the following equation.

[0015] _{V FDsat = Vres-Qsat / C} FD Vres reset voltage of the floating diffusion region, QSAT the saturation charge amount of the photodiode, is C _FD is the capacitance of the floating diffusion region.

Generally, the saturation charge of a photodiode must be above a certain value necessary to achieve the desired sensitivity. Assume that the value is, for example, A in FIG. Further, in order to achieve the above-described depletion transfer, it is necessary to achieve V _FDsat > Vdp. Here, Vdp is a depletion voltage of the photodiode. The value is B in FIG. When V _FDsat <Vdp, the reverse bias voltage of the photodiode becomes the voltage of the floating diffusion region, a neutral region exists in the photodiode, and the capacitance caused by the two depletion layers described above;
The signal voltage is read out by the capacitance division with the capacitance of the floating diffusion region. At the same time, even after reading, electrons in the photodiode have an amount close to the saturated charge amount Qsat, which causes afterimages and noise.

As described above, the conventional APS is designed so that the saturated charge amount Qsat of the photodiode satisfies A <Qsat <B, that is, is in the section C.

[0018]

However, the saturation charge Qsat or the depletion voltage Vdp is easily affected by variations in the manufacturing process. For example, n
If the ion implantation dose in forming the layer fluctuates by 10%, the depletion voltage fluctuates by 0.4 Volt. As a result, the production yield is reduced.

An object of the present invention is to provide a solid-state imaging device capable of reducing residual charges remaining in a photoelectric conversion portion and performing good photoelectric conversion, and a reset method thereof.

Another object of the present invention is to increase the process latitude in manufacturing a solid-state imaging device capable of performing a desired reset operation.

[0021]

According to the present invention, there is provided a solid-state imaging device comprising: a photoelectric conversion unit; an input terminal of an amplification unit; a transfer switch for transferring charge from the photoelectric conversion unit to the input terminal; A reset switch for applying a reset voltage to a terminal, wherein a pulse signal for turning on the reset switch and turning on the transfer switch is input to the reset switch and the transfer switch. And

Further, the solid-state imaging device according to the present invention includes a photoelectric conversion unit, an input terminal of an amplification unit, a transfer switch for transferring charge from the photoelectric conversion unit to the input terminal, and a reset voltage applied to the input terminal. And a circuit for generating a pulse signal for turning on the reset switch and turning on the transfer switch.

An image input device according to the present invention includes the solid-state imaging device according to the present invention, and a mechanical shutter for determining an exposure time of the solid-state imaging device.

The reset method of the solid-state imaging device according to the present invention comprises:
In the reset method of the solid-state imaging device according to the present invention, before the charge is accumulated, the reset switch is turned on and the transfer switch is turned on to remove the charge of the photoelectric conversion unit.

[0025]

(Embodiment 1) FIG. 1 is a circuit diagram of one pixel of a solid-state imaging device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation timing. This embodiment includes a basic configuration commonly applied to each embodiment described later.

The photoelectric conversion unit PD is composed of a photodiode having a PN junction or a PIN junction. One terminal of the photoelectric conversion unit PD is held at a reference potential for applying a reverse bias, and the other terminal is connected to the transfer switch Q1. . FIG. 1 shows a configuration in which the cathode is connected to the transfer switch Q1 and electrons are transferred.

Q2 is a reset switch, one terminal of which is connected to a reference voltage source _VDD for applying a reset voltage.

Q3 is a transistor serving as an amplifying unit for outputting a signal amplified according to a signal input to a gate as an input terminal.

Q4 is a selection switch for selecting a pixel from which a signal is to be read.

The control circuit SCC is connected to the gate of each switch.
A pulse signal as shown in FIG.

FIG. 3 is a diagram schematically showing a cross section of a semiconductor chip in which a part of the circuit shown in FIG. 1 is built.
FIG. 4 is a schematic diagram showing a potential profile of each region. TX is RST under the gate of the transfer switch.
Indicates the potential energy below the gate of the reset switch.

The n-type semiconductor layer in the photoelectric conversion unit PD is shared with one main electrode of the MOS transistor constituting the transfer switch Q1, and the other main electrode of the transfer switch Q1 serves as an input terminal of the amplifier. The floating diffusion region FD. The reset switch Q2 includes a MOS transistor having a pair of main electrodes including a floating diffusion region FD and a semiconductor region VDD to which a reset reference voltage is applied.

The floating diffusion region FD is connected to the gate of the transistor Q3, but Q3 and Q4 are shown in FIG.
Is omitted.

The operation of the apparatus, FIG. 2, as shown in FIG. 4, first, enter the high-level pulse to the gate of the reset switch Q2 as phi _RST, resets the diffusion region FD to the reference voltage. The potential profile at this time is P1 in FIG.

Next, a high-level pulse is input to the gate of the transfer switch Q1 like φ _TX to reset the photoelectric conversion unit PD. At this time, since the reset switch Q2 remains ON, the potential profile becomes like P2, and the charge is transferred to the diffusion region FD.

Then, the transfer switch Q1 is turned off to separate the photoelectric conversion unit PD from the diffusion region FD. Photoelectric conversion unit P
Since all the charges remaining in D have been transferred to the diffusion region FD, the n-layer of the photoelectric conversion unit PD is completely depleted.

When the transfer switch Q1 is turned off, the accumulation of photoelectric charges in the photoelectric conversion unit PD starts.

Subsequently, the reset switch Q2 is turned off. The potential profile at this time becomes like P3.

After accumulating the electric charge for a certain period of time, the transfer switch Q1 is turned on again to transfer the electric charge stored in the photoelectric conversion unit to the floating diffusion region FD. The potential profile at this time becomes like P4. Then, after turning off the transfer switch Q1, it reads the signal amplified by the transistor Q3 to input selection pulse phi _T to the gate of the selection switch Q4.

P5 shows a potential profile when the transfer switch Q1 is turned off. The charge RC remaining in the photoelectric conversion unit PD is removed by performing the above-described reset operation again.

In this embodiment, the transfer switch Q1 is turned on with a reverse bias voltage higher than the depletion voltage set as the reset reference voltage _VDD and supplied to the diffusion region FD via the reset switch. .

In this way, a reverse bias equal to or higher than the depletion voltage is applied to the photodiode, and the remaining charge in the photodiode can be sufficiently reduced.

The saturation charge Qsat of the photodiode is shown in FIG.
In the case of taking a value between B and F, when the transfer switch is turned on in a state where the charge equivalent to the saturated charge amount is accumulated in the photodiode, V _FDsat <Vdp, There are many charges. In this state, the transfer switch Q1 is turned off, and the next accumulation starts.
When the signal charge is read again, the charge that could not be read previously is mixed.

In the present invention, before entering the next accumulation,
The diffusion region FD is fixed at a potential sufficient to apply a reverse bias of not less than the depletion voltage Vdp to the photodiode, and by turning on the transfer switch, the charge remaining in the photodiode is discharged, and the inside of the photodiode is reset. I do.

[0045] As a result, may be the charge of the photodiode during signal transfer without depletion transfer, even a condition _{V FDsat = Vres-Qsat / C} FD <Vdp, afterimage as conventionally occurring in Does not occur. Therefore, the saturated charge amount Qsat of the photodiode
Satisfies A <Qsat <F. Therefore,
The permissible amount of variation at the time of designing or manufacturing the photodiode is increased, and the manufacturing yield is improved.

[0046] Incidentally, as a method of expanding the margin of the saturation charge amount Qsat as a V _FDsat> Vdp, the reset voltage Vr
It is conceivable to increase es.

That is, the reset voltage Vres of the floating diffusion region
Is increased from Vres1 to Vres2 and is changed from the solid line X to the alternate long and short dash line Y in FIG. 5, the margin of the saturated charge amount Qsat can be extended to the section AE. However, in this case, it is necessary to increase the power supply voltage at least higher than 5 Volt. This leads to an increase in power consumption and a decrease in other chip performance such as a necessity of preparing another power supply for the sensor chip.

In the present invention, including the embodiments described below, it is a matter of course that the conductivity type, potential, charge polarity, and potential energy of the semiconductor region may be all reversed. (Embodiment 2) Another embodiment of the present invention will be further described with reference to FIGS. 6, 7 and 8. FIG.

FIG. 6 is a schematic sectional view showing another embodiment of the solid-state imaging device of the present invention. FIG. 7 is a potential diagram of the solid-state imaging device of FIG. FIG. 8 is a drive timing chart showing the operation of the solid-state imaging device of FIG. The basic circuit configuration of the solid-state imaging device of FIG. 6 is the same as that shown in FIG.

In FIG. 6, a photodiode serving as a photoelectric conversion unit is a buried photodiode, and includes a P-type well 101, an N-type region 105, and a p-type region 104 formed on the surface of a substrate. As already explained,
The buried photodiode has an oxide film 106 made of SiO ₂ by providing a p-layer having a high impurity concentration on the surface.
Suppresses dark current generated at the interface.

Further, a junction capacitance can be formed between the n-layer of the storage portion and the p-layer on the surface, so that the saturation charge of the photodiode can be increased. Reference numeral 102 denotes a gate electrode of the transfer switch Q1, reference numeral 103 denotes an N-type semiconductor region serving as a floating diffusion region FD, and reference numeral 107 denotes a gate electrode of the reset switch Q2.

In FIG. 7, PD is a photodiode section,
TX schematically shows the potential profile below the gate of the transfer switch, FD shows the floating diffusion region, and RST shows the potential profile below the gate of the reset switch section, and corresponds to FIG.

Hereinafter, the operation of the solid-state imaging device will be described.

As shown in FIG. 8, after resetting the photodiode and the floating diffusion region 103, noise reading is performed from the output terminal Vout by the same reading circuit as in FIG.

Next, as shown in FIG.
A high-level signal (transfer signal φ _TX ) is applied to one gate 102
Is applied to turn on the transfer switch Q1, and the optical signal charges accumulated in the photodiode are read out to the floating diffusion region 103 (FD) via the transfer switch. The potential diagram at this time is PP1 in FIG.

Next, as shown in FIG.
A low-level signal is applied to the first gate 102 to turn off the transfer switch Q1, and a read signal is applied to the source follower circuit to read a sensor signal. The sensor signal is read by converting the signal charge Q _sig into Q _sig / C _FD using the capacitance C _FD of the floating diffusion region FD. The potential diagram at this time is PP2 in FIG.

Next, as shown in FIG. 8, a high-level signal (reset signal φ _RST ) is applied to the reset switch Q2 to turn on the reset switch Q2 and turn on the floating diffusion region 1.
03, and further turns on the transfer switch Q1,
The photodiode is also reset. The potential diagram at this time is PP3 in FIG. Since the potential energy of the diffusion region FD is lower than the potential energy of the photodiode PD, all residual charges are removed.

Next, after the transfer switch Q1 is turned off,
The reset switch Q2 is also turned off, and the reset ends. The potential diagram after the end of the reset is PP4 in FIG.

As described above, the floating diffusion region is fixed at a voltage to which a reverse bias higher than the depletion voltage can be applied.
By performing the operation of opening the transfer switch, the reset operation for depleting the photodiode is performed before accumulation without separately providing an overflow drain element or a reset element for the photodiode, thereby expanding the allowable range of manufacturing variations of the photodiode and increasing the yield. Can be improved. (Embodiment 3) FIG. 9 is an equivalent circuit diagram of one pixel portion of the solid-state imaging device according to the present embodiment. The photodiode PD in FIG. 9 is a buried photodiode as described above, Q1 is a MOS transistor serving as a transfer switch for transferring photocharge from the photodiode to the floating diffusion region FD, and Q2 is for resetting the floating diffusion region FD. Is a MOS transistor as a reset switch, Q3 is an input MOS transistor of a source follower for outputting a voltage of the floating diffusion region FD, and Q4 is a MOS transistor as a selection switch for selecting a pixel. The input follower input MOS transistor Q3 serves as an amplifier, and the floating diffusion region FD serves as an input terminal of the amplifier.

FIG. 10 is a circuit diagram of a solid-state imaging device in which 2 × 2 pixels PX shown in FIG. 9 are arranged in a matrix.

In the pixels PX1 and PX2 in the first row,
The selection signal line 506 is shared and the pulse signal φ_T1Is input
It is supposed to be. Similarly, the pixels PX3 in the second row,
Also in PX4, the selection signal line 506 is shared and controlled.
Pulse signal φ from circuit SCC _T2Is entered
ing.

In the pixels PX1 and PX3 in the first column, the signal output line 504 is shared and connected to the load array 511 and the memory 512. Similarly, the pixel P in the second column
In X2 and PX4, the signal output line 504 is shared and connected to the load array 511 and the memory 512. The memory 512 has a capacity for accumulating noise components and a capacity for accumulating signal components, and accumulates an output signal in these capacities when a sampling pulse is input.

A reset circuit 502 and a transfer control line 506 are supplied to a control circuit SCC for generating each pulse signal so that a pulse signal for turning on a corresponding transistor can be input simultaneously to all pixels or sequentially for each row. It is connected.

The signal read to the memory 512 is scanned by a scanning circuit 513 such as a shift register and output from an output terminal SG.

FIG. 11 is a driving timing chart showing driving pulses used when reading out one pixel.

Before starting the accumulation operation, with the reset switch Q2 turned on, a pulse φ _TX is input to the transfer control line 506 to turn on the transfer switch Q1 as shown at T1.
Then, the inside of the photodiode is reset to be depleted.

For example, when the voltage V _DD of the power supply line 501 is 5
Volt, and with the reset switch Q2 turned on,
The voltage of the floating diffusion region is set to about 3.5 Volt. At this time, the depletion voltage Vdp of the photodiode is about 2.
Since the voltage is 5 Volt, the photodiode is depleted by the reset operation of the photodiode. Depletion of the photodiode can be confirmed by an afterimage experiment.

Thereafter, accumulation is performed for 1/30 seconds. In this embodiment, the reset switch Q2 keeps the ON state during the main period during the accumulation period. Thereafter, to perform reading, the reset switch Q2 is turned off as in T3.
Then, the diffusion region FD is brought into a floating state. Then, the selection switch Q4 for reading is turned on like T4.
I do. Input MOS transistor Q3 and signal output line 504
The source follower consisting of the load 511 connected to the
A voltage corresponding to the voltage of the floating diffusion region is output to the signal output line 504. This output is sampled in the memory 512.

[0069] In the read period T _R in this example, while turning off the transfer switch Q1, the change from on to off the reset switch Q2, by turning on the selection switch Q4, to read the noise component of the pixel Can be. Therefore, a noise component is stored in the noise storage capacity of the memory 512 by the sampling pulse T5.

[0070] Then, after turned on by the pulse T6 the transfer switch Q1 in the read period T _R, by inputting the sampling pulses T7, stores signal component in the signal storage capacity of the memory 512.

The noise component and the signal component obtained in this manner are obtained by a subtracter such as a differential amplifier to obtain a differential output, whereby an output signal with reduced noise can be obtained.

At the time of sampling the signal component, since the diffusion region FD is in a floating state, the voltage V
_FD is V _FD = Vres−Q / C _FD (where Q indicates the amount of transferred charges), that is, Q / C from the reset voltage Vres.
_The voltage _{drops by FD} . Since a signal corresponding to the voltage is output to the signal output line 504, the signal is sampled.

Before the next accumulation, the reset switch Q
2 is turned on, the transfer switch Q1 is opened, and the inside of the photodiode is depleted.

In this example, when the photoelectric conversion characteristics were evaluated from the signals obtained by performing the above-described operations, good linearity was confirmed. When the output became saturated, the voltage of the floating diffusion region dropped to 1.5 Volt.

As a comparative example, when the pulse φ _TX to the transfer switch Q1 was always set to the low level and the afterimage characteristics were evaluated, an afterimage of 20 to 30% was confirmed.

The results are summarized in the following table.

[0077]

[Table 1] (Embodiment 4) Next, another example of the read operation timing of the solid-state imaging device as shown in FIG. 10 will be described.
The reset operation is as described above.

FIG. 10 shows a matrix of 2 × 2 pixels, while FIG. 12 shows operation timings for any three rows of a matrix of three or more rows.

[0079] period 7a, 7b, 7c correspond to the reading period T _R in FIG. 11, respectively. On the other hand, period 7A,
Reference numerals 7B and 7C denote horizontal scanning periods in which signals of each row stored in the memory 512 are sequentially output from the terminal SG by the scanning circuit 513 in a time-series manner. More specifically, in the readout period 7a, reading is performed from the pixels in the (n-1) th row, and the noise component and the optical signal component are written in the line memory 512 for one row. Next, the signals written to the line memory 512 during the horizontal scanning period 7A are sequentially read in time series. At least during this horizontal scanning period 7A, all the photodiodes are accumulating. Next, reading was performed from the pixels in the n-th row during the reading period 7b, and signals were read from the line memory 512 during the horizontal scanning period 7B.
The signals from the pixels in each row were read out in the rolling shutter mode in which the readout operation and the readout operation from the line memory were performed in row units as described above. As a result, a good moving image without an afterimage can be obtained. (Embodiment 5) FIG. 13 is a schematic diagram showing an image input device using the solid-state imaging device 1 according to the present invention. A mechanical shutter 2 is provided in an optical system 3 such as a lens, and the exposure time (accumulation time) of the solid-state imaging device 1 is controlled by the shutter 2. The reset operation is as described above.

The operation of this image input device is as follows.

At the beginning of the shutter open period, the reset operation of the photodiode is performed in the reset period 8 s,
All previously accumulated signals are removed. Thereafter, accumulation is started, and the shutter is closed after a lapse of a predetermined time. In the readout period 8a, the signals of the pixels in the (n-1) th row are read out to a line memory or the like, and in the horizontal scanning period 8A, the signals held in the line memory 512 are sequentially read out using the scanning circuit 513. Next, readout period 8
The signal of the pixel in the n-th row was read out to the line memory 512 at b, and the signals held in the line memory were read out sequentially using the scanning circuit 513 during the horizontal scanning period 8B. Thereafter, signals were read from the pixels in each row by the same operation. In this method, since the accumulation time of all pixels is the same at the same time,
It is suitable for capturing a still image. (Embodiment 6) FIG. 15 shows a sensor section having pixels arranged in a matrix, a bus line for sending a signal from the sensor section to an A / D converter, and holding signals from all A / D converted pixels. 1 shows a solid-state imaging device having a memory unit.

FIG. 16 shows the operation timing of the solid-state imaging device shown in FIG. The reset operation is as described above.

In the reset period 9S, all the pixels are reset.

After a predetermined storage time has elapsed, the mechanical shutter 2 is closed to terminate the storage of optical information.

In the readout period 9a, a signal from a pixel on the (n-1) th row is input to an A / D converter via a bus line, and an analog signal is converted into a digital signal.
A digital signal is written to a predetermined address in the memory unit.

Next, in the read period 9b, a signal is read from the pixels in the n-th row, A / D converted, and the pixel signals in the n-th row are written to another address in the memory section.

Then, in the read period 9c, n-
The pixel signals in the first row are read out and written to another address of the memory unit.

After the collective reset of the photodiodes, accumulation is performed, signals of each row are read out, signals from the pixels of each row are input to an A / D converter through a bus line, and digitized through the A / D converter. By writing the obtained image signal to a memory cell prepared for each pixel, it is possible to appropriately cope with both moving image and still image capturing. In particular, in the case of a moving image, the image processing IC can process the image of the previous frame during the accumulation period. (Embodiment 7) FIG. 17 shows another example of solid-state imaging according to the present invention.

The sensor section is divided into four blocks, and each block is provided with a horizontal and vertical scanning selection circuit which can operate individually.

Each scan selection circuit can select a row and a column at an independent timing by the scan control IC.

The read pixel signal is A / D converted and written into the memory unit.

In this example, based on the image signal of the previous frame,
The accumulation time of the next frame can be determined for each row.

For example, in the first frame as shown in FIG. 18, the photodiode is reset in the reset period 10S, and the accumulation is started. Thereafter, signals are sequentially read out for each row in the readout periods 10a to 10c and written into the memory unit.

When there is a signal that can be regarded as a saturation signal among the image signals stored in the memory unit, the storage time can be changed by changing the reset period generation timing in the next frame.

For example, when strong light is incident on the pixels on the nth and n + 1th rows and the signals from the pixels on the nth and n + 1th rows are saturated, as shown in FIG. The reset periods 9Sn and 9Sn + 1 of the n-th row and the (n + 1) -th row are delayed based on the determination result of the scanning control IC, and the accumulation time is set to n−
Make it shorter than the first line.

In this embodiment, by controlling the accumulation time by the scanning control IC, the relationship between the light quantity and the sensor output as shown by C1 in FIG. 20 can be obtained. Specifically, the reset operation of the photodiode of the present invention is delayed from the reset operation of the (n−1) th row, and the accumulation time of the (n) th row and the (n + 1) th row is set to about half of the (n−1) th row. As a result, when the reset periods of all the rows occur simultaneously, C2 in FIG.
As shown in Fig. 2, even when the saturation output is originally required, the accumulation time is shortened.
An output having a gradation like C1 of 0 can be obtained. (Embodiment 8) In the solid-state imaging device of the present invention, by setting the voltage applied to the transfer gate to a predetermined value, a part of the electric charge accumulated in the photodiode is held at the reset potential during the accumulation time. Blooming is prevented by flowing out to the diffusion region FD.

For example, by making the low-level pulse voltage at φ _TX in FIG. 2 slightly higher than the voltage of the p-type well 1201, the potential barrier of the transfer gate portion TX is slightly lowered and excess charges are transferred to the diffusion region FD. Pour out.

More specifically, the LOW level of the MOS transistor Q1 of the transfer switch in FIGS.
In contrast to the ground level, in the present embodiment, the LOW level is increased by 0.3 Volt from the ground level. As a result, the potential diagram of the photodiode and the transfer switch is as shown by S1 in FIG. Note that FIG.
S2 of FIG. 2 is a potential diagram when the LOW level is set to the GND level (0 Volt).

As in the present embodiment, the MOS of the transfer switch
By increasing the LOW level of the transistor Q1, the lowest potential portion becomes the channel portion TX of the transfer switch, and the transfer switch functions as a horizontal overflow drain. That is, during the accumulation period, the diffusion region is set to a fixed voltage, the gate voltage of the transfer switch is controlled, and the transfer switch is opened halfway, so that the transfer switch functions as a horizontal overflow drain. As a result, crosstalk is controlled.

As described above, according to each embodiment of the present invention, before starting the next accumulation, the floating diffusion region is fixed to a voltage to which a reverse bias higher than the depletion voltage can be applied, and the transfer switch is set. Can be opened, the following effects can be obtained by discharging the charge remaining in the photoelectric conversion unit and resetting the inside of the photoelectric conversion unit. (1) The transfer residue caused by the variation in the charge handled by the photodiode due to the manufacturing variation can be removed. (2) A solid-state imaging device with no afterimage can be provided without increasing the power supply voltage and without increasing the pixel size.

As for the reset operation of the photodiode, there is a technique disclosed in Japanese Patent Publication No. Hei 7-105915 for resetting using a separately provided switching element of the photodiode. It was difficult to reduce the size.

The photodiode in the case of the technique disclosed in the above publication is provided in a well, and is formed of a simple PN junction formed of a high-concentration impurity region of a conductivity type opposite to that of the well. However, large reset noise determined by the junction capacitance of the photodiode remains. On the other hand, in the present embodiment, since the reset is to deplete the embedded photodiode,
The reset noise is almost negligible.

Some CCDs have an overflow drain function by a vertical overflow drain and a collective reset function of pixels. In this case, reset is performed to deplete the buried photodiode as in the present embodiment. However, the element structure of the vertical overflow drain is completely different from that of a surface device such as a MOS transistor, and is an element extending in the depth direction. Although it does not occupy the area of the pixel, it is difficult to control the impurity profile in the depth direction. In addition, resetting of pixels can be performed only in a batch.

In the present invention, the transfer switch functions as a horizontal overflow drain by setting the floating diffusion region to a fixed voltage during the accumulation period, controlling the gate voltage of the transfer switch, and half-opening the transfer switch. The pixel size can be reduced without the necessity of providing a vertical overflow drain which is difficult to manufacture and a horizontal overflow drain element which hinders the reduction in pixel size.

If a photodiode is reset by using a transfer switch after reading a signal into the floating diffusion region for each row, a so-called rolling shutter operation can be performed.

Further, by using a decoder for the scanning part of the control electrode of the transfer switch, it is possible to reset the photodiode of an arbitrary pixel.

On the other hand, the floating diffusion region is fixed at a voltage to which a reverse bias higher than the depletion voltage can be applied,
If the operation of opening the transfer switch is performed collectively for all pixels, it is possible to function as an electronic shutter in an electronic still camera.

As described above, according to the present invention, the floating diffusion region is fixed at a voltage to which a reverse bias higher than the depletion voltage can be applied, and the operation of opening the transfer switch can be performed. The depletion reset operation is performed before accumulation, so that the manufacturing tolerance of the solid-state imaging device can be widened and the yield can be improved.

According to the present invention, the residual signal charge can be discharged at the time of reset even under the condition that all the charges cannot be transferred at the time of reading.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a solid-state imaging device according to a preferred embodiment of the present invention.

FIG. 2 is a drive timing chart for explaining an operation of the solid-state imaging device according to the preferred embodiment of the present invention;

FIG. 3 is a schematic sectional view of a main part of a solid-state imaging device according to a preferred embodiment of the present invention.

FIG. 4 is a schematic diagram showing how a potential profile of a main part of a solid-state imaging device according to a preferred embodiment of the present invention changes.

FIG. 5 is a graph illustrating a saturation charge amount dependency of a voltage of a floating diffusion region for explaining a reset voltage required for depletion of a photoelectric conversion unit.

FIG. 6 is a schematic sectional view of a main part of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 7 is a schematic diagram showing how a potential profile of a main part of a solid-state imaging device according to another preferred embodiment of the present invention changes.

FIG. 8 is a drive timing chart for explaining an operation of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 9 is a circuit diagram of one pixel of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 10 is a circuit diagram of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 11 is a drive timing chart for explaining an operation of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 12 is a drive timing chart for explaining another example of the operation timing of the solid-state imaging device used in the present invention.

FIG. 13 is a schematic diagram of an image input device according to the present invention.

FIG. 14 is a drive timing chart for explaining an example of operation timing of the image input device used in the present invention.

FIG. 15 is a circuit diagram of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 16 is a drive timing chart for explaining another example of the operation timing of the image input device used in the present invention.

FIG. 17 is a circuit diagram of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 18 is a drive timing chart for explaining another example of the operation timing of the image input device used in the present invention.

FIG. 19 is a drive timing chart for explaining another example of the operation timing of the image input device used in the present invention.

FIG. 20 is a graph showing the dependence of each output on the incident light amount when the accumulation time control is used and when it is not used.

FIG. 21 is a sectional view of a main part of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 22 is a schematic diagram showing a change in potential profile of a main part of a solid-state imaging device according to another preferred embodiment of the present invention.

FIG. 23 is a cross-sectional view of the solid-state imaging device for explaining depletion transfer.

FIG. 24 is a graph showing the dependence of the voltage required for the depletion transfer at the time of reading on the saturation charge.

[Explanation of symbols]

 PD photoelectric conversion unit Q1 transfer switch Q2 reset switch Q3 amplifying unit Q4 selection switch 101 P-type well (PWL) 102 gate electrode of transfer switch 103 floating diffusion region 104 p-region on surface 105 N-type region 106 oxide film 107 gate of reset switch electrode

Claims (32)

[Claims] 1. A photoelectric conversion unit, an input terminal of an amplification unit, a transfer switch for transferring charges from the photoelectric conversion unit to the input terminal, and a reset switch for applying a reset voltage to the input terminal. And a pulse signal for turning on the reset switch and turning on the transfer switch is input to the reset switch and the transfer switch. 2. The solid-state imaging device according to claim 1, wherein a reverse bias voltage sufficient to almost completely deplete the semiconductor region of the photoelectric conversion unit is set as a depletion voltage via the reset switch. Wherein the voltage applied to the input terminal is set higher than the depletion voltage. 3. The solid-state imaging device according to claim 1, wherein said photoelectric conversion unit is an embedded photodiode. 4. The solid-state imaging device according to claim 1, wherein the transfer switch is a switch that depletes and transfers the charge accumulated in the photoelectric conversion unit. 5. The solid-state imaging device according to claim 1, wherein the transfer switch is a switch that transfers a part of the electric charge stored in the photoelectric conversion unit while leaving a part of the electric charge. 6. The solid-state imaging device according to claim 1, wherein when the transfer switch and the reset switch are on, a reset voltage is set so that potential energy of the input terminal is lower than potential energy of the photoelectric conversion unit. Is a solid-state imaging device. 7. The solid-state imaging device according to claim 1, wherein the transfer switch is configured to be in a half-open state during a storage period and to flow excess charge to the input terminal. 8. The solid-state imaging device according to claim 1, wherein the reset for turning on both the transfer switch and the reset switch is performed for each row of the photoelectric conversion device. 9. The solid-state imaging device according to claim 1, wherein the reset in which both the transfer switch and the reset switch are turned on is performed simultaneously for all rows. 10. The solid-state imaging device according to claim 1, wherein a reset occurrence timing at which both the transfer switch and the reset switch are turned on is made different according to the amount of light incident on the photoelectric conversion unit. . 11. The solid-state imaging device according to claim 1, wherein the photoelectric conversion unit, an input terminal of the amplification unit, and the transfer switch are provided on a same semiconductor substrate. 12. The solid-state imaging device according to claim 1, wherein said input terminal is a diffusion region. 13. The solid-state imaging device according to claim 1, wherein the photoelectric conversion unit includes a first conductive type first semiconductor region in a semiconductor substrate and a second conductive type first semiconductor region in the first semiconductor region. A solid-state imaging device which is a photodiode including two semiconductor regions and a third semiconductor region of a first conductivity type between the second semiconductor region and an insulating film formed on a main surface of the semiconductor substrate. 14. An image input device comprising: the solid-state imaging device according to claim 1; and a mechanical shutter for determining an exposure time of the solid-state imaging device. 15. The image input device according to claim 14, wherein a photocharge accumulation time is determined by a reset operation of the solid-state imaging device and an opening / closing operation of the mechanical shutter. 16. The method for resetting a solid-state imaging device according to claim 1, wherein before resetting the charge, the reset switch is turned on and the transfer switch is turned on to remove the charge of the photoelectric conversion unit. A reset method characterized by the above-mentioned. 17. A photoelectric conversion unit, an input terminal of an amplification unit,
A transfer switch for transferring a charge from the photoelectric conversion unit to the input terminal; and a reset switch for applying a reset voltage to the input terminal, wherein the reset switch is turned on and the transfer switch is turned on. A solid-state imaging device having a circuit for generating a pulse signal for turning on the solid-state imaging device. 18. The solid-state imaging device according to claim 17, wherein when a reverse bias voltage sufficient to substantially deplete the semiconductor region of the photoelectric conversion unit is set as a depletion voltage, the reset switch is connected to the semiconductor device. A solid-state imaging device, wherein a voltage applied to the input terminal is set higher than the depletion voltage. 19. The solid-state imaging device according to claim 17, wherein said photoelectric conversion unit is an embedded photodiode. 20. The solid-state imaging device according to claim 17, wherein the transfer switch is a switch that depletes and transfers the charge accumulated in the photoelectric conversion unit. 21. The solid-state imaging device according to claim 17, wherein the transfer switch is a switch that transfers a part of the charge stored in the photoelectric conversion unit while leaving a part of the charge. 22. The solid-state imaging device according to claim 17, wherein when the transfer switch and the reset switch are on, a reset voltage is set so that potential energy of the input terminal is lower than potential energy of the photoelectric conversion unit. Is a solid-state imaging device. 23. The solid-state imaging device according to claim 17, wherein the transfer switch is configured to be in a half-open state during a storage period and to flow surplus charge to the input terminal. 24. The solid-state imaging device according to claim 17, wherein the reset in which both the transfer switch and the reset switch are turned on is performed for each row of the photoelectric conversion device. 25. The solid-state imaging device according to claim 17, wherein the reset in which both the transfer switch and the reset switch are turned on is performed simultaneously on all rows. 26. The solid-state imaging device according to claim 17, wherein a reset generation timing at which both the transfer switch and the reset switch are turned on is made different according to the amount of light incident on the photoelectric conversion unit. . 27. The solid-state imaging device according to claim 17, wherein the photoelectric conversion unit, an input terminal of the amplification unit, and the transfer switch are provided on a same semiconductor substrate. 28. The solid-state imaging device according to claim 17, wherein said input terminal is a diffusion region. 29. The solid-state imaging device according to claim 17, wherein the photoelectric conversion unit includes a first conductive type first semiconductor region in a semiconductor substrate and a second conductive type first semiconductor region in the first semiconductor region. A solid-state imaging device which is a photodiode including two semiconductor regions and a third semiconductor region of a first conductivity type between the second semiconductor region and an insulating film formed on a main surface of the semiconductor substrate. 30. An image input apparatus comprising: the solid-state imaging device according to claim 17; and a mechanical shutter for determining an exposure time of the solid-state imaging device. 31. The image input apparatus according to claim 30, wherein a reset operation of the solid-state imaging device and an opening / closing operation of the mechanical shutter determine an accumulation time of photocharge. 32. The method of resetting a solid-state imaging device according to claim 17, wherein before resetting the charge, the reset switch is turned on and the transfer switch is turned on.
A reset method comprising: removing charges from the photoelectric conversion unit.