JP2000200867A - Semiconductor package and assembling method thereof - Google Patents

Semiconductor package and assembling method thereof

Info

Publication number
JP2000200867A
JP2000200867A JP11001325A JP132599A JP2000200867A JP 2000200867 A JP2000200867 A JP 2000200867A JP 11001325 A JP11001325 A JP 11001325A JP 132599 A JP132599 A JP 132599A JP 2000200867 A JP2000200867 A JP 2000200867A
Authority
JP
Japan
Prior art keywords
bonding
lead
support substrate
leads
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11001325A
Other languages
Japanese (ja)
Inventor
Shigetoshi Ito
重寿 伊藤
Norio Maejima
紀男 前島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP11001325A priority Critical patent/JP2000200867A/en
Publication of JP2000200867A publication Critical patent/JP2000200867A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package and an assembling method thereof, where a bonding failure is prevented from occurring between the tip of a lead and a bonding wire. SOLUTION: In a semiconductor package, leads 301 to 304 are arranged to extend on a support board 2, and close contact grooves 31 to 34 are each provided to the inner parts of the leads 301 to 304. As the leads 301 to 304 are provided with the close contact grooves 31 to 34, the rear parts of the bonding regions of the tips of the inner parts of the leads can be brought into close contact with the surface of the support board 2 by pressing the tips of the inner parts with a lead pressing jig 12. Bonding wires 5 are each bonded to the tips of the inner parts by ultrasonic bonding. The close contact grooves 31 to 34 may be recessed, V-shaped or U-shaped in cross section.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体パッケージ
及びその組立方法に関し、特に電力用半導体素子（パワ
ーデバイス）やパワーＩＣを搭載した半導体チップとリ
ード先端との間をボンディングワイヤを介して接続する
構造を有する樹脂封止型半導体パッケージ及びその組立
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of assembling the same, and more particularly, to connecting a semiconductor chip mounted with a power semiconductor element (power device) or a power IC to a lead tip via a bonding wire. The present invention relates to a resin-sealed semiconductor package having a structure and an assembling method thereof.

【０００２】[0002]

【従来の技術】図６は従来技術に係る樹脂封止型半導体
パッケージの一部分を示す平面図である（図６には、内
部の構成をわかり易くするために、樹脂封止体の上側部
分を便宜的に取り除いた状態を示す）。図６に示すよう
に、樹脂封止型半導体パッケージは、支持基板１２０
と、支持基板１２０上の中央部分にマウントされた半導
体チップ１４０と、複数本のリード１３０〜１３９と、
これらを封止する樹脂封止体１１０とを備えて構成され
ている。2. Description of the Related Art FIG. 6 is a plan view showing a part of a resin-sealed semiconductor package according to the prior art (FIG. 6 shows an upper part of a resin-sealed body for easy understanding of the internal structure. Shows the state that it was removed.) As shown in FIG. 6, the resin-encapsulated semiconductor package is
A semiconductor chip 140 mounted at a central portion on the support substrate 120, a plurality of leads 130 to 139,
And a resin sealing body 110 for sealing them.

【０００３】半導体チップ１４０の表面上の周縁に沿っ
た領域には複数のボンディングパッド１４１が配設さ
れ、このボンディングパッド１４１とリード１３０〜１
３９のそれぞれのインナー部先端（ボンディング領域）
との間はボンディングワイヤ１５０を通して電気的に接
続される。ボンディングワイヤ１５０は樹脂封止型半導
体パッケージの組立プロセス中に周知のワイヤボンディ
ング法によりボンディングされる。すなわち、図示しな
いワイヤボンディング装置のキャピラリィにより、ボン
ディングワイヤ１５０の一端が半導体チップ１４０のボ
ンディングパッド１４１にボンディングされ、他端がリ
ード１３０〜１３９のそれぞれのインナー部先端にボン
ディングされている。ボンディングにおいては、ボンデ
ィングパッド１４１表面、インナー部先端表面のそれぞ
れに平行な方向においてキャピラリィに超音波振動が加
えられる。また、ボンディングにおいては、半導体チッ
プ１４０、リード１３０〜１３９のそれぞれがヒータに
より加熱されている。A plurality of bonding pads 141 are provided in a region along the periphery on the surface of the semiconductor chip 140, and the bonding pads 141 and the leads 130 to 1 are provided.
39 inner tip (bonding area)
Are electrically connected through a bonding wire 150. The bonding wire 150 is bonded by a well-known wire bonding method during an assembly process of the resin-sealed semiconductor package. That is, one end of the bonding wire 150 is bonded to the bonding pad 141 of the semiconductor chip 140 and the other end is bonded to the tip of each of the inner portions of the leads 130 to 139 by a capillary of a wire bonding apparatus (not shown). In bonding, ultrasonic vibration is applied to the capillary in a direction parallel to the surface of the bonding pad 141 and the surface of the tip of the inner portion. In bonding, each of the semiconductor chip 140 and the leads 130 to 139 is heated by a heater.

【０００４】[0004]

【発明が解決しようとする課題】前述の樹脂封止型半導
体パッケージにおいて、平面パターン上重複する位置に
まで延在して、インナー部が支持基板１２０上に配置さ
れたリード１３０、１３１、１３５、１３６のそれぞれ
のインナー部先端とボンディングパッド１４１との間の
ボンディングに際し、以下の点について配慮がなされて
いなかった。In the above-described resin-encapsulated semiconductor package, the leads 130, 131, 135, which extend to a position overlapping the planar pattern and whose inner portion is disposed on the support substrate 120, are provided. At the time of bonding between the tip of each inner portion of the 136 and the bonding pad 141, the following points were not considered.

【０００５】リード１３０、１３１、１３５、１３６の
それぞれのインナー部は、リード１３０、１３１、１３
５、１３６と支持基板１２０との間の電気的絶縁を十分
に取るために、支持基板１２０表面上から所定距離、例
えば、０．３mm乃至０．５mm程度だけ離間して配置され
ている。ワイヤボンディング時においては、図６中、符
号１６０を付して輪郭を破線で示す押え治具でインナー
部を支持基板１２０表面に押え付けた状態で、インナー
部先端にボンディングワイヤ１５０がボンディングされ
る。しかしながら、押え治具１６０でインナー部を押え
付けてもインナー部の弾力性によりインナー部、特にイ
ンナー部先端のボンディング領域の大半が支持基板１２
０表面から浮き上がってしまい、インナー部先端にボン
ディングワイヤ１５０を強く押し付けることができな
い。さらにこの浮き上がりによりインナー部先端が支持
基板１２０表面を滑ってしまい、ボンディング面に超音
波振動による擦り付けを充分に発生させることができな
い。この結果、リード１３０、１３１、１３５、１３６
のそれぞれとボンディングワイヤ１５０との間にボンデ
ィング不良を生じる可能性があり、樹脂封止型半導体パ
ッケージの電気的信頼性を低下させてしまうという問題
があった。The inner portions of the leads 130, 131, 135, and 136 are connected to the leads 130, 131, 13, respectively.
In order to obtain sufficient electrical insulation between the support substrates 120 and 5,136, they are arranged at a predetermined distance from the surface of the support substrate 120, for example, about 0.3 mm to 0.5 mm. At the time of wire bonding, the bonding wire 150 is bonded to the tip of the inner portion in a state where the inner portion is pressed against the surface of the support substrate 120 by a pressing jig denoted by reference numeral 160 in FIG. . However, even if the inner portion is pressed by the holding jig 160, the inner portion, particularly most of the bonding region at the tip of the inner portion, is mostly used because of the elasticity of the inner portion.
Thus, the bonding wire 150 is lifted from the surface of the inner portion and cannot be strongly pressed against the tip of the inner portion. Further, the lifting causes the tip of the inner portion to slide on the surface of the support substrate 120, so that the bonding surface cannot be sufficiently rubbed by ultrasonic vibration. As a result, the leads 130, 131, 135, 136
There is a possibility that a bonding failure may occur between each of these and the bonding wire 150, and there is a problem that the electrical reliability of the resin-encapsulated semiconductor package is reduced.

【０００６】さらに、このようなボンディング不良を生
じる可能性がある樹脂封止型半導体パッケージは製品と
しては不良品として取り扱われるので、組立プロセス上
の歩留まりを低下させてしまうという問題があった。Further, since a resin-encapsulated semiconductor package which may cause such a bonding failure is treated as a defective product, there is a problem that the yield in the assembly process is reduced.

【０００７】本発明は上記課題を解決するためになされ
たものである。従って、本発明の目的は、支持基板上に
重複配置されたリード先端とボンディングワイヤとの間
のボンディング不良を防止することができ、電気的信頼
性を向上させることができる半導体パッケージを提供す
ることである。The present invention has been made to solve the above problems. Accordingly, an object of the present invention is to provide a semiconductor package which can prevent a bonding failure between a tip end of a lead overlapped on a support substrate and a bonding wire and can improve electrical reliability. It is.

【０００８】さらに、本発明の他の目的は、ボンディン
グ不良に伴う製品不良の発生を減少させることができ、
歩留まりを向上させることができる半導体パッケージの
組立方法を提供することである。Still another object of the present invention is to reduce the occurrence of product defects due to bonding defects,
An object of the present invention is to provide a method of assembling a semiconductor package capable of improving the yield.

【０００９】[0009]

【課題を解決するための手段】上記課題を解決するため
に、本発明は、半導体チップを搭載する支持基板と、こ
の支持基板上にまで延在して配置されたリードと、この
リードの一部と支持基板とを少なくともモールドする樹
脂封止体とを備え、ボンディング領域近傍の、リードの
表面にこのリードを横断する密着用溝を備えた半導体パ
ッケージであることを第１の特徴とする。ここで、「ボ
ンディング領域」とは、半導体チップから延びるボンデ
ィングワイヤがいわゆるセカンドボンディング（第２ボ
ンディング）される領域の意である。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a support substrate on which a semiconductor chip is mounted, a lead extending over the support substrate, and one of the leads. A first feature is that the semiconductor package is provided with a resin sealing body for molding at least a portion and a support substrate, and is provided with a contact groove near the bonding area on the surface of the lead and crossing the lead. Here, the “bonding region” means a region where a bonding wire extending from the semiconductor chip is so-called second-bonded (second bonding).

【００１０】本発明の第１の特徴に係る半導体パッケー
ジにおいては、密着用溝で支持基板上にリード先端を密
着させ、位置の変動がない状態でリード先端とボンディ
ングワイヤとの間をボンディングすることができる。従
って、ボンディングに必要な温度、圧力、場合によって
は超音波パワー等が十分に印加できるので、リード先端
とボンディングワイヤとの間を電気的かつ機械的、ある
いは金属学的に確実に接続することができる。従って、
ボンディング不良を防止することができるので、半導体
パッケージの電気的信頼性を向上させることができる。In the semiconductor package according to the first aspect of the present invention, the tip of the lead is brought into close contact with the support substrate by the contact groove, and the lead tip and the bonding wire are bonded in a state where the position does not change. Can be. Therefore, the temperature, pressure, and in some cases, ultrasonic power required for bonding can be sufficiently applied, so that electrical and mechanical or metallurgical connection between the lead tip and the bonding wire can be reliably achieved. it can. Therefore,
Since bonding failure can be prevented, the electrical reliability of the semiconductor package can be improved.

【００１１】本発明の第１の特徴において、複数本のリ
ードを備える場合には必ずしもすべてのリードに密着用
溝を備える必要はなく、少なくとも支持基板上に延在し
て、即ち平面パターン上重複して配置されるリードに密
着用溝が形成されていればよい。さらに、本発明の第１
の特徴に係る半導体パッケージにおいて、密着用溝は、
リードに外力を加えると少なくともリード先端裏面を確
実に支持基板表面に密着させるために、リードの形状変
化を容易にする（リードを変形し易くする）溝の意で使
用されている。従って、このような機能を有する溝であ
れば、密着用溝の形状には限定されず、例えば密着用溝
には凹型溝（溝部の底部角部がほぼ直角）、Ｖ型溝、Ｕ
型溝（溝部の底部角部が丸みを帯びている）等の種々の
断面形状の溝が使用できる。しかし、Ｖ型溝の場合は、
押さえ治具でリードを支持板に押さえたときにその角部
からクラックが生じ易い。従って、凹型やＵ型の断面形
状が望ましい。これらの溝は、リードフレームの形成前
又は形成後に、エッチング加工や機械加工で容易に形成
することができる。リードの表面に形成された密着用溝
の深さは、リードの支持基板への密着を容易に行うこと
ができ、しかもリードの機械的強度を充分に確保しつ
つ、搭載される半導体チップの電流容量を充分に確保す
るために、リードの板厚の1/3〜1/2の範囲内の寸法で形
成されることが好ましい。In the first feature of the present invention, when a plurality of leads are provided, it is not always necessary to provide all of the leads with a contact groove, and at least the lead extends over the support substrate, that is, overlaps on a plane pattern. It is only necessary that a groove for contact be formed in the lead arranged in such a manner. Further, the first aspect of the present invention
In the semiconductor package according to the above feature, the contact groove is
When external force is applied to the lead, at least the back surface of the tip of the lead is surely brought into close contact with the surface of the support substrate. Therefore, as long as the groove has such a function, the shape of the groove for contact is not limited. For example, the groove for contact is a concave groove (the bottom corner of the groove is substantially at a right angle), a V-shaped groove, and a U-shaped groove.
A groove having various cross-sectional shapes such as a mold groove (a bottom corner of the groove is rounded) can be used. However, in the case of a V-shaped groove,
When the lead is pressed against the support plate by the holding jig, cracks are likely to occur from the corners. Therefore, a concave or U-shaped cross section is desirable. These grooves can be easily formed by etching or machining before or after forming the lead frame. The depth of the contact groove formed on the surface of the lead allows the lead to easily adhere to the support substrate, and ensures the mechanical strength of the lead while maintaining the current of the mounted semiconductor chip. In order to secure a sufficient capacity, the lead is preferably formed to have a dimension in the range of 1/3 to 1/2 of the thickness of the lead.

【００１２】本発明の第２の特徴は、支持基板上に半導
体チップをマウントし、密着用溝を備えたリードを支持
基板上に配置する工程と、リードの密着用溝よりも先端
部の所定の領域を支持基板側に押し付け、リードを折り
曲げ、この所定の領域を支持基板に密着させる工程と、
半導体チップのボンディングパッドにボンディングワイ
ヤの一端を第１ボンディングする工程と、所定の領域に
対してボンディングワイヤの他端を第２ボンディングす
る工程とを少なくとも有する半導体パッケージの組立方
法であることである。ここで、「所定の領域」とは、第
１の特徴において述べた「ボンディング領域」を含む領
域である。A second feature of the present invention is a step of mounting a semiconductor chip on a support substrate and disposing a lead provided with a contact groove on the support substrate; Pressing the area on the support substrate side, bending the lead, and bringing the predetermined area into close contact with the support substrate;
An object of the present invention is to provide a semiconductor package assembling method including at least a step of first bonding one end of a bonding wire to a bonding pad of a semiconductor chip and a step of second bonding the other end of the bonding wire to a predetermined region. Here, the “predetermined region” is a region including the “bonding region” described in the first feature.

【００１３】このような半導体パッケージの組立方法に
おいては、リードを支持基板側に押し付けると、密着用
溝によりリードの形状変化を助長し、リード先端の位置
が変動しないようにリード先端を支持基板に密着させる
ことができる。この密着状態でリード先端とボンディン
グワイヤとの間をボンディングすることにより、リード
先端とボンディングワイヤとの間の電気的かつ機械的な
接続を確実に行うことができ、ボンディング不良を防止
することができる。従って、半導体パッケージの組立プ
ロセスにおいて、不良品の発生を減少させることができ
るので、歩留まりを向上させることができる。なお、本
発明の第２の特徴に係る半導体パッケージの組立方法に
おいて、支持基板上に延在して配置されたリード先端は
必ずしも半導体パッケージの完成時点で支持基板に密着
されている必要はない。リード先端と支持基板との間は
少なくともリード先端とボンディングワイヤとの間のボ
ンディング時に密着されていればよい。In such a method of assembling a semiconductor package, when the lead is pressed against the support substrate, a change in the shape of the lead is promoted by the contact groove, and the tip of the lead is attached to the support substrate so that the position of the lead tip does not change. Can be in close contact. By bonding the tip of the lead and the bonding wire in this close contact state, electrical and mechanical connection between the tip of the lead and the bonding wire can be reliably performed, and bonding failure can be prevented. . Therefore, in the process of assembling the semiconductor package, the number of defective products can be reduced, so that the yield can be improved. In the method of assembling a semiconductor package according to the second aspect of the present invention, the tips of the leads extending on the support substrate do not necessarily have to be in close contact with the support substrate when the semiconductor package is completed. The lead tip and the support substrate only need to be in close contact at least at the time of bonding between the lead tip and the bonding wire.

【００１４】本発明においては、第１ボンディング（フ
ァーストボンディング）と第２ボンディング（セカンド
ボンディング）とを入れ替えてもよい。どちらを第１ボ
ンディングと呼び、どちらを第２ボンディングと呼ぶか
は単なる呼称の問題にすぎない。In the present invention, the first bonding (first bonding) and the second bonding (second bonding) may be interchanged. Which is referred to as first bonding and which is referred to as second bonding is merely a matter of naming.

【００１５】[0015]

【発明の実施の形態】以下、本発明の実施の形態を図面
を参照し説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１６】（第１の実施の形態）図１は本発明の第１
の実施の形態に係る樹脂封止型半導体パッケージにおい
て、その樹脂封止体の一部を取り除き見やすくした状態
のパッケージの左側一部分を示す平面図、図２（Ａ）は
図１に示すＦ２−Ｆ２切断線部分で切った樹脂封止型半
導体パッケージの要部拡大断面図である。図１及び図２
（Ａ）に示すように、本発明の第１の実施の形態に係る
樹脂封止型半導体パッケージは、半導体チップ４を搭載
する支持基板２と、この支持基板２上にまで延在して配
置された複数本のリード３０１〜３０４と、リード３０
１〜３０４の一部と支持基板２とを少なくともモールド
する樹脂封止体１とを備え、ボンディング領域近傍のリ
ード３０１〜３０４の表面に、このリード３０１〜３０
４をそれぞれ横断する密着用溝をそれぞれ備えている。
半導体チップ４の表面上には、複数個のボンディングパ
ッド４１〜４６が配置されている。なお、図１に示す樹
脂封止型半導体パッケージは、さらに複数本のリード３
１１〜３１６を備えている。図１（及び図２（Ａ））に
は樹脂封止型半導体パッケージの左側の一部分を示し、
パッケージの中央部分より右側の部分は図示省略してい
る。この省略された右側の他の部分は、パッケージの中
央部分を縦断する線に関して、図示された左側の部分の
実質的に線対称となる形状で構成されていることは勿論
である。(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2A is a plan view showing a part of the left side of the package in a state in which a part of the resin-sealed body is removed for easy viewing, and FIG. 2A shows F2-F2 shown in FIG. FIG. 3 is an enlarged cross-sectional view of a main part of the resin-sealed semiconductor package cut along a cutting line portion. 1 and 2
As shown in FIG. 1A, a resin-encapsulated semiconductor package according to a first embodiment of the present invention includes a support substrate 2 on which a semiconductor chip 4 is mounted, and a support substrate 2 extending over the support substrate 2. The plurality of leads 301 to 304
A resin sealing body 1 for molding at least a part of the support substrate 2 and the support substrate 2 is provided.
4 respectively.
A plurality of bonding pads 41 to 46 are arranged on the surface of the semiconductor chip 4. The resin-sealed semiconductor package shown in FIG.
11 to 316 are provided. FIG. 1 (and FIG. 2A) shows a part of the left side of the resin-encapsulated semiconductor package.
The portion on the right side of the central portion of the package is not shown. It is needless to say that the other part of the omitted right side is formed substantially in line symmetry with the left side part shown in FIG.

【００１７】本発明の第１の実施の形態において、支持
基板２には銅(Cu)板、銅(Cu)合金板、鉄(Fe)−ニッケル
(Ni)合金板等の導電性基板が使用されている。このた
め、支持基板２を電源基板として兼用することが出来
る。In the first embodiment of the present invention, a copper (Cu) plate, a copper (Cu) alloy plate, iron (Fe) -nickel
A conductive substrate such as an (Ni) alloy plate is used. Therefore, the support substrate 2 can also be used as a power supply substrate.

【００１８】また、半導体チップ４には、パワーMOSFET
や絶縁ゲート型バイポーラトランジスタ(IGBT)等の電力
用半導体素子（パワーデバイス）及びこのパワーデバイ
スの制御回路や保護回路等が集積化されたパワーＩＣを
搭載することが出来る。ただし、制御回路や保護回路等
は必ずしも、パワーデバイスと同一の半導体チップ４に
モノリシックに集積化されている必要はなく、複数個の
パワーデバイスのみが搭載されたパワーモジュールでも
良い。場合によっては単一のパワーデバイスが搭載され
た半導体チップ４でも良い。半導体チップ４は例えばシ
リコン(Si)や炭化珪素(SiC)等で形成すればよい。図１
に示すように、半導体チップ４の平面形状は方形状で形
成されている。図１中、この半導体チップ４の左辺に沿
った周縁部分には複数のボンディングパッド４１〜４４
が配設され、上辺に沿った周縁部分には複数のボンディ
ングパッド４５が配設され、下辺に沿った周縁部分には
複数のボンディングパッド４６が配設されている。半導
体チップ４は銀（Ag）ペーストや半田などの接着材を利
用し支持基板２の表面に上にマウントされている。The semiconductor chip 4 includes a power MOSFET.
A power IC in which a power semiconductor element (power device) such as a power transistor and an insulated gate bipolar transistor (IGBT) and a control circuit and a protection circuit of the power device are integrated. However, the control circuit, the protection circuit, and the like do not necessarily need to be monolithically integrated on the same semiconductor chip 4 as the power device, and may be a power module in which only a plurality of power devices are mounted. In some cases, the semiconductor chip 4 on which a single power device is mounted may be used. The semiconductor chip 4 may be formed of, for example, silicon (Si) or silicon carbide (SiC). FIG.
As shown in the figure, the planar shape of the semiconductor chip 4 is formed in a square shape. In FIG. 1, a plurality of bonding pads 41 to 44 are provided on a peripheral portion along the left side of the semiconductor chip 4.
Are provided on the peripheral portion along the upper side, and a plurality of bonding pads 46 are disposed on the peripheral portion along the lower side. The semiconductor chip 4 is mounted on the surface of the support substrate 2 using an adhesive such as silver (Ag) paste or solder.

【００１９】図１中、上側に配列されたリード３０１、
３０２、３１１〜３１３のそれぞれの樹脂封止体１内部
に延在するインナー部は半導体チップ４の周縁近傍に配
置され、それぞれのアウター部は樹脂封止体１の外部に
おいて上方向に導出されている。下側に配列されたリー
ド３０３、３０４、３１４〜３１６のそれぞれのインナ
ー部は同様に半導体チップ４の周縁近傍に配置され、そ
れぞれのアウター部は樹脂封止体１の外部において下方
向に導出されている。樹脂封止型半導体パッケージは横
方向に細長い平面形状で形成されており、短辺側に配置
されたリード３０１、３０２、３０３、３０４のそれぞ
れのインナー部はボンディングワイヤ長を短くするため
に支持基板２上に配置され、それぞれのインナー部先端
は半導体チップ４の左辺周縁近傍まで引き延ばされてい
る。第１の実施の形態に係る樹脂封止型半導体パッケー
ジにおいて、リード３０１〜３０４のそれぞれのインナ
ー部は、支持基板２の表面と所定距離だけ離間された状
態で支持基板２の表面とほぼ平行に引き延ばされてい
る。リード３１１〜３１６のそれぞれは支持基板２の上
部には配置されていない。リード３０１〜３０４、３１
１〜３１６はいずれも同一のリードフレームから切り離
されたものであり、このリードフレームは例えばFe-42%
Ni合金板、Fe-50%Ni合金板、Cu板、Cu合金板等の導電性
板材から形成されている。In FIG. 1, the leads 301 arranged on the upper side
The inner portions 302, 311 to 313 extending inside the resin sealing body 1 are arranged in the vicinity of the peripheral edge of the semiconductor chip 4, and the respective outer portions are led out upward outside the resin sealing body 1. I have. The respective inner portions of the leads 303, 304, 314 to 316 arranged on the lower side are similarly arranged near the peripheral edge of the semiconductor chip 4, and the respective outer portions are led out downward outside the resin sealing body 1. ing. The resin-encapsulated semiconductor package is formed in a horizontally-elongated planar shape, and the inner portions of the leads 301, 302, 303, and 304 arranged on the short sides are formed on a supporting substrate to reduce the length of the bonding wire. 2, and the tips of the respective inner portions are extended to the vicinity of the left edge of the semiconductor chip 4. In the resin-sealed semiconductor package according to the first embodiment, each of the inner portions of the leads 301 to 304 is substantially parallel to the surface of the support substrate 2 while being separated from the surface of the support substrate 2 by a predetermined distance. Has been prolonged. Each of the leads 311 to 316 is not arranged above the support substrate 2. Leads 301-304, 31
1 to 316 are all separated from the same lead frame, and this lead frame is, for example, Fe-42%
It is formed from a conductive plate material such as a Ni alloy plate, a Fe-50% Ni alloy plate, a Cu plate, and a Cu alloy plate.

【００２０】そして、支持基板２上にまで延在して配置
されたリード３０１のインナー部には密着用溝３１が配
設されている。同様に支持基板２上にまで延在して配置
されたリード３０２のインナー部には密着用溝３２、支
持基板２上にまで延在して配置されたリード３０３のイ
ンナー部には密着用溝３３、支持基板２上にまで延在し
て配置されたリード３０４のインナー部には密着用溝３
４がそれぞれ配設されている。密着用溝３１〜３４のそ
れぞれは、図１及び図２（Ａ）に符号１２を付して波線
で輪郭形状を示す、組立プロセスにおいて使用されるリ
ード押え治具の当接部近傍において、この当接部分とア
ウター部との間に配設されている。A contact groove 31 is provided in the inner portion of the lead 301 extending to the support substrate 2. Similarly, the inner portion of the lead 302 extended to the support substrate 2 is provided with the contact groove 32, and the inner portion of the lead 303 extended to the support substrate 2 is provided with the contact groove. 33, the inner surface of the lead 304 extended to the support substrate 2
4 are provided respectively. Each of the contact grooves 31 to 34 is denoted by reference numeral 12 in FIGS. 1 and 2 (A) and has a contour shape indicated by a wavy line. It is arranged between the contact part and the outer part.

【００２１】図２（Ｂ）はリード３０１〜３０４のそれ
ぞれの拡大斜視図である。密着用溝３１〜３４は、いず
れもリード３０１〜３０４のそれぞれの支持基板２側の
裏面に、リード幅全域に渡って形成された凹型形状の溝
であり、インナー部先端のボンディング領域（第１の実
施の形態においてはセカンドボンディング領域）裏面を
支持基板２表面に密着させるための溝である。すなわ
ち、密着用溝３１〜３４は、リード３０１〜３０４に外
力を加えると少なくともインナー部先端裏面を確実に支
持基板２の表面に密着させるために、リード３０１〜３
０４の形状変化を容易にする（リードを変形し易くす
る）ことができる。密着用溝３１〜３４の深さt2は、リ
ード３０１〜３０４の機械的強度を充分に確保すること
ができ、かつ搭載されるMOSFET、IGBT等のパワーデバイ
スやパワーＩＣの電流容量を充分に確保することができ
る深さに設計される。さらに、密着用溝３１〜３４の深
さt2は、インナー部先端裏面の支持基板２表面への密着
を容易に行うことができるように設計され、具体的に
は、リード３０１〜３０４の板厚t1の1/3〜1/2の範囲内
の寸法で形成されることが好ましい。例えば、リードフ
レームの材料にFe-42%Ni合金板を使用し、リード３０１
〜３０４の板厚t1を０．２５mmに設定した場合、密着用
溝３１〜３４の深さt2は０．０８３mm〜０．１２５mmの
範囲内で形成すればよい。FIG. 2B is an enlarged perspective view of each of the leads 301-304. Each of the contact grooves 31 to 34 is a concave groove formed over the entire lead width on the back surface of each of the leads 301 to 304 on the side of the support substrate 2, and is a bonding region (first region) at the tip of the inner portion. In the second embodiment, the second bonding region is a groove for bringing the back surface into close contact with the surface of the support substrate 2. That is, the contact grooves 31 to 34 are used to make the leads 301 to 304 in order to ensure that when the external force is applied to the leads 301 to 304, at least the inner rear surface of the inner part is brought into close contact with the surface of the support substrate 2.
04 can be easily changed (leads can be easily deformed). The depth t2 of the contact grooves 31 to 34 can sufficiently secure the mechanical strength of the leads 301 to 304 and sufficiently secure the current capacity of the mounted power devices such as MOSFETs and IGBTs and power ICs. Designed to the depth that can be done. Further, the depth t2 of the contact grooves 31 to 34 is designed so that the back surface of the inner portion tip can be easily adhered to the surface of the support substrate 2, and specifically, the plate thickness of the leads 301 to 304 Preferably, it is formed with a size in the range of 1/3 to 1/2 of t1. For example, an Fe-42% Ni alloy plate is used for the lead frame material, and the lead 301 is used.
In the case where the thickness t1 of No. to No. 304 is set to 0.25 mm, the depth t2 of the contact grooves 31 to 34 may be formed in the range of 0.083 mm to 0.125 mm.

【００２２】リード３０１のインナー部先端と半導体チ
ップ４のボンディングパッド４１との間、リード３０２
のインナー部先端とボンディングパッド４２との間、リ
ード３０３のインナー部先端とボンディングパッド４３
との間、リード３０４のインナー部先端とボンディング
パッド４４との間は、いずれもボンディングワイヤ５を
通して電気的に接続される。同様に、リード３１１〜３
１３のそれぞれのインナー部先端とボンディングパッド
４５との間、リード３１４〜３１６のそれぞれのインナ
ー部先端とボンディングパッド４６との間は、いずれも
ボンディングワイヤ５を通して電気的に接続される。ボ
ンディングワイヤ５には例えば直径３０μｍ乃至７５μ
ｍの金（Au）ワイヤ、銅（Cu）ワイヤ、アルミニウム
（Al）ワイヤ等が実用的に使用できる。Between the tip of the inner portion of the lead 301 and the bonding pad 41 of the semiconductor chip 4, the lead 302
Between the tip of the inner portion of the lead 303 and the bonding pad 42, and between the tip of the inner portion of the lead 303 and the bonding pad 43.
, And between the tip of the inner portion of the lead 304 and the bonding pad 44 are electrically connected through the bonding wire 5. Similarly, leads 311 to 311
13 and the bonding pads 45, and between the leads 314 to 316 and the bonding pads 46, respectively, are electrically connected through the bonding wires 5. For example, the bonding wire 5 has a diameter of 30 μm to 75 μm.
For example, a gold (Au) wire, a copper (Cu) wire, an aluminum (Al) wire, or the like can be practically used.

【００２３】樹脂封止体１は、支持基板２、半導体チッ
プ４、リード３０１〜３０４、３１１〜３１６のそれぞ
れのインナー部及びボンディングワイヤ５を覆うように
形成されている。樹脂封止体１には例えばエポキシ系樹
脂が実用的に使用できる。The resin sealing body 1 is formed so as to cover the support substrate 2, the semiconductor chip 4, the inner parts of the leads 301 to 304, 311 to 316 and the bonding wires 5. For example, an epoxy resin can be practically used for the resin sealing body 1.

【００２４】次に、前述の樹脂封止型半導体パッケージ
の組立方法を説明する。図３（Ａ）、図３（Ｂ）、図４
（Ａ）、図４（Ｂ）はいずれも組立工程毎に示す樹脂封
止型半導体パッケージの組立工程断面図である。なお、
これらの工程断面図は図１に示すＦ２−Ｆ２切断線で切
った断面に相当する図である。Next, a method of assembling the above-described resin-sealed semiconductor package will be described. 3 (A), 3 (B), 4
4A and 4B are cross-sectional views of an assembling process of a resin-sealed semiconductor package shown for each assembling process. In addition,
These process cross-sectional views are views corresponding to cross sections cut along the F2-F2 cutting line shown in FIG.

【００２５】（１）まず、支持基板２を準備し、図３
（Ａ）に示すようにこの支持基板２の表面上に半導体チ
ップ４をマウントするとともに、リード３０１〜３０
４、３１１〜３１６（図１参照）を配置する。これらの
リード３０１〜３０４、３１１〜３１６は図示しない同
一のリードフレームに連結された状態にある。同図３
（Ａ）にはリード３０４だけが示されている。前述のよ
うにリード３０１〜３０４のインナー部は支持基板２上
にまで延在して配置されており、これらのインナー部に
は密着用溝３１〜３４が予め形成されている。リードフ
レームはエッチング加工又は打ち抜き加工で形成される
が、このリードフレームの形成前又は形成後にエッチン
グ加工若しくはダイヤモンドブレードやワイヤーソー等
を用いた機械加工、レーザー加工等により密着用溝３１
〜３４が形成されている。(1) First, the support substrate 2 is prepared, and FIG.
As shown in FIG. 2A, the semiconductor chip 4 is mounted on the surface of the support substrate 2 and the leads 301 to 30 are mounted.
4, 311 to 316 (see FIG. 1). These leads 301 to 304 and 311 to 316 are connected to the same lead frame (not shown). FIG. 3
(A) shows only the lead 304. As described above, the inner portions of the leads 301 to 304 are arranged so as to extend over the support substrate 2, and the grooves 31 to 34 for contact are formed in these inner portions in advance. The lead frame is formed by etching or punching. Before or after the formation of the lead frame, the contact groove 31 is formed by etching, machining using a diamond blade or a wire saw, laser processing, or the like.
To 34 are formed.

【００２６】（２）ワイヤボンディング工程に先立ち、
第２ボンディング（セカンドボンディング）領域となる
リード３０１〜３０４、３１１〜３１６（図１参照）の
それぞれのインナー部をリード押え治具１２により押え
付け、それぞれのインナー部先端の位置が固定される。
支持基板２上にまで延在して配置されないリード３１１
〜３１６のそれぞれのインナー部は、図示しないが表面
及び裏面がリード押え治具１２により挟み込まれるの
で、強固に押え付けられる。これに対して、支持基板２
にまで延在して配置されたリード３０１〜３０４のそれ
ぞれのインナー部は、図３（Ｂ）に示すように、リード
押え治具１２により支持基板２の表面側に押え付けら
れ、折り曲げられる。この結果、少なくともインナー部
先端（セカンドボンディング領域）の裏面と支持基板２
の表面との間が密着される。リード３０１〜３０４のそ
れぞれのインナー部には密着用溝３１〜３４が各々配設
されており、この密着用溝３１〜３４のそれぞれを折れ
曲がり点として、好ましくは弾性変形範囲内で、インナ
ー部が折れ曲がり、インナー部先端の裏面と支持基板２
の表面との間を確実に密着させることができる。この密
着によりリード３０１〜３０４のそれぞれのインナー部
先端の位置が固定される。なお、図３（Ｂ）にはリード
３０４の密着状態が示されるが、他のリード３０１、３
０２、３０３のそれぞれの密着状態も同様である。(2) Prior to the wire bonding step,
The respective inner portions of the leads 301 to 304 and 311 to 316 (see FIG. 1) serving as second bonding (second bonding) regions are pressed by the lead holding jig 12, and the positions of the tips of the respective inner portions are fixed.
Lead 311 not extending to and disposed on support substrate 2
Although not shown, the front and back surfaces of each of the inner portions 316 are sandwiched by the lead holding jig 12, so that the inner portions are strongly pressed. On the other hand, the supporting substrate 2
As shown in FIG. 3B, the inner portions of the leads 301 to 304 arranged so as to extend downward are pressed against the front side of the support substrate 2 by the lead holding jig 12 and bent. As a result, at least the back surface of the tip of the inner portion (second bonding region) and the supporting substrate 2
The surface is closely adhered. Adhesion grooves 31 to 34 are respectively provided in the inner portions of the leads 301 to 304, and each of the adhesion grooves 31 to 34 is used as a bending point. Bent, back surface of inner end tip and support substrate 2
Can be surely brought into close contact with the surface. By this close contact, the positions of the tips of the inner portions of the leads 301 to 304 are fixed. Note that FIG. 3B shows a state in which the leads 304 are in close contact with each other.
The same applies to the close contact states of 02 and 303.

【００２７】（３）引き続き、ワイヤボンディング工程
を行う。まずワイヤボンディング装置（ワイヤボンダ）
のキャピラリィ１０の先端からボンディングワイヤ５を
送り出し、ボンディングワイヤ５の先端部分にボールを
形成する。ボールは、ボンディングワイヤ５の先端部分
に電気スパークを発生させることにより、またボンディ
ングワイヤ５の先端部分を加熱溶融させることにより容
易に形成することができる。図４（Ａ）に示すように、
このボールを半導体チップ４のボンディングパッド（フ
ァーストボンディング領域）４４の表面に押し付け、ボ
ンディングワイヤ５の第１ボンディング（ファーストボ
ンディング）を行う。ボールは、キャピラリィ１０の先
端で押し潰されることにより、ボール形状から釘頭形状
に変形されている。この第１ボンディング（ファースト
ボンディング）においては、半導体チップ４が加熱され
た状態で、熱圧着される。若しくは、半導体チップ４が
加熱された状態で、さらに、キャピラリィ１０にボンデ
ィングパッド４４の表面と平行な方向の超音波振動が加
えられ、ボンディングワイヤ５の先端のボールと半導体
チップ４のボンディングパッド４４とが電気的に接続さ
れる。(3) Subsequently, a wire bonding step is performed. First, wire bonding equipment (wire bonder)
The bonding wire 5 is sent out from the tip of the capillary 10 and a ball is formed at the tip of the bonding wire 5. The ball can be easily formed by generating an electric spark at the tip of the bonding wire 5 or by heating and melting the tip of the bonding wire 5. As shown in FIG.
The ball is pressed against the surface of the bonding pad (first bonding area) 44 of the semiconductor chip 4 to perform the first bonding (first bonding) of the bonding wire 5. The ball is deformed from a ball shape to a nail head shape by being crushed by the tip of the capillary 10. In the first bonding (first bonding), the semiconductor chip 4 is thermocompression bonded while being heated. Alternatively, while the semiconductor chip 4 is heated, an ultrasonic vibration is further applied to the capillary 10 in a direction parallel to the surface of the bonding pad 44, and the ball at the tip of the bonding wire 5 and the bonding pad 44 of the semiconductor chip 4 Are electrically connected.

【００２８】（４）ファーストボンディングが終了する
と、キャピラリィ１０は、ボンディングワイヤ５を送り
出しながら上方に移動し、さらにリード３０４のインナ
ー部先端（セカンドボンディング領域）の表面上まで移
動し、そしてインナー部先端の表面にボンディングワイ
ヤ５の他端側を押し付け、図４（Ｂ）に示すように第２
ボンディング（セカンドボンディング）を行う。この第
２ボンディング（セカンドボンディング）においては、
リードフレームが加熱された状態で、熱圧着されるか、
若しくは、半導体チップ４が加熱された状態で、さら
に、キャピラリィ１０にインナー部先端の表面と平行な
方向の超音波振動が加えられる。セカンドボンディング
においては、インナー部先端は密着用溝３４により支持
基板２の表面に密着されており、支持基板２がボンディ
ングの際のインナー部先端の台座として働くので、イン
ナー部先端の表面にキャピラリィ１０によりボンディン
グワイヤ５を強く押し付けることができる。さらに、セ
カンドボンディングにおいては、インナー部先端が密着
用溝３４により支持基板２の表面に密着された状態でリ
ード押え治具１２によりインナー部先端が押え付けられ
ているので、キャピラリィ１０に超音波振動が加えられ
てもインナー部先端の位置ずれがなく、超音波振動のパ
ワーが十分に印加出来る。このため、超音波パワーによ
り、インナー部先端の表面にボンディングワイヤ５を強
く擦り付けることができる。従って、インナー部先端の
表面とボンディングワイヤ５との間の接合を確実に行う
ことができるので、ボンディング不良、特にセカンドボ
ンディング不良を防止することができる。(4) When the first bonding is completed, the capillary 10 moves upward while sending out the bonding wire 5, moves further up to the surface of the inner portion tip (second bonding area) of the lead 304, and then moves to the inner portion tip. The other end of the bonding wire 5 is pressed against the surface of the second wire, and as shown in FIG.
Perform bonding (second bonding). In this second bonding (second bonding),
With the lead frame heated, thermocompression bonding or
Alternatively, while the semiconductor chip 4 is heated, ultrasonic vibration is further applied to the capillary 10 in a direction parallel to the surface of the tip of the inner portion. In the second bonding, the tip of the inner portion is in close contact with the surface of the support substrate 2 by the contact groove 34, and the support substrate 2 acts as a pedestal at the tip of the inner portion during bonding. Thereby, the bonding wire 5 can be pressed strongly. Further, in the second bonding, since the tip of the inner portion is pressed by the lead holding jig 12 in a state where the tip of the inner portion is in close contact with the surface of the support substrate 2 by the contact groove 34, the ultrasonic vibration is applied to the capillary 10. Is applied, there is no displacement of the tip of the inner part, and the power of ultrasonic vibration can be sufficiently applied. Therefore, the bonding wire 5 can be strongly rubbed against the surface of the tip of the inner portion by the ultrasonic power. Therefore, the bonding between the surface of the inner portion tip and the bonding wire 5 can be reliably performed, so that a bonding defect, particularly a second bonding defect, can be prevented.

【００２９】（５）セカンドボンディングが終了する
と、キュピラリィ１０を上昇させ、セカンドボンディン
グにより発生した肉薄部分でボンディングワイヤ５を切
断することにより、半導体チップ４のボンディングパッ
ド４４とリード３０４との間がボンディングワイヤ５に
より電気的に接続されている。同様に、図１に示すリー
ド３０１のインナー部とボンディングパッド４１との
間、リード３０２のインナー部とボンディングパッド４
２との間、リード３０３のインナー部とボンディングパ
ッド４３との間のそれぞれをワイヤボンディングにより
電気的に接続する。さらに同様に、リード３１１〜３１
３のそれぞれのインナー部とボンディングパッド４５と
の間、リード３１４〜３１６のそれぞれのインナー部と
ボンディングパッド４６との間をワイヤボンディングに
より電気的に接続する。すべてのワイヤボンディングが
終了した後にリード押え治具１２によるリード３０１〜
３０４、３１１〜３１６の押え付けを解除する。この押
え付けの解除により、リード３０１〜３０４、３１１〜
３１６のそれぞれのインナー部は、復元力により元の位
置に復帰し、支持基板２の表面から所定間隔だけ離間さ
れる。(5) When the second bonding is completed, the capillary 10 is raised, and the bonding wire 5 is cut at the thin portion generated by the second bonding, so that the bonding between the bonding pad 44 of the semiconductor chip 4 and the lead 304 is performed. They are electrically connected by wires 5. Similarly, between the inner part of the lead 301 and the bonding pad 41 shown in FIG.
2 and between the inner portion of the lead 303 and the bonding pad 43 are electrically connected by wire bonding. Similarly, leads 311-31
3 and the bonding pads 45, and between the inner portions of the leads 314 to 316 and the bonding pads 46 by wire bonding. After all the wire bonding is completed, the leads 301 to 301 by the lead holding jig 12
The pressing of 304, 311 to 316 is released. By releasing the pressing, the leads 301 to 304, 311-
Each of the inner portions 316 returns to the original position by the restoring force, and is separated from the surface of the support substrate 2 by a predetermined interval.

【００３０】（６）トランスファーモールド法により支
持基板２、半導体チップ４、リード３０１〜３０４、３
１１〜３１６のそれぞれのインナー部及びボンディング
ワイヤ５を覆う樹脂封止体１を形成する。引き続き、リ
ード３０１〜３０４、３１１〜３１６のそれぞれのアウ
ター部をリードフレームから切り離し、必要に応じてこ
のアウター部に所定のリード成形を行うことにより、前
述の図１及び図２（Ａ）に示す樹脂封止型半導体パッケ
ージが完成する。(6) The support substrate 2, the semiconductor chip 4, the leads 301 to 304, 3
The resin sealing body 1 covering the inner portions 11 to 316 and the bonding wires 5 is formed. Subsequently, the respective outer portions of the leads 301 to 304 and 311 to 316 are cut off from the lead frame, and a predetermined lead is formed on the outer portions as necessary, as shown in FIGS. 1 and 2A described above. A resin-sealed semiconductor package is completed.

【００３１】このように構成される樹脂封止型半導体パ
ッケージにおいては、密着用溝３１〜３４のそれぞれで
支持基板２上にリード３０１〜３０４のそれぞれのイン
ナー部先端を密着させ位置の変動がない状態でインナー
部先端とボンディングワイヤ５との間をボンディングす
ることができるので、インナー部先端とボンディングワ
イヤ５との間を電気的かつ機械的に確実に接続すること
ができる。従って、ボンディング不良を防止することが
できるので、樹脂封止型半導体パッケージの電気的信頼
性を向上させることができる。In the resin-encapsulated semiconductor package having such a configuration, the tips of the inner portions of the leads 301 to 304 are brought into close contact with the support substrate 2 at the respective contact grooves 31 to 34 so that the position does not change. Since the bonding between the tip of the inner portion and the bonding wire 5 can be performed in this state, the connection between the tip of the inner portion and the bonding wire 5 can be reliably electrically and mechanically connected. Therefore, bonding failure can be prevented, and the electrical reliability of the resin-encapsulated semiconductor package can be improved.

【００３２】さらに、このような樹脂封止型半導体パッ
ケージの組立方法においては、３０１〜３０４のそれぞ
れのインナー部を支持基板２側に押し付けると、密着用
溝３１〜３４のそれぞれによりインナー部の形状変化を
助長し、インナー部先端の位置が変動しないようにイン
ナー部先端を支持基板２に密着させることができる。こ
の密着状態でインナー部先端とボンディングワイヤ５と
の間をボンディングすることにより、インナー部先端と
ボンディングワイヤ５との間の電気的かつ機械的な接続
を確実に行うことができ、ボンディング不良を防止する
ことができる。従って、樹脂封止型半導体パッケージの
組立プロセスにおいて、不良品の発生を減少させること
ができるので、歩留まりを向上させることができる。Further, in such a method of assembling a resin-sealed semiconductor package, when the respective inner portions 301 to 304 are pressed against the support substrate 2 side, the shape of the inner portions is formed by the respective contact grooves 31 to 34. The change can be promoted, and the tip of the inner portion can be brought into close contact with the support substrate 2 so that the position of the tip of the inner portion does not change. By bonding the tip of the inner portion and the bonding wire 5 in this tight contact state, electrical and mechanical connection between the tip of the inner portion and the bonding wire 5 can be reliably performed, and bonding failure is prevented. can do. Therefore, in the process of assembling the resin-sealed semiconductor package, the occurrence of defective products can be reduced, and the yield can be improved.

【００３３】なお、第１の実施の形態に係る樹脂封止型
半導体パッケージにおいては、半導体チップ４のボンデ
ィングパッド４１〜４６のそれぞれをファーストボンデ
ィング領域、リード３０１〜３０４、３１１〜３１６の
それぞれのインナー部先端をセカンドボンディング領域
としたが、本発明においては、ファーストボンディング
領域とセカンドボンディング領域とを入れ替えてもよ
い。In the resin-encapsulated semiconductor package according to the first embodiment, each of the bonding pads 41 to 46 of the semiconductor chip 4 is connected to the first bonding area, and each of the leads 301 to 304 and 311 to 316 is connected to the inner. Although the second bonding region is formed at the tip of the portion, the first bonding region and the second bonding region may be exchanged in the present invention.

【００３４】（その他の実施の形態）上記のように、本
発明は第１の実施の形態によって記載したが、この開示
の一部をなす論述及び図面は本発明を限定するものであ
ると理解すべきではない。この開示から当業者には様々
な代替実施の形態、実施例及び運用技術が明らかとなろ
う。(Other Embodiments) As described above, the present invention has been described with reference to the first embodiment. However, it should be understood that the description and drawings constituting a part of this disclosure limit the present invention. should not do. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

【００３５】例えば、上記第１の実施の形態に係る樹脂
封止型半導体パッケージの密着用溝は種々の形状が採用
可能である。図５（Ａ）、図５（Ｂ）は、本発明の他の
実施の形態（第２の実施の形態）に係る樹脂封止型半導
体パッケージの要部拡大断面図である。図５（Ａ）に示
す樹脂封止型半導体パッケージにおいては、リード３０
１〜３０４（図１参照。同図５（Ａ）にはリード３０４
だけを示す。）のそれぞれのインナー部にＶ型形状の密
着用溝３５が配設されている。図５（Ｂ）に示す樹脂封
止型半導体パッケージにおいては、リード３０１〜３０
４（同様に図１参照。同図５（Ｂ）にはリード３０４だ
けを示す。）のそれぞれのインナー部には、底部角部が
丸みを帯びたＵ型形状の密着用溝３６が配設されてい
る。更に、図示を省略するがＷ字形状や逆メサ形状等で
もかまわない。このように構成される種々の形状の密着
用溝の場合であっても、第１の実施の形態に係る樹脂封
止型半導体パッケージで得られる効果と同様の効果を得
ることができる。For example, various shapes can be adopted for the contact groove of the resin-sealed semiconductor package according to the first embodiment. FIGS. 5A and 5B are enlarged cross-sectional views of a main part of a resin-sealed semiconductor package according to another embodiment (second embodiment) of the present invention. In the resin-sealed semiconductor package shown in FIG.
1 to 304 (see FIG. 1, and FIG.
Just show. A V-shaped contact groove 35 is provided in each of the inner portions. In the resin-sealed semiconductor package shown in FIG.
4 (similarly to FIG. 1; only the lead 304 is shown in FIG. 5B), a U-shaped contact groove 36 having a rounded bottom corner is provided in each inner portion. Have been. Further, although not shown, a W-shape or an inverted mesa shape may be used. Even in the case of the contact grooves having various shapes configured as described above, the same effects as those obtained by the resin-sealed semiconductor package according to the first embodiment can be obtained.

【００３６】このように、本発明はここでは記載してい
ない様々な実施の形態等を含むことは勿論である。した
がって、本発明の技術的範囲は上記の説明から妥当な特
許請求の範囲に係る発明特定事項によってのみ定められ
るものである。As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

【００３７】[0037]

【発明の効果】本発明は、支持基板上に重複配置された
リード先端とボンディングワイヤとの間のボンディング
不良を防止することができ、電気的信頼性を向上させる
ことができる半導体パッケージを提供することができ
る。According to the present invention, there is provided a semiconductor package capable of preventing a bonding failure between a tip end of a lead and a bonding wire overlappingly arranged on a support substrate and improving electrical reliability. be able to.

【００３８】さらに、本発明は、ボンディング不良に伴
う製品不良の発生を減少させることができ、歩留まりを
向上させることができる半導体パッケージの組立方法を
提供することができる。Further, the present invention can provide a method of assembling a semiconductor package capable of reducing the occurrence of product failures due to bonding failures and improving the yield.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態に係る樹脂封止型半
導体パッケージの一部分を示す平面図である。FIG. 1 is a plan view showing a part of a resin-sealed semiconductor package according to a first embodiment of the present invention.

【図２】（Ａ）は本発明の第１の実施の形態に係る樹脂
封止型半導体パッケージの要部拡大断面図、（Ｂ）は本
発明の第１の実施の形態に係る樹脂封止型半導体パッケ
ージのリードの拡大斜視図である。FIG. 2A is an enlarged cross-sectional view of a main part of a resin-sealed semiconductor package according to a first embodiment of the present invention, and FIG. 2B is a resin seal according to the first embodiment of the present invention; FIG. 3 is an enlarged perspective view of a lead of the semiconductor package.

【図３】本発明の第１の実施の形態に係る組立工程毎に
示す樹脂封止型半導体パッケージの組立工程断面図であ
る（その１）。FIG. 3 is a sectional view of an assembling process of the resin-sealed semiconductor package shown for each assembling process according to the first embodiment of the present invention (part 1).

【図４】本発明の第１の実施の形態に係る組立工程毎に
示す樹脂封止型半導体パッケージの組立工程断面図であ
る（その２）。FIG. 4 is a sectional view of an assembling process of the resin-sealed semiconductor package shown for each assembling process according to the first embodiment of the present invention (part 2).

【図５】本発明の他の実施の形態（第２の実施の形態）
に係る樹脂封止型半導体パッケージの要部拡大断面図で
ある。FIG. 5 is another embodiment of the present invention (second embodiment).
FIG. 2 is an enlarged sectional view of a main part of the resin-sealed semiconductor package according to FIG.

【図６】従来技術に係る樹脂封止型半導体パッケージの
平面図である。FIG. 6 is a plan view of a resin-sealed semiconductor package according to the related art.

【符号の説明】[Explanation of symbols]

１ 樹脂封止体 ２ 支持基板 ３１〜３４，３５，３６ 密着用溝 ３０１〜３０４，３１１〜３１６ 支持基板 ４ 半導体チップ ４１〜４６ ボンディングパッド ５ ボンディングワイヤ １０ キャピラリィ １２ リード押え治具 DESCRIPTION OF SYMBOLS 1 Resin sealing body 2 Support substrate 31-34, 35, 36 Adhesion groove 301-304, 311-316 Support substrate 4 Semiconductor chip 41-46 Bonding pad 5 Bonding wire 10 Capillary 12 Lead holding jig

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップを搭載する支持基板と、 前記支持基板上にまで延在して配置されたリードと、 前記リードの一部と前記支持基板とを少なくともモール
ドする樹脂封止体とを備え、 ボンディング領域近傍の、前記リードの表面に前記リー
ドを横断する密着用溝を備えたことを特徴とする半導体
パッケージ。1. A support substrate on which a semiconductor chip is mounted, a lead extending over the support substrate, and a resin sealing body for molding at least a part of the lead and the support substrate. A semiconductor package, comprising: a contact groove in the vicinity of a bonding region on the surface of the lead that traverses the lead. 【請求項２】 支持基板上に半導体チップをマウント
し、密着用溝を備えたリードを前記支持基板上に配置す
る工程と、 前記リードの前記密着用溝よりも先端部の所定の領域を
前記支持基板側に押し付け前記リードを折り曲げ、該所
定の領域を前記支持基板に密着させる工程と、 前記半導体チップのボンディングパッドにボンディング
ワイヤの一端を第１ボンディングする工程と、 前記所定の領域に対して前記ボンディングワイヤの他端
を第２ボンディングする工程とを少なくとも有すること
を特徴とする半導体パッケージの組立方法。2. A step of mounting a semiconductor chip on a support substrate and arranging a lead provided with a contact groove on the support substrate; Pressing the lead against the support substrate, bending the lead to bring the predetermined region into close contact with the support substrate, and first bonding one end of a bonding wire to a bonding pad of the semiconductor chip; Performing a second bonding of the other end of the bonding wire.
JP11001325A 1999-01-06 1999-01-06 Semiconductor package and assembling method thereof Pending JP2000200867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11001325A JP2000200867A (en) 1999-01-06 1999-01-06 Semiconductor package and assembling method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11001325A JP2000200867A (en) 1999-01-06 1999-01-06 Semiconductor package and assembling method thereof

Publications (1)

Publication Number Publication Date
JP2000200867A true JP2000200867A (en) 2000-07-18

Family

ID=11498356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11001325A Pending JP2000200867A (en) 1999-01-06 1999-01-06 Semiconductor package and assembling method thereof

Country Status (1)

Country Link
JP (1) JP2000200867A (en)

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