JP2001284370A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2001284370A
JP2001284370A JP2000094071A JP2000094071A JP2001284370A JP 2001284370 A JP2001284370 A JP 2001284370A JP 2000094071 A JP2000094071 A JP 2000094071A JP 2000094071 A JP2000094071 A JP 2000094071A JP 2001284370 A JP2001284370 A JP 2001284370A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead
bonding
bonded
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000094071A
Other languages
Japanese (ja)
Inventor
Masakazu Watanabe
昌和 渡辺
Shigeo Kimura
茂夫 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2000094071A priority Critical patent/JP2001284370A/en
Publication of JP2001284370A publication Critical patent/JP2001284370A/en
Pending legal-status Critical Current

Links

Classifications

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of further miniaturization by bonding a bonding wire first to the side of a lead part. SOLUTION: A common board 21, which has many mountings 26, is prepared. Each mounting part 26 has an island 22 and a lead 23. A semiconductor chip 30 is die-bonded to the island 22, and a buffer 32 is made on an electrode pad 31, as need. It is first bonded to the side of the lead 23 is second bonded to the side of the lead 23, and is second bonded to the side of the electrode pad 31, thus performing wire bonding. These are covered with a common resin layer 36. The resin layer 36 and the common board 21 are divided separately for each mount 26, so as to obtain individual semiconductor devices.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、軽薄短小化、特に
小型化に対応して装置の薄形化を実現できる、半導体装
置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device capable of realizing a thinner device corresponding to a reduction in size and size, particularly, a reduction in size.

【０００２】[0002]

【従来の技術】従来の半導体装置の組み立て工程に於い
ては、半導体ウェハをダイシングする事によって得られ
た半導体チップを、リードフレームにダイボンド・ワイ
ヤボンドし、金型と樹脂注入によるトランスファーモー
ルドによって半導体チップを封止し、リードフレームを
切断して個々の半導体装置毎に分離するという工程が行
われている。この製造方法によって得られる半導体装置
は、リードフレームの加工精度の限界、リードフレーム
と金型との位置合わせ精度の限界などにより、パッケー
ジサイズには自ずと限界があった。2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor chip obtained by dicing a semiconductor wafer is die-bonded and wire-bonded to a lead frame, and the semiconductor is formed by transfer molding using a mold and resin injection. A process of sealing a chip, cutting a lead frame and separating each semiconductor device is performed. The semiconductor device obtained by this manufacturing method naturally has a limit in the package size due to the limit of the processing accuracy of the lead frame, the limit of the alignment accuracy of the lead frame and the die, and the like.

【０００３】近年、例えば特開平９−６４０４９号等に
開示されているように、ウェハスケールＣＳＰ（チップ
・サイズ・パッケージ）が注目され始めている。この技
術は、半導体ウェハを分割せずに樹脂封止し、樹脂と半
導体ウェハとを半導体チップ毎にダイシングする事によ
り、半導体チップと同一寸法の半導体装置を形成するも
のである。外部接続電極は樹脂表面に部分的に露出させ
た導電層で構成する。[0003] In recent years, as disclosed in, for example, Japanese Patent Application Laid-Open No. 9-64049, a wafer scale CSP (chip size package) has been receiving attention. According to this technique, a semiconductor device having the same dimensions as a semiconductor chip is formed by sealing a semiconductor wafer with a resin without dividing the semiconductor wafer and dicing the resin and the semiconductor wafer for each semiconductor chip. The external connection electrode is formed of a conductive layer partially exposed on the resin surface.

【０００４】しかしながら、チップサイズが１０数ｍｍ
にも及ぶＬＳＩチップであればその寸法内に多数個の電
極を配置することが可能であるものの、例えばチップサ
イズが１ｍｍにも満たないような、しかも半導体チップ
裏面側を１つの電極として用いるようなチップでは、ウ
ェハスケールＣＳＰ技術を適用するには無理がある。However, the chip size is more than 10 mm
Although it is possible to arrange a large number of electrodes within the size of an LSI chip having a size of as large as possible, for example, the chip size is less than 1 mm, and the back surface of the semiconductor chip is used as one electrode. It is impossible to apply the wafer scale CSP technology to a simple chip.

【０００５】そこで、斯様なトランジスタチップは、図
５に示すような手法で実装することが考案されている。Therefore, it has been devised that such a transistor chip is mounted by a method as shown in FIG.

【０００６】すなわち、図５（Ａ）に示すように、先ず
は絶縁性の共通基板１１を準備する。共通基板１１の表
面には、半導体装置に対応する多数の搭載部が形成され
ており、各搭載部にはアイランド部１２とリード部１３
とが設けられている。アイランド部１２の各々に半導体
チップ１４をダイボンドし、半導体チップ１４の電極パ
ッドとリード部１３とをボンディングワイヤ１５でワイ
ヤボンドする。That is, as shown in FIG. 5A, first, an insulating common substrate 11 is prepared. A large number of mounting portions corresponding to the semiconductor device are formed on the surface of the common substrate 11, and each mounting portion has an island portion 12 and a lead portion 13.
Are provided. The semiconductor chip 14 is die-bonded to each of the island portions 12, and the electrode pads of the semiconductor chip 14 and the lead portions 13 are wire-bonded with the bonding wires 15.

【０００７】次いで図５（Ｂ）に示すように、共通基板
１１の上部に樹脂層１６を形成し、各半導体チップ１４
を一括封止し、そして図５（Ｃ）に示すように各搭載部
毎に樹脂層１６と共通基板１１とをダイシングブレード
１７で切断することにより、図５（Ｄ）に示したよう
な、半導体装置を形成する。外部接続用の電極１８は共
通基板１１の裏面側に形成され、各々は共通基板１１を
貫通するスルーホール１９を介してアイランド部１２と
リード部１３とに接続される。Next, as shown in FIG. 5B, a resin layer 16 is formed on the common substrate 11 and each semiconductor chip 14 is formed.
5C, and the resin layer 16 and the common substrate 11 are cut by a dicing blade 17 for each mounting portion as shown in FIG. A semiconductor device is formed. The electrodes 18 for external connection are formed on the back surface side of the common substrate 11, and each is connected to the island portion 12 and the lead portion 13 through a through hole 19 penetrating the common substrate 11.

【０００８】この手法によれば、例えば縦×横の寸法が
１．０ｍｍ×０．６ｍｍの様な、極めて小さい寸法の半
導体装置を安価に製造することができる。According to this method, it is possible to manufacture a semiconductor device having an extremely small size, for example, 1.0 mm × 0.6 mm in length and width, at a low cost.

【０００９】[0009]

【発明が解決しようとする課題】しかしながら、共通基
板１１と半導体チップ１４とは共に、一定の機械的強度
を保たせるために例えば０．２５ｍｍ〜０．３５ｍｍ程
度の板厚が必要である。更に、電極パッド側をファース
トボンド、リード部１３側をセカンドボンドとするボン
ディングワイヤ１５には、ワイヤと半導体チップとの接
触を避けるため、１５０μ程度のループ高さＨ１（図５
Ｄ参照）が必要である。加えて、ボンディングワイヤ１
５が露出しないように、樹脂層１６にも一定の膜厚が必
要とされる。However, both the common substrate 11 and the semiconductor chip 14 need to have a thickness of, for example, about 0.25 mm to 0.35 mm in order to maintain a certain mechanical strength. Further, the bonding wire 15 having a first bond on the electrode pad side and a second bond on the lead portion 13 side has a loop height H1 of about 150 μm (FIG. 5) in order to avoid contact between the wire and the semiconductor chip.
D) is required. In addition, bonding wire 1
The resin layer 16 also needs to have a constant thickness so that the layer 5 is not exposed.

【００１０】これらのことから、縦×横の寸法は上記手
法によって小型化が可能であるものの、装置の高さＨ２
（図５Ｄ参照）は０．５ｍｍ程度が限界であって、薄形
化が困難である欠点があった。縦横の寸法に対して高さ
Ｈ２が大きいと、半導体装置を実装する際に取扱が困難
となり、且つ電子機器の薄形化に対応できない欠点があ
る。From these facts, the vertical and horizontal dimensions can be reduced by the above method, but the height H2
(See FIG. 5D) has a drawback that the limit is about 0.5 mm and it is difficult to reduce the thickness. If the height H2 is larger than the vertical and horizontal dimensions, it is difficult to handle the semiconductor device when mounting it, and there is a drawback that the electronic device cannot be made thinner.

【００１１】[0011]

【課題を解決するための手段】本発明は、上述した各事
情に鑑みて成されたものであり、半導体チップを搭載す
るアイランド部と、前記半導体チップの電極と接続され
るリード部とを有する搭載部を、多数個配列した共通の
基板を準備する工程と、前記搭載部の各々に半導体チッ
プを固着する工程と、前記半導体チップの電極パッドと
前記リード部とを、前記リード部側にファーストボンド
し、前記電極パッド側にセカンドボンドしたボンディン
グワイヤで接続する工程と、前記多数の搭載部を共通の
樹脂層で被覆する工程と、前記搭載部毎に前記樹脂層と
前記共通基板とを分離して、個々の半導体装置を形成す
る工程と、を具備することにより、薄形化が可能な半導
体装置の製造方法を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has an island portion for mounting a semiconductor chip and a lead portion connected to an electrode of the semiconductor chip. A step of preparing a common substrate in which a plurality of mounting sections are arranged; a step of fixing a semiconductor chip to each of the mounting sections; and a step of firstly positioning the electrode pads of the semiconductor chip and the lead sections on the lead section side. Bonding, connecting to the electrode pad side with a second-bonded bonding wire, covering the plurality of mounting portions with a common resin layer, and separating the resin layer and the common substrate for each mounting portion. And a step of forming individual semiconductor devices, thereby providing a method of manufacturing a semiconductor device that can be reduced in thickness.

【００１２】[0012]

【発明の実施の形態】図１、図２は、本発明の一実施の
形態を説明するための図である。1 and 2 are diagrams for explaining an embodiment of the present invention.

【００１３】第１工程：図１（Ａ）参照 先ず、例えばセラミック製などの絶縁素材からなる共通
基板２１を準備する。共通基板２１は例えば縦×横が１
００ｍｍ×５０ｍｍの大きさと０．３ｍｍ程度の板厚を
持ち、共通基板２１の表面には例えば１００個の搭載部
が一定間隔で縦横に配列されている。その搭載部の各々
には、銅箔等の金属めっき層によってアイランド部２２
とリード部２３とが所望の形状のパターンに形成されて
いる。共通基板２１の裏面側には同じく銅箔などの金属
メッキ層によって外部接続電極２４が形成されている。
アイランド部２２及び外部接続電極２４とは、共通基板
２１を貫通するビアホール２５によって電気的に接続さ
れている。First Step: See FIG. 1A First, a common substrate 21 made of an insulating material such as ceramic is prepared. The common substrate 21 is, for example, 1 × length × width.
It has a size of 00 mm × 50 mm and a plate thickness of about 0.3 mm. On the surface of the common substrate 21, for example, 100 mounting portions are arranged vertically and horizontally at regular intervals. Each of the mounting portions is provided with an island portion 22 by a metal plating layer such as a copper foil.
And the lead portion 23 are formed in a pattern having a desired shape. External connection electrodes 24 are also formed on the back side of the common substrate 21 by a metal plating layer such as a copper foil.
The island portion 22 and the external connection electrode 24 are electrically connected by a via hole 25 penetrating the common substrate 21.

【００１４】共通基板２１の各搭載部２６と外部接続電
極２４のパターン形状を図３（Ａ）の上面図と図３
（Ｂ）の裏面図に示す。各搭載部のアイランド部２２と
リード部２３は、同一形状、同一寸法で縦横に一定間隔
で配列されており、各アイランド部２２とリード部２３
は例えば０．０７ｍｍの線幅で延在する接続部２７を介
して、隣の搭載部２６のアイランド部２２又はリード部
２３に接続されている。接続部２７はまた、搭載部２６
を配列した領域の周囲を囲むように形成した共通接続部
２８に接続され、全ての搭載部２６のアイランド部２２
とリード部２３とが電気的に共通接続されている。各搭
載部２６と各搭載部２６との間には、ダイシングに必要
となる、２０〜５０μｍの間隔が設けられる。FIG. 3A is a plan view showing the pattern shapes of each mounting portion 26 of the common substrate 21 and the external connection electrodes 24. FIG.
This is shown in the back view of FIG. The island portion 22 and the lead portion 23 of each mounting portion have the same shape and the same dimensions and are arranged vertically and horizontally at regular intervals.
Is connected to the island portion 22 or the lead portion 23 of the adjacent mounting portion 26 via a connecting portion 27 extending with a line width of, for example, 0.07 mm. The connection part 27 is also provided with the mounting part 26.
Are connected to a common connecting portion 28 formed so as to surround the periphery of the region where the
And the lead portion 23 are electrically connected in common. An interval of 20 to 50 μm, which is necessary for dicing, is provided between each mounting section 26.

【００１５】図３（Ｂ）を参照して、共通基板２１の裏
面側には、外部接続電極２４ａ、２４ｂ、２４ｃが形成
される。アイランド部２２に対して外部接続電極２４ａ
が対応し、各リード部２３に対して各外部接続電極２４
ｂ、２４ｃが対応する。対応する各電極部は、共通基板
２１を貫通しタングステン、Ａｇ等の導電材料で埋設さ
れた直径０．１５ｍｍ程度のビアホール２５によって電
気的に接続されている。Referring to FIG. 3B, external connection electrodes 24a, 24b and 24c are formed on the back surface of common substrate 21. External connection electrode 24a for island portion 22
Correspond to each external connection electrode 24 for each lead portion 23.
b and 24c correspond. The corresponding electrode portions are electrically connected to each other by a via hole 25 having a diameter of about 0.15 mm penetrating the common substrate 21 and buried with a conductive material such as tungsten or Ag.

【００１６】第２工程：図１（Ｂ）参照 上記の共通基板２１を準備した後、各搭載部２６のアイ
ランド部２２に、半導体チップ３０をＡｇペースト等の
導電材料でダイボンドする。半導体チップ３０が３端子
のトランジスタ素子である場合、外部接続電極２４ａが
コレクタ、外部接続電極２４ｂ、２４ｃがベースとエミ
ッタに対応し、半導体チップ３０がパワーＭＯＳＦＥＴ
素子である場合は、外部接続電極２４ａがドレイン、外
部接続電極２４ｂ、２４ｃがゲートとソースに対応す
る。Second Step: See FIG. 1B After the above-mentioned common substrate 21 is prepared, the semiconductor chip 30 is die-bonded to the island portion 22 of each mounting portion 26 with a conductive material such as Ag paste. When the semiconductor chip 30 is a three-terminal transistor element, the external connection electrode 24a corresponds to a collector, the external connection electrodes 24b and 24c correspond to a base and an emitter, and the semiconductor chip 30 is a power MOSFET.
In the case of an element, the external connection electrode 24a corresponds to a drain, and the external connection electrodes 24b and 24c correspond to a gate and a source.

【００１７】第３工程：図１（Ｃ）参照 ダイボンドした半導体チップ３０に対してワイヤボンド
するのであるが、必要である場合には、半導体チップ３
０の電極パッド３１に緩衝剤をあらかじめ形成する。緩
衝剤は、例えばワイヤのボールだけを残すことで形成す
る。即ち、先端にボール部３２を形成したボンディング
ワイヤを電極パッド３１上にファーストボンドし、キャ
ピラリ３３を上昇した後、再度下降させ、キャピラリ３
３の先端部でワイヤを切断することで、電極パッド３１
上にボール部３２だけを残したものである。このボール
部３２は、ボンディングワイヤの金材料からなるもので
あるので、緩衝剤として好適である。尚、本例に限られ
ることなく、アルミ、鉄、銅などの金属片を電極パッド
２１上に接着するような形態でも良い。Third step: Refer to FIG. 1C. Wire bonding is performed on the semiconductor chip 30 which has been die-bonded.
A buffer is formed in advance on the zero electrode pad 31. The buffer is formed, for example, by leaving only the ball of wire. That is, the bonding wire having the ball portion 32 formed at the tip is first bonded onto the electrode pad 31, and the capillary 33 is raised and then lowered again, and the capillary 3 is lowered.
3 by cutting the wire at the tip of the electrode pad 31.
Only the ball portion 32 is left above. Since the ball portion 32 is made of a gold material for a bonding wire, it is suitable as a buffer. The present invention is not limited to this example, and a form in which a metal piece such as aluminum, iron, or copper is bonded onto the electrode pad 21 may be used.

【００１８】第４工程：図１（Ｄ）参照 次いで、搭載部２６のリード部２３と半導体チップ３０
の電極パッド３１上に形成した緩衝剤３４とをボンディ
ングワイヤ３５でワイヤボンドする。先ずキャピラリ３
３をリード部２３側にファーストボンドする。ボンディ
ングワイヤ３５は例えば直径が３０μｍの金線からな
り、緩衝剤３４としてボール部３２を用いることで、緩
衝剤３４を形成してからワイヤボンディングするまでを
連続的に処理することができる。Fourth Step: See FIG. 1D Next, the lead portion 23 of the mounting portion 26 and the semiconductor chip 30
And a buffering agent 34 formed on the electrode pad 31 of FIG. First, capillary 3
3 is first bonded to the lead portion 23 side. The bonding wire 35 is made of, for example, a gold wire having a diameter of 30 μm. By using the ball portion 32 as the buffer 34, the process from forming the buffer 34 to performing wire bonding can be continuously performed.

【００１９】第５工程：図２（Ａ）参照 次いでキャピラリ３３を移動し、電極パッド３１上の緩
衝剤３４に対してセカンドボンドを行う。緩衝材３４の
表面が半導体チップ３０の表面より突出しており、しか
も比較的軟質素材を選択しているので、キャピラリ３３
の先端部が半導体チップ３０表面に衝突することもな
く、ダメージを与えることもない。また、ボンディング
ワイヤと同素材であるから、接着性も良好である。Fifth Step: See FIG. 2A Next, the capillary 33 is moved, and second bonding is performed on the buffer 34 on the electrode pad 31. Since the surface of the buffer material 34 protrudes from the surface of the semiconductor chip 30 and a relatively soft material is selected, the capillary 33
Does not collide with the surface of the semiconductor chip 30 and does not cause damage. In addition, since it is made of the same material as the bonding wire, it has good adhesiveness.

【００２０】第６工程：図２（Ｂ）参照 搭載した全ての半導体チップ３０に対してワイヤボンデ
ィングした後、共通基板２１の表面に熱硬化性エポキシ
樹脂などの樹脂層３６を形成する。樹脂層３６はトラン
スファーモールドあるいはポッティングによって、半導
体チップ３０を共通に封止するように形成する。Sixth step: See FIG. 2B. After wire bonding to all the mounted semiconductor chips 30, a resin layer 36 such as a thermosetting epoxy resin is formed on the surface of the common substrate 21. The resin layer 36 is formed by transfer molding or potting so as to seal the semiconductor chips 30 in common.

【００２１】第７工程：図２（Ｃ）参照 搭載部２６毎に、ダイシングライン３７に沿って樹脂層
３６と共通基板２１とをダイシングブレード３８でダイ
シングして、個々の半導体装置に分離する。ダイシング
により接続部２７も切断される。Seventh step: See FIG. 2C For each mounting section 26, the resin layer 36 and the common substrate 21 are diced along a dicing line 37 with a dicing blade 38 to separate them into individual semiconductor devices. The connecting portion 27 is also cut by dicing.

【００２２】この様にして製造した半導体装置を図４に
示す。図４は（Ａ）は断面図、図４（Ｂ）は上面図、図
４（Ｃ）は裏面図である。装置全体の寸法は、縦×横が
１．０ｍｍ×０．６ｍｍ程度である。そして、リード部
２３側にファーストボンド、電極パッド３１側にセカン
ドボンドしたので、形状的に半導体チップ３０の端部に
接触しにくい構成であり、半導体チップ３０の表面から
ボンディングワイヤ３５の最大高さまでのループ高さＨ
１を、従来の１５０μｍから、本発明では５０μｍ程度
の高さまで低減することができる。その結果、半導体装
置全体の高さＨ２を、０．４０ｍｍまで容易に薄形化す
ることができる。FIG. 4 shows a semiconductor device manufactured in this manner. 4A is a sectional view, FIG. 4B is a top view, and FIG. 4C is a back view. The dimensions of the entire device are about 1.0 mm × 0.6 mm in length × width. Since the first bonding is performed on the lead portion 23 side and the second bonding is performed on the electrode pad 31 side, the configuration is such that the end portion of the semiconductor chip 30 is hardly contacted, and from the surface of the semiconductor chip 30 to the maximum height of the bonding wire 35. Loop height H
1 can be reduced from the conventional 150 μm to a height of about 50 μm in the present invention. As a result, the height H2 of the entire semiconductor device can be easily reduced to 0.40 mm.

【００２３】また、ボンディングワイヤ３５のファース
トボンド位置を、ビアホール２５上に配置するように形
成すれば、キャピラリ圧力はリード部２３、ビアホール
２５内部の埋設金属及び外部接続電極２４とで支持され
るので、共通基板２１に対して余分な機械的応力を与え
ずにボンディングすることができる。一方、電極パッド
３１側に於いては、電極パッド３１の位置をアイランド
部２２と外部接続電極２４ａとが重畳するような位置関
係に配置することにより、これも共通基板２１に与える
機械的応力を小さくできる。加えて軟質の緩衝剤３２を
用いることにより、キャピラリ圧力を分散できるから、
半導体チップ３０や共通基板２１に対して与えられる機
械的応力を緩和できる。これらの組み合わせにより、半
導体チップ３０と共通基板２１の厚みを更に追い込ん
で、０．３０ｍｍ程度までは、容易に薄形化が可能とな
る。このことは、高さが薄形化できることによって、縦
×横の寸法を更に小型化できる事を意味する。If the first bonding position of the bonding wire 35 is formed on the via hole 25, the capillary pressure is supported by the lead portion 23, the buried metal inside the via hole 25, and the external connection electrode 24. In addition, bonding can be performed without applying extra mechanical stress to the common substrate 21. On the other hand, on the electrode pad 31 side, by arranging the position of the electrode pad 31 in such a positional relationship that the island portion 22 and the external connection electrode 24a overlap, this also reduces the mechanical stress applied to the common substrate 21. Can be smaller. In addition, by using the soft buffer 32, the capillary pressure can be dispersed,
The mechanical stress applied to the semiconductor chip 30 and the common substrate 21 can be reduced. With these combinations, the thickness of the semiconductor chip 30 and the common substrate 21 can be further reduced, and the thickness can be easily reduced to about 0.30 mm. This means that the height and width can be further reduced by reducing the height.

【００２４】[0024]

【発明の効果】以上に説明したように、本発明によれ
ば、多数個の素子を共通の基板で製造し、後から切り出
すようにして製造することによって、安価に大量に且つ
小型化した半導体装置を製造できる利点を有する。As described above, according to the present invention, by manufacturing a large number of elements on a common substrate and cutting them out later, a large-scale and inexpensive semiconductor can be manufactured at low cost. It has the advantage that the device can be manufactured.

【００２５】更に、ボンディングワイヤ３５のファース
トボンドをリード部２３側に配したことにより、半導体
装置の高さＨ２を減じて、更なる軽薄短小化を実現でき
る利点を有するものである。Further, by disposing the first bond of the bonding wire 35 on the lead portion 23 side, the height H2 of the semiconductor device can be reduced, and there is an advantage that further reduction in size and size can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining the present invention.

【図２】本発明を説明するための断面図である。FIG. 2 is a cross-sectional view for explaining the present invention.

【図３】本発明を説明するための（Ａ）上面図（Ｂ）裏
面図である。3A is a top view and FIG. 3B is a back view for explaining the present invention.

【図４】本発明を説明するための（Ａ）断面図、（Ｂ）
上面図、（Ｃ）裏面図である。4A and 4B are cross-sectional views for explaining the present invention.
It is a top view and (C) is a back view.

【図５】従来例を説明するための図である。FIG. 5 is a diagram for explaining a conventional example.

【符号の説明】[Explanation of symbols]

２１ 共通基板 ２３ リード部 ２４ 外部接続電極 ３０ 半導体チップ ３１ 電極パッド ３２ 緩衝剤 DESCRIPTION OF SYMBOLS 21 Common board 23 Lead part 24 External connection electrode 30 Semiconductor chip 31 Electrode pad 32 Buffer

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップを搭載するアイランド部
と、前記半導体チップの電極と接続されるリード部とを
有する搭載部を、多数個配列した共通の基板を準備する
工程と、 前記搭載部の各々に半導体チップを固着する工程と、 前記半導体チップの電極パッドと前記リード部とを、前
記リード部側にファーストボンドし、前記電極パッド側
にセカンドボンドしたボンディングワイヤで接続する工
程と、 前記多数の搭載部を共通の樹脂層で被覆する工程と、 前記搭載部毎に前記樹脂層と前記共通基板とを分離し
て、個々の半導体装置を形成する工程と、を具備するこ
とを特徴とする半導体装置の製造方法。A step of preparing a common substrate on which a plurality of mounting portions each having an island portion for mounting a semiconductor chip and a lead portion connected to an electrode of the semiconductor chip are arranged; Fixing the semiconductor chip to the semiconductor chip; connecting the electrode pads of the semiconductor chip and the lead portions to the lead portion side by first bonding, and connecting the electrode pads to the second bonding pads by a second-bonded bonding wire; A semiconductor comprising: a step of covering a mounting portion with a common resin layer; and a step of separating the resin layer and the common substrate for each mounting portion to form individual semiconductor devices. Device manufacturing method. 【請求項２】 前記電極パッドの上に緩衝部材を形成
し、前記緩衝部材に対して前記ボンディングワイヤをセ
カンドボンドする事を特徴とする請求項１記載の半導体
装置の製造方法。2. The method according to claim 1, wherein a buffer member is formed on the electrode pad, and the bonding wire is second-bonded to the buffer member. 【請求項３】 前記緩衝剤が、前記ボンディングワイヤ
のボール部をファーストボンドし、前記ボール部だけを
前記電極パッド上に残したものであることを特徴とする
請求項２記載の半導体装置の製造方法3. The manufacturing method of a semiconductor device according to claim 2, wherein said buffering agent first bonds a ball portion of said bonding wire and leaves only said ball portion on said electrode pad. Method
JP2000094071A 2000-03-30 2000-03-30 Method of manufacturing semiconductor device Pending JP2001284370A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000094071A JP2001284370A (en) 2000-03-30 2000-03-30 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000094071A JP2001284370A (en) 2000-03-30 2000-03-30 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2001284370A true JP2001284370A (en) 2001-10-12

Family

ID=18609166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000094071A Pending JP2001284370A (en) 2000-03-30 2000-03-30 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2001284370A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184385A (en) * 2006-01-06 2007-07-19 Renesas Technology Corp Semiconductor device, and method of manufacturing same
EP2617593A1 (en) * 2012-01-19 2013-07-24 Nishikawa Rubber Co., Ltd. Cover member for automobiles
WO2014119146A1 (en) * 2013-01-31 2014-08-07 シャープ株式会社 Method for manufacturing light-emitting device, and light-emitting device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184385A (en) * 2006-01-06 2007-07-19 Renesas Technology Corp Semiconductor device, and method of manufacturing same
EP2617593A1 (en) * 2012-01-19 2013-07-24 Nishikawa Rubber Co., Ltd. Cover member for automobiles
US8783750B2 (en) 2012-01-19 2014-07-22 Nishikawa Rubber Co., Ltd. Cover member for automobiles
WO2014119146A1 (en) * 2013-01-31 2014-08-07 シャープ株式会社 Method for manufacturing light-emitting device, and light-emitting device
CN104904025A (en) * 2013-01-31 2015-09-09 夏普株式会社 Method for manufacturing light-emitting device, and light-emitted device
JPWO2014119146A1 (en) * 2013-01-31 2017-01-26 シャープ株式会社 LIGHT EMITTING DEVICE MANUFACTURING METHOD AND LIGHT EMITTING DEVICE
CN104904025B (en) * 2013-01-31 2018-04-03 夏普株式会社 The manufacture method and light-emitting device of light-emitting device

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