JP2000188626A5 - - Google Patents

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Publication number
JP2000188626A5
JP2000188626A5 JP1999327311A JP32731199A JP2000188626A5 JP 2000188626 A5 JP2000188626 A5 JP 2000188626A5 JP 1999327311 A JP1999327311 A JP 1999327311A JP 32731199 A JP32731199 A JP 32731199A JP 2000188626 A5 JP2000188626 A5 JP 2000188626A5
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JP
Japan
Prior art keywords
data
serial bus
bus
register
host
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999327311A
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English (en)
Japanese (ja)
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JP2000188626A (ja
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Publication date
Application filed filed Critical
Publication of JP2000188626A publication Critical patent/JP2000188626A/ja
Publication of JP2000188626A5 publication Critical patent/JP2000188626A5/ja
Pending legal-status Critical Current

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JP11327311A 1998-10-13 1999-10-13 一体のマイクロコントロ―ラ・エミュレ―タを有するリンク／トランザクション層コントロ―ラ Pending JP2000188626A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10393798P 1998-10-13 1998-10-13
US103937 1998-10-13

Publications (2)

Publication Number Publication Date
JP2000188626A JP2000188626A (ja) 2000-07-04
JP2000188626A5 true JP2000188626A5 (https=) 2006-11-30

Family

ID=22297802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11327311A Pending JP2000188626A (ja) 1998-10-13 1999-10-13 一体のマイクロコントロ―ラ・エミュレ―タを有するリンク／トランザクション層コントロ―ラ

Country Status (2)

Country Link
US (1) US6513085B1 (https=)
JP (1) JP2000188626A (https=)

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US7171506B2 (en) * 2003-11-17 2007-01-30 Sony Corporation Plural interfaces in home network with first component having a first host bus width and second component having second bus width
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US7995606B1 (en) 2003-12-03 2011-08-09 Apple Inc. Fly-by and ack-accelerated arbitration for broadcast packets
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US7502338B1 (en) 2003-12-19 2009-03-10 Apple Inc. De-emphasis training on a point-to-point connection
US7237135B1 (en) 2003-12-29 2007-06-26 Apple Inc. Cyclemaster synchronization in a distributed bridge
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US8650304B2 (en) 2004-06-04 2014-02-11 Qualcomm Incorporated Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system
US9201599B2 (en) * 2004-07-19 2015-12-01 Marvell International Ltd. System and method for transmitting data in storage controllers
US8723705B2 (en) 2004-11-24 2014-05-13 Qualcomm Incorporated Low output skew double data rate serial encoder
US8873584B2 (en) 2004-11-24 2014-10-28 Qualcomm Incorporated Digital data interface device
US8692838B2 (en) 2004-11-24 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US8699330B2 (en) 2004-11-24 2014-04-15 Qualcomm Incorporated Systems and methods for digital data transmission rate control
US8667363B2 (en) 2004-11-24 2014-03-04 Qualcomm Incorporated Systems and methods for implementing cyclic redundancy checks
US8539119B2 (en) 2004-11-24 2013-09-17 Qualcomm Incorporated Methods and apparatus for exchanging messages having a digital data interface device message format
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US8692839B2 (en) 2005-11-23 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US8730069B2 (en) 2005-11-23 2014-05-20 Qualcomm Incorporated Double data rate serial encoder
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JP4854050B2 (ja) * 2009-09-24 2012-01-11 エヌイーシーコンピュータテクノ株式会社 ノード制御装置、ノード制御装置の制御方法、情報処理システム、及びコンピュータプログラム
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TWI677711B (zh) * 2017-11-13 2019-11-21 財團法人金屬工業研究發展中心 虛實影像整合裝置
US10628077B2 (en) * 2018-03-23 2020-04-21 Hamilton Sundstrand Corporation System to acquire analog to digital (ADC) data using high end timer (N2HET) and high end timer transfer unit (HTU)
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US6157972A (en) * 1997-12-05 2000-12-05 Texas Instruments Incorporated Apparatus and method for processing packetized information over a serial bus
US6327637B1 (en) * 1998-12-18 2001-12-04 Cirrus Logic, Inc. Interface tap for 1394-enabled serial bus device

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