JP2000174249A - Ccd solid state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the transfer efficiency of a horizontal register and increase the handling charge quantity of a vertical register by increasing the transfer electric field of the horizontal register and the handling charge quantity of the vertical register because of a deep potential of the transfer channel. SOLUTION: A p-type region 25a and an n-type buried channel region 26a are formed on a p-type well region 21, and a transfer electrode 36 composed of a set of a storage electrode 34 and a transfer electrode 35 is formed through a gate insulation film 28 thereon. In a CCD solid state image sensing element, esp., a horizontal transfer register 3 is implanted with additional impurity ions, the impurity profiles and potentials of a vertical transfer register 2 and the horizontal transfer register 3 are formed in optimum conditions, respectively, thereby constituting a CCD solid state image pickup element. Since the handling signal quantity Qv of the vertical transfer register 2 and the horizontal transfer register electric field E11 can be large, a CCD solid state image pickup element having a high required specification level can be easily realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD solid-state imaging device in which sensors are two-dimensionally arranged in a matrix.

[0002]

2. Description of the Related Art General interline transfer type CC
FIG. 7 shows a schematic plan view of the D solid-state imaging device. As shown in FIG. 7, in the CCD solid-state imaging device 10, a plurality of light receiving units (sensors) 1 are arranged in a matrix, and a vertical transfer register 2 having a CCD structure is provided on one side of the light receiving unit 1 corresponding to each column.
And a common horizontal transfer register 3 having a CCD structure is provided at one end of each vertical transfer register 2.
The signal charge photoelectrically converted by the light receiving unit 1 is read out to the vertical transfer register 2 through the readout gate unit 4, and the signal charge is transferred to the horizontal transfer register 3 by, for example, four-phase drive transfer by the vertical transfer register 2. The data is transferred in the horizontal transfer register 3 by, for example, two-phase driving, and the output
Through the output terminal 6 sequentially.

The CC of the interline transfer system shown in FIG.
In the D solid-state imaging device 10, the cross-sectional structure along the line II 'from the light receiving section 1 to the vertical transfer register 2 and the cross-sectional structure along the line II-II' of the horizontal transfer register 3 are shown in FIGS. It is configured as follows. That is, FIG.
As shown in FIG. 1, a low-concentration second conductivity type, ie, p-type well region (hereinafter referred to as a first p-type well region) 42 is formed on a first conductivity type, for example, an n-type semiconductor substrate 41, and the first conductivity type is formed. p
The light receiving section 1 and the vertical transfer register 2 are formed in the mold well area 42. The light receiving section 1 forms, for example, an n region 43 that forms a photodiode with the first p-type well region 42 on the first p-type well region 42, and furthermore, forms a hole accumulation layer on the surface of the n-type region 43. It has a so-called buried photodiode structure in which ap ⁺ region 44 is formed.

On the other hand, the vertical transfer register 2 sequentially forms a higher concentration p-type region (second p-type well region) 46 and an n-type buried channel region 47 on the first p-type well region 42. Into a so-called embedded channel type,
A vertical transfer electrode 49 made of, for example, polycrystalline silicon is formed on the buried channel region 47 with a gate insulating film 48 interposed therebetween.
Is formed.

The read gate section 4 between the light receiving section 1 and the vertical transfer register 2 is formed by extending a vertical transfer electrode 49 on the first p-type well area 42 with a gate insulating film 48 interposed therebetween. 52 denotes an insulating film such as SiO ₂ and 53 denotes a p ⁺ channel stop region. The read gate unit 4
Is formed on the first p-type well region 42 at a higher concentration (p
⁺ ) Is formed, and a gate insulating film 48 is formed thereon.
May be formed.

[0006] As shown in FIG. 5, the horizontal transfer register 3 includes the p-type region 46 on the first p-type well region 42.
And p formed simultaneously with the n-type region 47 as described later.
A mold region 46a and an n-type buried channel region 47a are formed to form a so-called buried channel type, and a two-phase transfer electrode made of, for example, polycrystalline silicon, ie, a storage, is formed on the buried channel region 47a via a gate insulating film 48. A horizontal transfer electrode 56 composed of an electrode 54 and a transfer electrode 55 is formed.

[0007] Conventionally, as shown in FIG.
Impurity ion implantation has been performed on the vertical transfer register 2 and the horizontal transfer register 3 of the CD solid-state imaging device 10 under the same ion implantation conditions. The process of this ion implantation will be described.

First, a first p-type well region (1PW) 4
In order to form 2, a p-type impurity is ion-implanted into the n-type semiconductor substrate 41 at a high energy of about several MeV. Thereafter, a p-type impurity is implanted at an energy of several hundred keV into the first p-type well region 42 in a portion to be the vertical transfer register 2 and the horizontal transfer register 3, thereby forming a second p-type impurity.
The mold well regions 46 and 46a are formed. Subsequently, buried channels 47 and 47a are formed by ion-implanting an n-type impurity with an energy of several hundred keV.

Therefore, the impurity profiles and potential diagrams on the XX 'line of the vertical transfer register 2 and the YY' line of the horizontal transfer register 3 are shown in FIGS. 6A and 6B.
It becomes as shown in. In FIG. 6A, p (1PW) is the first p-type well region 42, p (2PW) is the second p-type well region 46, 46a, and n is the buried channel 4.
7 and 47a respectively show impurity concentration distributions. In FIG. 6B, the potential value at the deepest point of the transfer channel is Pc, and the distance from the surface is d.

[0010]

However [0005] In the case of forming the vertical transfer register 2 and the horizontal transfer register 3 as described above at the same impurity profile, to make the handling signal amount Q _v of the vertical transfer register 2, When the transfer channel is made closer to the surface and the transfer channel potential is made shallower by ion-implanting n-type impurities with low acceleration energy, the horizontal register transfer electric field E
_H can no longer earn.

That is, in the potential diagram of FIG.
When both c and d are reduced, the signal amount Q _v handled by the vertical transfer register 2 can be increased, but the horizontal register transfer electric field E _H decreases. When the horizontal register transfer electric field E _H is small, the transfer efficiency of the horizontal transfer is deteriorated, and it is difficult to increase the transfer speed.

Conversely, in order to increase the horizontal register transfer electric field E _H , the transfer channel is made farther from the surface and the potential of the transfer channel is made deeper by ion-implanting n-type impurities with a high acceleration energy. since the channel is away from the transfer electrodes, the change in potential of the transfer electrodes is small effect on the transfer channel, resulting vertical transfer register 2 handling signal amount Q _v is reduced.

That is, in the potential diagram of FIG.
When both c and d are increased, the horizontal register transfer electric field E _H can be increased, but the handled signal amount Q _v of the vertical transfer register 2 decreases.

In order to solve the above-mentioned problem, a method of separately forming the vertical transfer register 2 and the horizontal transfer register 3 under optimum conditions (impurity concentration and the like) may be considered.

However, when such a method of making a difference is adopted, when a misalignment occurs between the vertical transfer register 2 and the horizontal transfer register 3, a so-called potential dip (potential pocket) is easily generated. Problem may occur. When the potential dip occurs, the transfer of the signal charge is not completely performed, and the transfer efficiency is reduced.

In order to solve the above-mentioned problems, the present invention provides a CCD solid-state imaging device capable of improving both the transfer efficiency of a horizontal register and the charge amount handled by a vertical register.

[0017]

In the CCD solid-state imaging device according to the present invention, the potential of the transfer channel of the horizontal register is formed deeper than the deepest potential of the transfer channel of the vertical register, and the potential of the transfer channel of the horizontal register is most deep. Is formed such that the deeper the position is, the longer the distance from the transfer electrode is to the position where the potential of the transfer channel of the vertical register is deepest.

According to the configuration of the present invention described above, since the potential of the transfer channel of the horizontal register is deep, the electric field of the horizontal register transfer can be increased. Also, the position where the potential of the transfer channel of the vertical register is deepest is
Since the distance from the transfer electrode is shorter than the deepest position of the transfer channel of the horizontal register, a change in the potential of the transfer electrode is more effectively applied to the transfer channel, so that the amount of charge handled by the vertical register can be increased.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a CCD solid-state imaging device in which sensors are two-dimensionally arranged in a matrix, and a vertical register for transferring signal charges generated by sensors in each column, and a vertical register for transferring signal charges. Signal charge
A horizontal register for transferring each row, wherein the potential of the transfer channel of the horizontal register is formed deeper than the deepest potential of the transfer channel of the vertical register, and the position where the potential of the transfer channel of the horizontal register is deepest is vertically This is a CCD solid-state imaging device formed so that the distance from the transfer electrode is longer than the deepest position of the transfer channel of the register.

FIG. 1 and FIG. 2 are cross-sectional views showing a main part of a CCD solid-state imaging device as one embodiment of the present invention. still,
The CCD solid-state imaging device of the present embodiment is a CCD solid-state imaging device 10 of the interline transfer system shown in FIG.
FIGS. 1 and 2 correspond to a cross-sectional view taken along the line II ′ and a cross-sectional view taken along the line II-II ′.

In this embodiment, as shown in FIG. 2, the configuration relating to the light receiving section 1 and the vertical transfer register 2 is the same as the configuration shown in FIG. That is, a low-concentration second conductivity type, that is, a p-type well region (hereinafter referred to as a first p-type well region) 21 is formed on a first conductivity type, for example, an n-type semiconductor substrate 20, and the first p-type well region 21 is formed. The light receiving portion 1 and the vertical transfer register 2 are formed in the well region 21. The light receiving section 1 includes, for example, an n-type region 2 that forms a photodiode on the first p-type well region 21 with the first p-type well region 21.
2 and a so-called buried photodiode structure in which ap ⁺ region 23 serving as a hole accumulation layer is formed on the surface of the n-type region 22.

The vertical transfer register 2 forms a so-called buried channel type by sequentially forming a higher concentration p-type region 25 and an n-type buried channel region 26 on the first p-type well region 21. A vertical transfer electrode 29 made of, for example, polycrystalline silicon is formed on the region 26 with a gate insulating film 28 interposed therebetween. 6A and 6B show an impurity profile and a potential diagram on the BB 'line of the vertical register 2. FIG.
In this vertical transfer register 2, the potential value Pc at the deepest point of the vertical transfer channel in FIG. 6B is P ₂ , and the distance d from this surface to the surface is d ₂ .

The read gate section 4 between the light receiving section 1 and the vertical transfer register 2 also has a first p-type well region 2 as in FIG.
1 is formed by extending a vertical transfer electrode 29 with a gate insulating film 28 interposed therebetween. 30 is an insulating film such as SiO ₂ , 3
2 indicates a p ⁺ channel stop region. Note that the read gate unit 4 may be formed by forming a p-type region having a higher concentration (p ⁺ ) on the first p-type well region 21 and forming a gate insulating film 28 thereon. Good.

On the other hand, the configuration related to the horizontal transfer register 3 is the same as the configuration shown in FIG. 5 as shown in FIG.
However, as will be described later, the impurity profile and the potential are different from those in the related art. That is, the p-type well region 21 has p
A type region 25a and an n-type buried channel region 26a are formed to form a so-called buried channel type, and a two-phase transfer electrode made of, for example, polycrystalline silicon, ie, a storage, is formed on the buried channel region 26a via a gate insulating film 28. The transfer electrode 36 is formed by forming an electrode 34 and a transfer electrode 35 as a set.

As will be described later, the p-type region 25a and the n-type buried channel region 26a are different from the state where the impurity is ion-implanted simultaneously with the p-type region 25 and the n-type region 26. different. Therefore, the depth of the region, the impurity concentration, and the like do not always match those of the p-type region 25 and the n-type region 26 described above.

In the CCD solid-state imaging device according to the present embodiment, additional ion implantation of an n-type impurity is particularly performed on the horizontal transfer register 3 to optimize the impurity profiles and potentials of the vertical transfer register 2 and the horizontal transfer register 3 respectively. The CCD solid-state imaging device is formed under the following conditions.

Next, the vertical transfer register 2 and the horizontal transfer register 3 in the CCD solid-state image pickup device of the present embodiment.
Will be described.

First, as in the case of the conventional structure, the n-type semiconductor substrate 2 is formed so as to include all the regions 2 and 3 serving as registers.
With respect to 0, a first p-type well region 21 is formed by ion-implanting a p-type impurity with high energy of about several MeV.

Next, a second p-type well region 25 is formed by ion-implanting a p-type impurity with an energy of several hundred keV. Further, an buried channel 26 is formed by ion-implanting an n-type impurity with an energy of several hundred keV.

In this embodiment, in particular, only the horizontal transfer register 3 is thereafter doped with n-type impurities at a higher acceleration energy (on the order of several hundred keV or more) than when the buried channel 26 is first formed. An additional ion implantation step is provided.

FIG. 3A shows an impurity concentration distribution of the horizontal transfer register 3 in the present embodiment. FIG. 3B shows a potential diagram of the horizontal transfer register 3 in the present embodiment.

In FIG. 3A, n (HPA) indicated by a broken line indicates one form of the impurity concentration distribution of the n-type impurity in the above-mentioned additional step. Since the acceleration energy is high, the buried channel 26 is formed at a position deeper than the impurity distribution of the original buried channel 26 shown in FIG.

The HPA shown in FIG.
esister Potential Adjust (horizontal register potential adjustment). Further, regarding the horizontal transfer register 3, the potential value Pc at the deepest portion of the horizontal transfer channel in FIG. 3B is P ₁ , and the distance d from this surface to the surface is d ₁ .

With the additional ion implantation described above, d can be increased, that is, the position of the horizontal transfer channel can be made farther from the surface as shown in FIG. 3B. Further, the potential Pc of the horizontal transfer channel can be increased.

That is, the most potential of the horizontal transfer channel
D = d from the surface at a deep position _HAnd vertical transfer channel
Distance d from the surface at the deepest potential
d_VIs compared with FIG. 3B._H= D₁And figure
D from 6B_V= D_TwoAnd d₁> D_TwoSo d_H
> D_VAnd the horizontal transfer channel is
The distance from the surface is large and formed at a deep position.

Further, comparing the potential value Pc = P _{H at} the deepest position of the horizontal transfer channel with the potential value Pc = P _{V at} the same position of the vertical transfer channel, it can be seen from FIG. 3B that P _H = P _{H. 1,} a P _V = P ₂ from FIG. 6B, P because it is _{P 1> P 2 H> P} V
Thus, the potential of the horizontal transfer channel becomes deeper than that of the vertical transfer channel. Therefore, the horizontal register transfer electric field E
It is also easy to increase _H.

As a result of the additional ion implantation, in the horizontal transfer register 3, the p-type region 25a and the n-type region 26 shown in FIG.
And an n-type buried channel region 26a is formed. At this time, the p-type region 25 and the n-type region 26 of the vertical transfer register 2 form the p-type region 25a and the n-type buried channel region 26a, for example, in which the depth, impurity concentration, and the like are changed by additional ion implantation. Is done.

In addition, since the potential Pc of the horizontal transfer channel is deepened by the additional ion implantation of the n-type impurity, the potential barrier PB with respect to the substrate 20 is lowered, and the injection of noise charges from the substrate 20 is problematic. In such a case, the second p-type well region (2
PW). Additional ion implantation of a p-type impurity with the same energy as in the formation of the PW) 25 (for example, p
(HPA)) to adjust the potential of the horizontal transfer channel and its surroundings.

According to the CCD solid-state imaging device of the present embodiment described above, since the potential Pc of the transfer channel of the horizontal transfer register 3 is deep, the horizontal register transfer electric field E _H can be increased. Further, since the distance d from the transfer electrodes of the transfer channel vertical transfer register 2 are close, the change in the potential of the transfer electrodes extend effectively the transfer channel, increasing the handling charge amount Q _v of the vertical transfer register 2 Can be.

Therefore, the handling signal of the vertical transfer register 2
No. Q_vAnd horizontal register transfer electric field E _HBoth larger than before
And the level of these required specifications
High-performance CCD solid-state imaging device can be easily realized.
You.

At this time, since the vertical transfer register 2 and the horizontal transfer register 3 are not completely formed separately, it is possible to avoid problems such as potential dip caused by misalignment occurring during the manufacturing process. .

In the above embodiment, the present invention is applied to an interline transfer type CCD solid-state image pickup device. However, the present invention can be applied to other configurations such as a frame interline transfer type CCD solid state image pickup device.

The CCD solid-state imaging device according to the present invention is not limited to the above-described embodiment, but may take various other configurations without departing from the gist of the present invention.

[0044]

According to the above-described CCD solid-state imaging device according to the present invention, since the potential of the transfer channel of the horizontal register is deep, the horizontal register transfer electric field can be increased. Therefore, high transfer efficiency and transfer speed can be secured.

The position where the potential of the transfer channel of the vertical register is deepest is closer to the transfer electrode than the deepest position of the transfer channel of the horizontal register, so that the amount of charge handled by the vertical register can be increased. .

Accordingly, both the signal amount handled by the vertical register and the transfer electric field of the horizontal register can be made larger than in the past, and a CCD solid-state imaging device having a high level of these required specifications can be easily realized.

Further, it is possible to avoid problems such as generation of potential dips due to misalignment occurring during the manufacturing process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a horizontal transfer register of a CCD solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a light receiving unit and a vertical transfer register of the CCD solid-state imaging device according to the embodiment.

FIG. 3 is a graph showing an impurity profile in an AA ′ section of FIG. 1; B It is a potential diagram of an AA 'section of FIG.

FIG. 4 is a cross-sectional view illustrating a configuration of a light receiving unit and a vertical transfer register of a conventional CCD solid-state imaging device.

FIG. 5 is a cross-sectional view illustrating a configuration of a horizontal transfer register of a conventional CCD solid-state imaging device.

6A is a diagram showing impurity profiles on the line XX ′ in FIG. 4 and on the line YY ′ in FIG. 5; B X in FIG.
FIG. 6 is a potential diagram on a line −X ′ and a line YY ′ in FIG. 5.

FIG. 7 is a schematic diagram (plan view) of an interline transfer type CCD solid-state imaging device.

[Explanation of symbols]

Reference Signs List 1 light receiving unit (sensor), 2 vertical transfer register, 3 horizontal transfer register, 4 read gate, 5 output amplifier, 6 output terminal, 10 CCD solid-state image sensor, 20
Semiconductor substrate, 21 first p-type well region, 22 n
Type region, 23p ⁺ region, 25p type region, 26 buried channel region, 28 gate insulating film, 29 vertical transfer electrode, 30 insulating film, 32 channel stop region,
34 storage electrode, 35 transfer electrode, 3
6 Horizontal transfer electrodes

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA03 AB01 BA13 BA16 CA04 DA03 DA32 EA15 FA06 FA26 FA35 5C024 AA01 CA16 CA31 FA01 GA11 GA16 GA17 JA21

Claims (1)

[Claims] 1. A CCD solid-state imaging device in which sensors are two-dimensionally arranged in a matrix, wherein: a vertical register for transferring signal charges generated by sensors in each column; and the signal charges transferred by the vertical register. And a horizontal register for transferring the data by one row. The potential of the transfer channel of the horizontal register is formed deeper than the deepest potential of the transfer channel of the vertical register. Wherein the deeper position is formed so that the distance from the transfer electrode is longer than the deepest position of the transfer channel of the vertical register.
Solid-state imaging device.