JP4183302B2 - Method for manufacturing charge coupled device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge coupled device, and more particularly to a method for manufacturing a charge coupled device applicable to a solid-state imaging device having a two-stage horizontal transfer path.
[0002]
[Prior art]
FIG. 2 is a configuration diagram of the solid-state imaging device 1 having the two-stage horizontal transfer path 5.
[0003]
The pixel unit 2 has a plurality of vertical transfer paths 4 arranged in a vertical direction with a plurality of photodiodes 3 arranged two-dimensionally. One photodiode 3 corresponds to one pixel constituting a two-dimensional image, and converts received light into electric charge. The converted charge is transferred from the photodiode 3 to the vertical transfer path 4. The vertical transfer path 4 transfers charges in the vertical direction.
[0004]
The two-stage horizontal transfer path 5 includes a first horizontal transfer path 5a and a second horizontal transfer path 5b. Both the vertical transfer path 4 and the horizontal transfer paths 5a and 5b are constituted by charge coupled devices (CCD). The charges on the vertical transfer path 4 are transferred vertically downward, and are transferred to either the first horizontal transfer path 5a or the second horizontal transfer path 5b. The first and second horizontal transfer paths 5a and 5b transfer charges in the horizontal left direction.
[0005]
The first amplifier 6a amplifies the charge transferred in the horizontal direction by the first horizontal transfer path 5a and outputs it to the outside. The second amplifier 6b amplifies the charge transferred in the horizontal direction by the second horizontal transfer path 5b and outputs it to the outside.
[0006]
For example, a solid-state imaging device for capturing a high-resolution image, such as a high-definition television (HDTV), has a large number of pixels, and thus needs to transfer charges at high speed. Therefore, in order to improve the charge transfer efficiency of the CCD and equalize the sensitivity of the amplifier, the solid-state imaging device having the two-stage horizontal transfer path is used.
[0007]
The configuration of the boundary area 7 between the first horizontal transfer path 5a and the second horizontal transfer path 5b is shown below.
[0008]
FIG. 3 is a conceptual diagram of the boundary area 7 and is a diagram obtained by rotating FIG. 1A by 90 °. A shift gate 12 is provided between the first horizontal transfer path 5a and the second horizontal transfer path 5b. In the potential waveforms S1 and S2, the horizontal axis indicates the position on the first or second transfer path 5a, 5b or the shift gate 12, and the vertical axis indicates the potential with respect to charges (electrons).
[0009]
The potential waveform S1 is a waveform when the shift gate 12 is closed without a gate signal being applied to the shift gate 12. After the charge on the vertical transfer path is transferred to the first horizontal transfer path 5a, the charge remains on the first horizontal transfer path 5a because the shift gate 12 is closed.
[0010]
The potential waveform S2 is a waveform when the gate signal is applied to the shift gate 12 and the shift gate 12 is opened. After the charge 13 on the vertical transfer path is transferred to the first horizontal transfer path 5a, the shift gate 12 is open, so that the charge 13 on the vertical transfer path is in the vertical direction (the horizontal direction in FIG. 3) toward the second horizontal transfer path 5b. Moved to. Thereafter, if the shift gate 12 is closed, the charge remains in the second horizontal transfer path 5b.
[0011]
As described above, by controlling the shift gate 12, the charge on the vertical transfer path can be transferred to the first horizontal transfer path 5a or the second horizontal transfer path 5b.
[0012]
FIG. 4 is a diagram for explaining the operation of transferring the charges 11 in the horizontal direction in the first horizontal transfer path 5a.
[0013]
The horizontal transfer path 5a is configured by setting a first well region W1, a first barrier region B1, a second well region W2, and a second barrier region B2 as a set, and repeatedly providing them in the horizontal direction. . A drive signal Hφ1 is supplied to the first well region W1 and the first barrier region B1, and a drive signal Hφ2 is supplied to the second well region W2 and the second barrier region B2. The horizontal transfer path 5a is two-phase driven by drive signals Hφ1 and Hφ2.
[0014]
The potential waveform S1 is a waveform when the drive signals Hφ1 and Hφ2 are both 0V. The effective impurity concentration of the well regions W1 and W2 is adjusted so that the potential is lower than that of the barrier regions B1 and B2. For example, the well regions W1 and W2 are high impurity concentration n-type regions, and the barrier regions B1 and B2 are low impurity concentration n-type regions. Well regions W1 and W2 have substantially the same potential, and barrier regions B1 and B2 have substantially the same potential.
[0015]
The potential waveform S2 is a waveform when the drive signal Hφ1 is 5V and the drive signal Hφ2 is 0V. The horizontal transfer path 5a has a potential gradient and gradually changes from a high potential region to a low region in the order of the regions B2, W2, B1, and W1. The electric charge 11 is transferred in the horizontal left direction according to the above-described potential gradient.
[0016]
5A to 5D are device cross-sectional views for explaining a manufacturing process of a horizontal transfer path (charge coupled device) according to a conventional technique.
[0017]
First, as shown in FIG. 5A, n-type impurities 23 are ion-implanted into the surface of the p-type Si region 21 in the Si substrate to form an n-type Si region 22 on the surface of the p-type Si region 21.
[0018]
Next, as shown in FIG. 5B, the surface of the n-type Si region 22 is made of SiO. ₂ A layer 24 is formed, and a first poly gate 25 having a predetermined pattern made of polycrystalline Si is formed thereon. The first poly gate 25 corresponds to an electrode formed on the well regions W1 and W2.
[0019]
Next, as shown in FIG. 5C, p-type impurities 27 are ion-implanted into the substrate using the first poly gate 25 as a mask. A p-type Si region 26 is formed on the surface of the n-type Si region 22 under the window where the first poly gate 25 is not provided. The n-type Si region 22 below the p-type Si region 26 corresponds to the barrier regions B1 and B2. The n-type Si region 22 below the first poly gate 25 corresponds to the well regions W1 and W2.
[0020]
Next, as shown in FIG. 5D, with the first poly gate 25 as a mask, SiO 2 ₂ A part of the layer 24 is anisotropically etched, and then the entire surface of the substrate is SiO. ₂ The layer 28 is formed by thermal oxidation and CVD, and a second poly gate 29 having a predetermined pattern made of polycrystalline Si is formed thereon. The first poly gate 25 is a gate electrode for controlling the n-type Si region (well region) 22, and the second poly gate 29 is a gate electrode for controlling the p-type Si region (barrier region) 26.
[0021]
The potential waveform S1 is a potential waveform in the n-type region 22 when the potentials of the first and second poly gates 25 and 29 are both 0V. The p-type Si region 26 under the second poly gate 29 has a high potential and becomes barrier regions B1 and B2. The n-type Si region 22 under the first poly gate 25 has a low potential and becomes well regions W1 and W2.
[0022]
[Problems to be solved by the invention]
By controlling the drive signals Hφ1 and Hφ2, the first and second horizontal transfer paths 5a and 5b can transfer charges in the horizontal direction. In the two-stage horizontal transfer path 5, the charge is vertically transferred from the first horizontal transfer path 5a to the second horizontal transfer path 5b by controlling the shift gate 12 without affecting the charge transfer in the horizontal direction. The problem is that it is difficult to transfer smoothly in the direction.
[0023]
Next, the configuration of the two-stage horizontal transfer path 5 for solving the above problem will be described.
FIG. 6A is a configuration diagram of the boundary area 7 (FIG. 2) according to the prior art. A shift gate 12 is provided between the first horizontal transfer path 5a and the second horizontal transfer path 5b. In FIG. 4, four regions W1, B1, W2, and B2 are shown, but in FIG. 6A, for convenience of explanation, the region of FIG. 4 is shifted by two to the left, and four regions W2, B2, W1, and B1 are displayed. Indicates the area.
[0024]
The horizontal transfer paths 5a and 5b are configured by setting the second well region W2, the second barrier region B2, the first well region W1, and the first barrier region B1 as a set, and repeatedly providing them in the horizontal direction. Is done. A drive signal Hφ1 is supplied to the first well region W1 and the first barrier region B1, and a drive signal Hφ2 is supplied to the second well region W2 and the second barrier region B2. Horizontal transfer paths 5a and 5b are two-phase driven by drive signals Hφ1 and Hφ2.
[0025]
The well regions W1 and W2 in the first horizontal transfer path 5a have a tapered shape that gradually expands toward the second horizontal transfer path 5b. Conversely, the barrier regions B1 and B2 in the first horizontal transfer path 5a have a reverse taper shape that gradually narrows toward the second horizontal transfer path 5b.
[0026]
FIG. 6B shows the electric field generated in the first well region W1 by a broken line. Since the well region W1 has a taper shape, a potential increases from a narrow width (horizontal distance) region to a wide width region (from the top to the bottom in the figure) due to the side effect ( (Potential is low). The well region W1 generates a built-in potential due to a difference in impurity concentration at the boundary with the barrier regions B1 and B2. The well region W1 has a higher potential (lower potential) toward the inside from the boundary with the barrier region. By making the well region W1 tapered, a natural potential gradient can be generated in the vertical direction.
[0027]
As shown in the potential waveform S2 of FIG. 4, the charges 11 are accumulated in the first well region W1 by the horizontal transfer. As shown in FIG. 6A, the charge 31 in the well region W1 moves vertically downward in accordance with the potential gradient. Then, by opening the shift gate 12, the charge 31 passes between the channel stop regions 33a and 33b and is transferred to the second horizontal transfer path 5b. The channel stop regions 33a and 33b are doped with an impurity having a conductivity opposite to that of the well region, and have a higher potential than the surroundings.
[0028]
FIG. 16 is a cross-sectional view taken along the line AA in FIG. Although omitted in FIG. 6A, SiO 2 is formed on the well region W1 and the barrier region B2. ₂ Through the layer 24, the shift gate 12, the well gate electrode 25, and the barrier gate electrode 29 are formed. Shift gate 12 and gate electrodes 25 and 29 are mutually connected to SiO. ₂ Insulated by layer 24. Below the shift gate 12, a boundary between the well region W1 and the barrier region B2 exists. The shift gate 12 is an electrode for shifting charges from the first horizontal transfer path 5a to the second horizontal transfer path 5b.
[0029]
The manufacturing method of the well gate electrode 25 and the barrier gate electrode 29 has already been described with reference to FIGS. The well gate electrode 25 is an electrode for applying a voltage to the well region W1, and the barrier gate electrode 29 is an electrode for applying a voltage to the barrier region B2.
[0030]
As described above, by forming the well region W1 in a tapered shape, a natural potential gradient is generated, and charges can be smoothly transferred in the vertical direction. However, this method has a limit in generating a potential gradient, and it is difficult to generate a steep potential gradient.
[0031]
An object of the present invention is to provide a method of manufacturing a charge coupled device applicable to a solid-state imaging device having a two-stage horizontal transfer path for smoothly transferring charges in the vertical direction.
[0032]
[Means for Solving the Problems]
According to one aspect of the present invention, A well region and a barrier region are repeatedly provided in the horizontal direction, A first horizontal transfer path that receives charges from a plurality of vertical transfer paths and transfers charges in the horizontal direction, and receives charges from the plurality of vertical transfer paths via the first horizontal transfer path and charges in the horizontal direction. A solid-state imaging device having: a second horizontal transfer path that transfers a charge; and a shift gate that selectively supplies a charge from the plurality of vertical transfer paths to either the first or second horizontal transfer path. A method of manufacturing a charge coupled device in a first horizontal transfer path, comprising: (a) forming a first n-type region serving as the first horizontal transfer path on a semiconductor substrate surface; and (b) the first Forming a first insulating layer on one n-type region; and (c) an electrode for transferring charges on the first horizontal transfer path, wherein an opening is formed on the first insulating layer. The first electrode layer having a predetermined pattern in which the surface shape of the portion includes a tapered portion And (d) forming a well region having a surface shape including a tapered portion in the first horizontal transfer path by ion-implanting n-type impurities into the semiconductor substrate using the first electrode layer as a mask. And (e) a first predetermined region in which the first electrode layer is used as a part of a mask and an n-type impurity includes a tapered portion of a surface shape in the well region, and a first predetermined region in the well region And a step of ion-implanting the well region and the second predetermined region in the barrier region that extend over the boundary between the first horizontal transfer path and the shift gate in the vicinity of the boundary between the first horizontal transfer path and the shift gate. Is provided.
[0033]
The well region is formed by self-alignment by ion implantation using the first electrode layer as a mask. Further, by ion-implanting n-type impurities into a predetermined region in the well region using the first electrode layer as a mask, a high n-type impurity concentration region can be formed in the predetermined region by self-alignment. When the charge coupled device is applied to a two-stage horizontal transfer path in a solid-state image sensor, the charge transfer efficiency in the vertical direction can be improved by forming the high n-type impurity concentration region into a tapered shape.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1A shows a two-stage transfer path according to the first embodiment of the present invention, and shows a specific configuration of area 7 in FIG.
[0035]
A shift gate 12 is provided between the first horizontal transfer path 5a and the second horizontal transfer path 5b. By controlling the shift gate 12, the charge can be shifted from the first horizontal transfer path 5a to the second horizontal transfer path 5b.
[0036]
The horizontal transfer paths 5a and 5b are configured by setting the second well region W2, the second barrier region B2, the first well region W1, and the first barrier region B1 as a set, and repeatedly providing them in the horizontal direction. Is done. A drive signal Hφ1 is supplied to the first well region W1 and the first barrier region B1, and a drive signal Hφ2 is supplied to the second well region W2 and the second barrier region B2. The horizontal transfer paths 5a and 5b are two-phase driven by drive signals Hφ1 and Hφ2.
[0037]
The well regions W1 and W2 in the first horizontal transfer path 5a have a tapered shape that gradually expands toward the second horizontal transfer path 5b. On the other hand, the barrier regions B1 and B2 in the first horizontal transfer path 5a have a reverse taper shape that gradually narrows toward the second horizontal transfer path 5b. A vertical sectional view of FIG. 1A is the same as FIG.
[0038]
As shown in FIG. 6B, the well region W1 has a high potential from a narrow width (horizontal distance) to a wide width region (from the top to the bottom in the figure). (Potential is low). That is, by making the well region W1 tapered, a natural potential gradient can be generated in the vertical direction.
[0039]
Further, in the first well region W1, a hatched high impurity concentration region 41 is formed so as to straddle the first horizontal transfer path 5a and the shift gate 12. Similar to the surface shape of the first well region W1, the surface shape of the high impurity concentration region 41 has a tapered portion that gradually expands toward the second horizontal transfer path 5b, and is preferably triangular.
[0040]
FIG. 1B shows the electric field generated in the high impurity concentration region 41 by a broken line. The high impurity concentration region 41 generates a built-in potential due to a difference in impurity concentration at the boundary with the well region W1. The high impurity concentration region 41 has a higher potential (lower potential) as it goes inward from the boundary with the well region W1. By forming the high impurity concentration region 41 having the tapered portion, a natural potential gradient can be generated in the vertical direction.
[0041]
As shown in the potential waveform S2 of FIG. 4, the charges 11 are accumulated in the first well region W1 by the horizontal transfer. As shown in FIG. 1A, the charge 42 in the well region W1 moves vertically downward according to the potential gradient caused by the well region W1 having the tapered portion and the potential gradient caused by the high impurity concentration region 41 having the tapered portion. Then, by opening the shift gate 12, the charge 42 passes between the channel stop regions 33a and 33b and is transferred to the second horizontal transfer path 5b.
[0042]
As described above, the well region W1 is tapered, and the high impurity concentration region 41 having a tapered portion is provided, so that a natural steep potential gradient is generated and charges can be smoothly transferred in the vertical direction.
[0043]
The well regions W1 and W2 and the barrier regions B1 and B2 are not tapered and inversely tapered, but are rectangular as shown in FIG. 4 and the high impurity concentration region 41 having the tapered portion is provided. Also good. Even in this case, the potential gradient can be generated, but the potential gradient becomes gentler than that in the above case.
[0044]
Said horizontal transfer path can be manufactured by using the process shown to FIG. 5 (A)-(D). At this time, it is necessary to add a step of forming the high impurity concentration region 41 by providing a resist mask pattern so that a predetermined region is exposed and performing ion implantation into the substrate.
[0045]
However, with this method, it is difficult to increase the positional accuracy of the high impurity concentration region 41, and as shown in FIG. 7A, the high impurity concentration region 41 is formed in the barrier regions B1 and B2 adjacent to the well region W1. Easy to protrude (prone to misalignment). For example, the high impurity concentration region 41a is formed in the barrier region B1, and the high impurity concentration region 41b is formed in the barrier region B2. The protruding areas 41a and 41b cause the following adverse effects.
[0046]
FIG. 7B is a diagram showing the three-dimensional potential of the horizontal transfer path shown in FIG. In FIGS. 7A and 7B, the well regions W1 and W2 and the barrier regions B1 and B2 are indicated by rectangles for simplification of the drawing. FIG. 7B shows the potential state when the drive signal Hφ1 is 5V and the drive signal Hφ2 is 0V.
[0047]
Since the majority of the high impurity concentration region 41 having the tapered portion is formed in the well region W1, a vertical potential gradient is generated.
[0048]
A high impurity concentration region 41a is formed in the barrier region B1, and a high impurity concentration region 41b is formed in the barrier region B2. The high impurity concentration regions 41a and 41b have lower potentials than the others in the barrier regions B1 and B2, and become so-called potential pockets for storing charges. The potential pocket reduces charge transfer efficiency.
[0049]
Next, a method for manufacturing a horizontal transfer path (charge coupled device) for preventing the generation of potential pockets will be described with reference to FIGS.
[0050]
8A is a plan view of the Si substrate, and FIG. 8B is a cross-sectional view taken along the line AA of FIG. 8A. First, as shown in FIG. 8B, n-type impurities 53 are ion-implanted into the surface of the p-type Si region 51 to form an n-type Si region 52 on the surface of the p-type Si region 51.
[0051]
The n-type impurity 53 is, for example, P or As. In the case of P, the ion implantation conditions are, for example, a dose amount of 1 × 10 ¹¹ ~ 1x10 ¹² cm ^-2 The acceleration voltage is 10 to 50 keV.
[0052]
9A is a plan view of the substrate, and FIG. 9B is a cross-sectional view taken along the line AA of FIG. 9A. As shown in FIG. 9B, a p-type impurity 54 is ion-implanted into the surface of the n-type Si region 52, and a low impurity concentration n is implanted into the surface of the n-type Si region 52. ^- A type Si region 53 is formed.
[0053]
The p-type impurity 54 is, for example, B. The ion implantation conditions are, for example, a dose of 1 × 10 ¹¹ ~ 1x10 ¹² cm ^-2 The acceleration voltage is 10 to 50 keV. However, the p-type impurity 54 needs to be less than the n-type impurity 53 in FIG.
[0054]
FIG. 10A is a plan view of the substrate, and FIG. 10B is a cross-sectional view taken along the line AA in FIG. As shown in FIG. ^- SiO 2 is formed on the surface of the mold Si region 53 by the CVD method. ₂ A layer 55 is formed, and a first poly gate 56 having a predetermined pattern made of polycrystalline Si is formed thereon.
[0055]
The first poly gate 56 is formed in a predetermined pattern by photolithography and etching after depositing polycrystalline Si over the entire surface of the substrate by CVD. The first poly gate 56 corresponds to an electrode formed on the barrier regions B1 and B2.
[0056]
In FIG. 10A, SiO ₂ The area where the layer 55 is exposed is an area in which the well regions W1 and W2 are formed, and has a tapered shape that expands toward the second horizontal transfer path (downward in the figure). SiO ₂ In the area where the layer 55 is exposed, for example, the upper side L1 is 3.6 μm, the lower side L2 is 5.8 μm, and the height L3 is 7.5 μm.
[0057]
The area of the first poly gate 56 is only partly shown in the figure, but is an area where the barrier regions B1 and B2 are formed, and as it goes to the second horizontal transfer path as shown in FIG. It is a reverse taper shape that narrows (as it goes down in the figure).
[0058]
11A is a plan view of the substrate, and FIG. 11B is a cross-sectional view taken along the line AA in FIG. 11A. As shown in FIG. 11B, n-type impurities 58 are ion-implanted into the substrate using the first poly gate 56 as a mask. Under the window where the first poly gate 56 is not provided, an n-type Si region 57 is formed by self-alignment.
[0059]
The n-type Si region 57 is n ^- The n-type impurity concentration is higher than that of the type Si region 53. The n-type Si region 57 corresponds to the well regions W1 and W2, and n ^- The type Si region 53 corresponds to the barrier regions B1 and B2.
[0060]
The n-type impurity 58 is, for example, P or As. In the case of P, the ion implantation conditions are, for example, a dose amount of 1 × 10 ¹¹ ~ 1x10 ¹² cm ^-2 The acceleration voltage is 10 to 50 keV. However, n-type Si region 57 and n ^- The impurity concentration ratio of the type Si region 53 is, for example, 6: 1.
[0061]
12A is a plan view of the substrate, FIG. 12B is a cross-sectional view taken along the line AA of FIG. 12A, and FIG. 12C is a cross-sectional view of FIG. It is BB sectional drawing (vertical direction sectional drawing) of these. In order to form the high impurity concentration region 59 having the tapered portion, a resist mask 61 having a predetermined pattern is formed on the substrate. For easy understanding of the drawing, the display of the resist mask 61 is omitted in FIG.
[0062]
Next, n-type impurity 60 is ion-implanted into the substrate using resist mask 61 and first poly gate 56 as a mask. A high impurity concentration n having a tapered portion on the surface of the n-type Si region 57 under the window where the resist mask 61 and the first poly gate 56 are not provided. ⁺ A type Si region 59 is formed.
[0063]
n ⁺ Since the type Si region 59 is self-aligned using the resist mask 61 and the first poly gate 56 as a mask, it does not protrude from the n type Si region (well region) 57. That is, n ⁺ Type Si region 59 is n ^- It is possible to prevent the potential pocket regions 41a and 41b (FIGS. 7A and 7B) from being generated in the type Si region (barrier region) 53. n ⁺ The type Si region 59 is accommodated in the n-type Si region (well region) 57 using the first poly gate 56 as a mask, and has a shape in which both ends of the triangular shape are cut.
[0064]
The n-type impurity 60 is, for example, P or As. The ion implantation conditions are, for example, a dose of 1 × 10 ^Ten ~ 1x10 ¹² cm ^-2 The acceleration voltage is 10 to 50 keV. Where n ⁺ Type Si region 59 and n type Si region 57 and n ^- The impurity concentration ratio of the type Si region 53 is, for example, 1: 0.06: 0.01.
[0065]
13A is a plan view of the substrate, and FIG. 13B is a cross-sectional view taken along the line AA in FIG. 13A. Using the first poly gate 56 as a mask, SiO ₂ A part of the layer 55 is anisotropically etched, and then the entire surface of the substrate is SiO. ₂ The layer 62 is formed by a thermal oxidation method and a CVD method, and a second poly gate 63 having a predetermined pattern made of polycrystalline Si is formed thereon.
[0066]
The second poly gate 63 is formed in a predetermined pattern by photolithography and etching after depositing polycrystalline Si over the entire surface of the substrate by CVD. Second poly gate 63 is formed so as to cover an area where n-type Si region (well region) 57 is projected upward.
[0067]
The first poly gate 56 is n ^- The second poly gate 63 is an n-type Si region (well region) 57 and an n-type Si region (barrier region) 53. ⁺ This is a gate electrode for controlling the type Si region 59.
[0068]
The potential waveform S1 is a waveform when the potentials of the first and second poly gates 56 and 63 are 0V. n ^- The type Si region 53 has high potential and becomes barrier regions B1 and B2. n-type Si region 57 and n ⁺ The type Si region 59 has a low potential and becomes well regions W1 and W2.
[0069]
Thus, the horizontal transfer path is completed. N with taper ⁺ Since the type Si region 59 is self-aligned using the first poly gate 56 as a mask, it does not protrude from the n type Si region (well region) 57. Further, the above self-alignment can prevent the generation of potential pocket regions 41a and 41b shown in FIGS. 7A and 7B.
[0070]
FIG. 14 shows a two-stage horizontal transfer path according to the second embodiment of the present invention, and shows a specific configuration of area 7 in FIG. In the present embodiment, the generation of potential pockets due to misalignment of the high impurity concentration region can be prevented by providing the transfer path with the high impurity concentration region 71 including the triangular region 71a and the region 71b extending in the horizontal direction. it can. Details will be described below.
[0071]
The portions denoted by the same reference numerals as those in FIG. 1A are the same as described above. By making the well region W1 tapered, a natural potential gradient can be generated in the vertical direction.
[0072]
Further, the high impurity concentration region 71 is formed so as to straddle the first horizontal transfer path 5 a and the shift gate 12. The high impurity concentration region 71 includes a triangular region 71a and a region 71b extending in the horizontal direction.
[0073]
Similar to the shape of the first well region W1, the shape of the region 71a has a tapered portion that gradually expands toward the second horizontal transfer path 5b, and is preferably triangular.
[0074]
The region 71b is formed to be elongated in the horizontal direction so as to straddle the first horizontal transfer path 5a and the shift gate 12. The elongated region 71b extends over the well regions W1 and W2 and the barrier regions B1 and B2.
[0075]
FIG. 15 is a diagram showing the three-dimensional potential of the horizontal transfer path shown in FIG. For simplification of the drawing, the well regions W1 and W2 and the barrier regions B1 and B2 are indicated by rectangles. FIG. 15 shows the potential state when the drive signal Hφ1 is 5V and the drive signal Hφ2 is 0V.
[0076]
Since the high impurity concentration region 71a having a tapered portion is formed in the well region W1, a potential gradient is generated in the vertical direction. The elongated high impurity concentration region 71b has a low potential and serves as a potential side groove of the first transfer path 5a. The high impurity concentration region 71 b forms a potential side groove of the first horizontal transfer path 5 a and a potential side groove of the shift gate 12.
[0077]
The charge 73 moves in the lateral groove region 71b in the horizontal direction. Since the region 71b forms a potential side groove, generation of potential pocket regions 41a and 41b as shown in FIG. 7B can be prevented. The formation of the high impurity concentration region 71 does not require highly accurate alignment.
[0078]
As described above, in the first horizontal transfer path 5a, by providing a part of the region 71b serving as the potential side groove at the end portion on the second horizontal transfer path 5b side, misalignment is performed when the high impurity concentration region 71 is formed. Thus, it is possible to prevent the adverse effect of generating potential pockets.
[0079]
The first horizontal transfer path 5a can smoothly transfer charges in the vertical direction toward the second horizontal transfer path 5b without adversely affecting the charge transfer in the horizontal direction.
[0080]
Also in the second embodiment, the well regions W1, W2 and the barrier regions B1, B2 may be rectangular as shown in FIG.
[0081]
Said horizontal transfer path can be manufactured using the process shown in FIG. 5 or FIGS. However, it is necessary to form the high impurity concentration region 71 in the above shape.
[0082]
According to the first and second embodiments, it is possible to form a natural potential gradient in the vertical direction by forming a high impurity concentration region having a tapered portion in the well region W1 of the first horizontal transfer path 5a. it can. The first horizontal transfer path 5a can smoothly transfer charges in the vertical direction toward the second horizontal transfer path 5b without adversely affecting the charge transfer in the horizontal direction.
[0083]
Further, according to the second embodiment, by providing a part of the region 71b serving as the potential side groove at the end portion on the second horizontal transfer path 5b side in the first horizontal transfer path 5a, the misalignment in the process. Generation of potential pockets can be prevented.
[0084]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0085]
【The invention's effect】
As described above, according to the present invention, n-type impurities are ion-implanted into a predetermined region in the well region using the first electrode layer as a mask, so that a region having a high n-type impurity concentration is self-aligned to the predetermined region. Can be formed. A region having a high n-type impurity concentration can be formed with high precision alignment.
[0086]
When the charge coupled device is applied to a two-stage horizontal transfer path in a solid-state imaging device, the charge transfer efficiency in the vertical direction can be improved if the high n-type impurity concentration region is tapered. The first horizontal transfer path can transfer charges in the horizontal direction, and can also transfer charges smoothly in the vertical direction toward the second horizontal transfer path.
[Brief description of the drawings]
FIG. 1A is a plan view of a two-stage horizontal transfer path according to a first embodiment of the present invention, and FIG. 1B is a diagram showing an electric field generated in a high impurity concentration region.
FIG. 2 is a plan view of a solid-state image sensor.
FIG. 3 is a plan view and a potential waveform diagram of a two-stage horizontal transfer path.
FIG. 4 is a plan view and a potential waveform diagram of a first horizontal transfer path.
FIGS. 5A to 5D are process diagrams showing a method of manufacturing a horizontal transfer path (charge coupled device) according to the prior art.
6A is a plan view of a two-stage horizontal transfer path according to the prior art, and FIG. 1B is a diagram showing an electric field generated in a well region.
FIG. 7A is a plan view of a first horizontal transfer path, and FIG. 7B is a three-dimensional potential diagram of the first horizontal transfer path.
FIG. 8 shows a manufacturing process of a horizontal transfer path (charge coupled device). 8A is a plan view of the substrate, and FIG. 8B is a cross-sectional view taken along the line AA in FIG. 8A.
FIG. 9 shows a step that follows FIG. 9A is a plan view of the substrate, and FIG. 9B is a cross-sectional view taken along the line AA of FIG. 9A.
10 shows a step that follows FIG. 9. FIG. FIG. 10A is a plan view of the substrate, and FIG. 10B is a cross-sectional view taken along the line AA in FIG.
FIG. 11 shows a step that follows FIG. 11A is a plan view of the substrate, and FIG. 11B is a cross-sectional view taken along the line AA in FIG. 11A.
12 shows a step that follows FIG. 11. FIG. 12A is a plan view of the substrate, FIG. 12B is a cross-sectional view taken along the line AA in FIG. 12A, and FIG. 12C is a cross-sectional view taken along the line BB in FIG. It is.
13 shows a step that follows FIG. 12. FIG. 13A is a plan view of the substrate, and FIG. 13B is a cross-sectional view taken along the line AA in FIG. 13A.
FIG. 14 is a plan view of a two-stage horizontal transfer path according to a second embodiment of the present invention.
15 is a three-dimensional potential diagram of the two-stage horizontal transfer path shown in FIG.
16 is a cross-sectional view taken along the line AA in FIG.
[Explanation of symbols]
1 Solid-state image sensor
2 Pixel part
3 Photodiode
4 Vertical transfer path
5a First horizontal transfer path
5b Second horizontal transfer path
6a First amplifier
6b Second amplifier
11 Charge
12 Shift gate
13 Charge
W1, W2 well region
B1, B2 Barrier area
21 p-type Si region
22 n-type Si region
23 n-type impurities
24 SiO ₂ layer
25 First polygate
26 p-type Si region
27 p-type impurities
28 SiO ₂ layer
29 Second polygate
31 charge
33 channel stop
41 High impurity concentration region
42 charge
51 p-type Si region
52 n-type Si region
53 n-type impurities
54 p-type impurities
55 SiO ₂ layer
56 First polygate
57 n-type Si region
58 n-type impurities
59 n ⁺ Type Si region
60 n-type impurities
61 resist
62 SiO ₂ layer
63 second poly gate
71 High impurity concentration region
73 charge

Claims (4)

A well region and a barrier region are repeatedly provided in the horizontal direction, receive charges from a plurality of vertical transfer paths and transfer charges in the horizontal direction, and the first transfer paths from the plurality of vertical transfer paths. A charge is selectively transferred from the plurality of vertical transfer paths to the first or second horizontal transfer path by receiving a charge via the horizontal transfer path and transferring the charge in the horizontal direction. A solid-state imaging device having a shift gate for supplying a charge coupled device in the first horizontal transfer path,
(A) forming a first n-type region serving as the first horizontal transfer path on a semiconductor substrate surface;
(B) forming a first insulating layer on the first n-type region;
(C) An electrode for transferring charges on the first horizontal transfer path, wherein the first electrode layer having a predetermined pattern in which the surface shape of the opening includes a tapered portion is formed on the first insulating layer. Forming, and
And (d) step of the first of the n-type impurity electrode layer as a mask to ion-implanted into the semiconductor substrate first surface shape in the horizontal transfer path forming said well region includes a tapered portion,
(E) Using the first electrode layer as a part of a mask, an n-type impurity is continuously connected to a first predetermined region whose surface shape in the well region includes a tapered portion, and a first predetermined region in the well region. and method of manufacturing the charge-coupled device comprising the steps of ion implantation and a second predetermined region of the first of said well regions and the barrier region spanning both in the vicinity of the boundary of the horizontal transfer path and the shift gate.   In the step (a), the first n-type impurity concentration is lower than that of the second n-type region by ion-implanting p-type impurities into the second n-type region formed on the surface of the semiconductor substrate. The method of manufacturing a charge-coupled device according to claim 1, wherein the n-type region is formed on the surface of the second n-type region. And (f) forming a second insulating layer so as to cover the first electrode layer; and (g) a second region projected onto the well region on the second insulating layer. The method for producing a charge coupled device according to claim 1, further comprising a step of forming an electrode layer. 4. The method of manufacturing a charge coupled device according to claim 1, wherein the semiconductor substrate is Si, the first insulating layer is SiO2, and the first electrode layer is polycrystalline Si.

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