JP2000162635A5 - - Google Patents
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- JP2000162635A5 JP2000162635A5 JP1999025009A JP2500999A JP2000162635A5 JP 2000162635 A5 JP2000162635 A5 JP 2000162635A5 JP 1999025009 A JP1999025009 A JP 1999025009A JP 2500999 A JP2500999 A JP 2500999A JP 2000162635 A5 JP2000162635 A5 JP 2000162635A5
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- film
- light shielding
- insulating film
- electro
- substrate
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- 239000010408 film Substances 0.000 claims description 181
- 239000000758 substrate Substances 0.000 claims description 53
- 239000011229 interlayer Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 230000000875 corresponding Effects 0.000 claims description 13
- 239000003566 sealing material Substances 0.000 claims description 10
- 239000002356 single layer Substances 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005755 formation reaction Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000011324 bead Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000003365 glass fiber Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 230000003287 optical Effects 0.000 claims 1
- 238000001039 wet etching Methods 0.000 description 5
- 239000011651 chromium Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical class [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
Description
【００１７】
【課題を解決するための手段】
本発明の電気光学装置は上記課題を解決するために、一対の基板間に電気光学物質が封入され、該基板の該電気光学物質に面する側に相交差して配列された複数のデータ線及び複数の走査線と、前記基板を相互に接着するギャップ材混入のシール材と、前記シール材の形成領域において、前記データ線及び走査線の少なくとも一方の延設方向に配置された複数の引き出し配線と、前記基板と前記引き出し配線との間に配置された凹状に窪んだ領域を有する層間絶縁膜とを備えており、前記複数の引き出し配線の各々は、前記シール材の形成領域において前記層間絶縁膜の凹状に窪んだ領域に形成されていることを特徴とする。[0017]
[Means for Solving the Problems]
According to the electro-optical device of the present invention, in order to solve the above problems, an electro-optical material is enclosed between a pair of substrates, and a plurality of data lines arranged crosswise on the side of the substrate facing the electro-optical material A plurality of scan lines, a seal material mixed with a gap material for bonding the substrates to one another, and a plurality of lead wirings arranged in the extending direction of at least one of the data lines and the scan lines in the formation region of the seal material. And an interlayer insulating film having a concavely recessed region disposed between the substrate and the lead-out wiring, and each of the plurality of lead-out wirings is the interlayer insulating in a formation region of the seal material. It is characterized in that it is formed in a recessed area of the membrane.
【００１８】
本発明の電気光学装置によれば、一対の基板は相互に接着されており、シール材に混入されたギャップ材により、基板間のギャップは制御されている。従って、データ線及び走査線によりマトリクス駆動される所定層厚の電気光学物質を備えた、例えばＴＦＴ駆動、ＴＦＤ駆動等のアクティブマトリクス駆動方式の電気光学装置或いはパッシブマトリクス駆動方式の電気光学装置として構成される。ここで、層間絶縁膜は、シール領域において引き出し配線に対向する部分が凹状に窪んで形成されている。従って、データ線や走査線が形成された基板側のシール領域においてシール材に接する層間絶縁膜等の最上層の表面（以下、単に“シール領域の表面”という）において引き出し配線上に形成される当該引き出し配線の厚みによる凸状の突出の高さは、当該凹状に窪んだ部分の深さに応じて低められることになる。即ち、シール領域の表面における平坦化が図られる。従って、平坦化されたシール領域上でシール材に混入されたギャップ材を介してかかる応力は面上に一様に分散される。従って、前述の図２４及び図２５に示したような引き出し配線が断線したりショートしたりする可能性は大きく低減される。また、このシール領域の表面における高さの差を実質的に零にせずに、多少なりとも小さくすれば、同様の作用により、引き出し配線が断線したりショートしたりする可能性は多少なりとも低減される。[0018]
According to the electro-optical device of the present invention, the pair of substrates are adhered to each other, and the gap between the substrates is controlled by the gap material mixed in the sealing material. Therefore, it is configured as an electro-optical device of active matrix drive type such as TFT drive, TFD drive, or an electro-optical device of passive matrix drive type provided with an electro-optical material of a predetermined layer thickness driven in matrix by data lines and scanning lines. Be done. Here, in the seal region, the interlayer insulating film is formed so as to be recessed in a portion facing the lead-out wiring. Therefore, it is formed on the lead-out wiring on the surface of the uppermost layer such as interlayer insulating film in contact with the seal material in the seal region on the substrate side where the data lines and scan lines are formed (hereinafter simply referred to as "surface of seal region") The height of the convex protrusion due to the thickness of the lead-out wiring is reduced according to the depth of the concave portion. That is, planarization on the surface of the seal area is achieved. Therefore, the stress applied through the gap material mixed in the seal material on the flattened seal area is uniformly distributed on the surface. Therefore, the possibility of disconnection or shorting of the lead-out lines as shown in FIGS. 24 and 25 is greatly reduced. In addition, if the height difference on the surface of the seal area is made substantially zero without reducing it somewhat, the possibility that the lead wiring will be disconnected or short-circuited is reduced to some extent by the same action. Be done.
【００２０】
また、本発明は、前記複数のデータ線及び複数の走査線は、前記基板のうちの一方に設けられており、該一方の基板上に、前記各データ線及び前記各走査線に接続された薄膜トランジスタと、 該薄膜トランジスタに接続された画素電極と、前記薄膜トランジスタの少なくともチャネル領域を前記一方の基板の側から見て各々重なる位置に設けられた遮光膜と、前記走査線に平行に配設され前記画素電極に所定容量を各々付与する容量線とを更に備えており、前記層間絶縁膜は、前記一方の基板上の前記遮光膜が形成されている領域においては前記遮光膜上に且つ前記遮光膜が形成されていない領域においては前記一方の基板上に設けられており、前記薄膜トランジスタ、前記データ線、前記走査線及び前記容量線のうち少なくとも一つに対向する部分が前記基板のうちの他方の側から見て凹状に窪んで形成された第１層間絶縁膜を含み、該第１層間絶縁膜は、前記シール領域において前記引き出し配線に対向する部分が凹状に窪んで形成されると良い。[0020]
Further, according to the present invention, the plurality of data lines and the plurality of scanning lines are provided on one of the substrates, and are connected to the respective data lines and the respective scanning lines on the one substrate. A thin film transistor, a pixel electrode connected to the thin film transistor, a light shielding film provided so as to overlap at least a channel region of the thin film transistor when viewed from the side of the one substrate; The interlayer insulating film is further provided on the light shielding film in a region where the light shielding film is formed on the one of the substrates, and the interlayer insulating film further includes a capacitance line for applying a predetermined capacitance to the pixel electrode. Is provided on the one substrate in a region where the first and second electrodes are not formed, and faces at least one of the thin film transistor, the data line, the scanning line, and the capacitance line. Portion includes a first interlayer insulating film formed in a recessed shape when viewed from the other side of the substrate, and the first interlayer insulating film is formed such that a portion facing the lead wiring in the seal region is recessed It is good if it is formed in depression.
【００２１】
この構成によれば、遮光膜は、複数のＴＦＴの少なくともチャネル領域を一方の基板の側から見て覆う位置において一方の基板に設けられている。従って、一方の基板の側からの戻り光等が当該チャネル領域に入射する事態を未然に防ぐことができ、光電流の発生によりＴＦＴの特性が劣化することはない。そして、第１層間絶縁膜は、一方の基板及び遮光膜の上方に設けられている。従って、遮光膜からＴＦＴ等を電気的に絶縁し得ると共に遮光膜がＴＦＴ等を汚染する事態を未然に防げる。ここで特に、第１層間絶縁膜は、ＴＦＴ、データ線、走査線及び容量線のうち少なくとも一つに対向する部分が他方の基板の側から見て凹状に窪んで形成されているので、従来のように第１層間絶縁膜を平らに形成してその上にこれらのＴＦＴ等を形成する場合と比較すると、凹状に窪んだ部分の深さに応じて、これらのＴＦＴ等が形成された領域と形成されていない領域との合計膜厚の差が減少し、画素部における平坦化が促進される。即ち、従来のように、画素領域における平坦化膜のスピンコート等による塗布、平坦化された絶縁膜の形成等の工程を、省略又は簡略化できる。[0021]
According to this configuration, the light shielding film is provided on one of the plurality of TFTs at a position covering the channel region of the plurality of TFTs as viewed from the side of the one substrate. Therefore, it is possible to prevent in advance the return light and the like from the side of one substrate from entering the channel region, and the generation of the photocurrent does not deteriorate the characteristics of the TFT. The first interlayer insulating film is provided above one of the substrates and the light shielding film. Therefore, the TFT and the like can be electrically isolated from the light shielding film, and the light shielding film can be prevented from contaminating the TFT and the like. Here, in particular, since the first interlayer insulating film is formed so as to have a portion facing at least one of the TFT, the data line, the scanning line, and the capacitance line recessed from the side of the other substrate, As compared with the case where the first interlayer insulating film is formed flat and the TFTs and the like are formed thereon, the region where the TFTs and the like are formed according to the depth of the recessed portion. The difference in the total film thickness between the and the non-formed regions is reduced, and planarization in the pixel portion is promoted. That is, as in the prior art, the steps such as spin coating or the like of the planarizing film in the pixel region and the formation of the planarized insulating film can be omitted or simplified.
【００２２】
また、本発明は、前記シール領域において、前記データ線の延設方向に配置されたデータ線側引き出し配線をなす金属膜に対しては、前記走査線をなす導電性のポリシリコン膜及び導電性の前記遮光膜の少なくとも一方が前記層間絶縁膜を介して積層形成されていると共に、前記走査線の延設方向に配置された走査線側引き出し配線をなす前記ポリシリコン膜に対しては、前記金属膜及び前記遮光膜の少なくとも一方が前記層間絶縁膜を介して積層形成されていると良い。[0022]
Further, according to the present invention, the conductive polysilicon film forming the scanning line and the conductivity of the metal film forming the data line side lead-out wire arranged in the extending direction of the data line in the seal region With respect to the polysilicon film forming the scanning line side lead-out wiring, at least one of the light shielding films is formed to be laminated via the interlayer insulating film and is disposed in the extending direction of the scanning lines. It is preferable that at least one of the metal film and the light shielding film be laminated via the interlayer insulating film.
【００２３】
この構成によれば、シール領域において、前記データ線の延設方向に配置されたデータ線側引き出し配線は、例えばＡｌ（アルミニウム）等の金属膜から構成されており、走査線の延設方向に配置された走査線側引き出し配線は、導電性のポリシリコン膜から構成されており、遮光膜は、Ｗ（タングステン）等の高融点金属膜から構成されている。ここで、シール領域において、データ線側引き出し配線は、一般に画像表示領域のデータ線の延設方向に沿った上下の辺から引き出されており、走査線側引き出し配線は、一般に画像表示領域の走査線の延設方向に沿った左右の辺から引き出されている。従って、仮にデータ線側引き出し配線をなす金属膜と、走査線側引き出し配線をなすポリシリコン膜との厚みが相異なれば、画像表示領域の上下の辺におけるシール領域の表面の高さと左右の辺におけるシール領域の表面の高さとが相異なるので、シール材の全体に混入されるギャップ材による基板間ギャップの制御が不安定なものとなってしまう。そこで、本発明では、データ線側引き出し配線に対しては、走査線側をなす導電性のポリシリコン膜を積層し、他方、走査線側引き出し配線に対しては、データ線をなす金属膜を積層する。すると、画像表示領域の上下の辺におけるシール領域の表面の高さと左右の辺におけるシール領域の表面の高さとは一致するので、シール材の全体に混入されるギャップ材による基板間ギャップの制御が安定なものとなる。[0023]
According to this configuration, in the seal region, the data line side lead-out interconnections arranged in the extending direction of the data lines are made of a metal film such as Al (aluminum), for example, in the extending direction of the scanning lines. The arranged scanning line side lead-out wiring is made of a conductive polysilicon film, and the light shielding film is made of a high melting point metal film such as W (tungsten). Here, in the seal area, the data line side lead out lines are generally drawn out from the upper and lower sides along the extending direction of the data lines of the image display area, and the scanning line side lead out lines are generally scanning the image display area. It is drawn from the left and right sides along the extension direction of the line. Therefore, if the thicknesses of the metal film forming the data line side lead wire and the polysilicon film forming the scan line side lead wire are different, the height of the surface of the seal area and the left and right sides in the upper and lower sides of the image display area Since the height of the surface of the seal region in the above is different, the control of the gap between the substrates by the gap material mixed in the whole of the seal material becomes unstable. Therefore, in the present invention, a conductive polysilicon film forming the scanning line side is stacked on the data line side lead wiring, while a metal film forming the data line is formed on the scanning line side lead wiring. Stack. Then, since the height of the surface of the seal area on the upper and lower sides of the image display area matches the height of the surface of the seal area on the left and right sides, the control of the inter-substrate gap by the gap material mixed in the entire seal material It will be stable.
【００２５】
また、本発明は、前記データ線の延設方向に配置された前記データ線側引き出し配線をなす前記金属膜は、積層形成された前記ポリシリコン膜及び前記遮光膜の少なくとも一方とコンタクトホールを介して電気接続されており、前記データ線引き出し配線の少なくとも一部は、前記金属膜と共に前記ポリシリコン膜及び前記遮光膜の少なくとも一方からなる冗長構造を有すると良い。[0025]
Further, according to the present invention, the metal film forming the data line side lead-out wire arranged in the extending direction of the data line is formed via a contact hole with at least one of the polysilicon film and the light shielding film formed by lamination. Preferably, at least a portion of the data line lead-out wiring has a redundant structure including at least one of the polysilicon film and the light shielding film together with the metal film.
【００２６】
この構成によれば、データ線側引き出し配線をなす金属膜に積層形成された導電性のポリシリコン膜及び遮光膜の少なくとも一方は、コンタクトホールを介してデータ線側引き出し配線に電気接続されており、データ線は、積層された２つ又は３つの導電膜からなる冗長構造を有する。従って、例えば、シール領域下においてギャップ材による応力を受けて配線が断線しても、或いは、基板に垂直な方向に一つの導電膜が層間絶縁膜を破って他の導電膜にショートしても配線不良となる可能性は非常に低くなる。[0026]
According to this configuration, at least one of the conductive polysilicon film and the light shielding film laminated on the metal film forming the data line side lead wire is electrically connected to the data line side lead wire through the contact hole. The data lines have a redundant structure consisting of two or three stacked conductive films. Therefore, for example, even if the wiring is disconnected due to stress from the gap material under the seal region, or even if one conductive film breaks the interlayer insulating film and shorts to another conductive film in the direction perpendicular to the substrate. The possibility of wiring failure is very low.
【００２７】
また、本発明は、前記走査線側引き出し配線をなす前記ポリシリコン膜は、積層形成された前記金属膜及び前記導電性の遮光膜の少なくとも一方とコンタクトホールを介して電気接続されており、前記走査線側引き出し配線の少なくとも一部は、前記ポリシリコン膜と共に前記金属膜及び前記遮光膜の少なくとも一方からなる冗長構造を有すると良い。[0027]
Further, in the present invention, the polysilicon film forming the scanning line side lead-out wiring is electrically connected to at least one of the laminated metal film and the conductive light shielding film through a contact hole. At least a part of the scanning line side lead-out line may have a redundant structure including at least one of the metal film and the light shielding film together with the polysilicon film.
【００２８】
この構成によれば、走査線側引き出し配線をなす導電性のポリシリコン膜に積層形成された金属膜及び前記遮光膜の少なくとも一方は、コンタクトホールを介して走査線側引き出し配線に電気接続されており、走査線は、積層された２つ又は３つの導電膜からなる冗長構造を有する。[0028]
According to this configuration, at least one of the metal film laminated on the conductive polysilicon film forming the scanning line side lead wiring and the light shielding film is electrically connected to the scanning line side lead wiring through the contact hole. The scan line has a redundant structure consisting of two or three conductive films stacked.
【００２９】
また、本発明は、前記データ線側引き出し配線をなす前記金属膜に対して積層形成された前記ポリシリコン膜及び前記遮光膜の少なくとも一方は、前記シール領域において前記基板を介して入射される光がシール材に透過可能なように網目状又はストライプ状の平面パターンを備えており、前記走査線側引き出し配線をなす前記ポリシリコン膜に対して積層形成された前記金属膜及び前記遮光膜の少なくとも一方は、前記シール領域において前記基板を介して入射される光がシール材に透過可能なように網目状又はストライプ状の平面パターンを備えると良い。[0029]
Further, according to the present invention, at least one of the polysilicon film and the light shielding film laminated and formed on the metal film forming the data line side lead-out light is incident through the substrate in the seal region. Is provided with a mesh-like or stripe-like plane pattern so as to be permeable to the sealing material, and at least at least the metal film and the light shielding film laminated on the polysilicon film forming the scanning line side lead-out wiring It is preferable that one of them has a reticulated or striped planar pattern so that light incident through the substrate in the seal area can be transmitted to the seal material.
【００３０】
この構成によれば、シール領域において、データ線側引き出し配線に対して積層形成された導電性のポリシリコン膜及び遮光膜の少なくとも一方は、網目状又はストライプ状の平面パターンを備えているので、当該電気光学装置の製造工程において、光硬化性樹脂等の光硬化性材料からなるシール材を用いた場合に、基板を介して光を入射すれば、この積層構造における網目の間或いはストライプの間を通ってシール材に光を照射することが出来る。従って、光硬化性樹脂等からなるシール材を良好に光硬化させることが出来る。[0030]
According to this configuration, at least one of the conductive polysilicon film and the light shielding film laminated and formed on the data line side lead-out wiring in the seal region has the mesh pattern or the stripe pattern plane pattern. When a sealing material made of a photocurable material such as a photocurable resin is used in the manufacturing process of the electro-optical device, if light is incident through the substrate, it is between the meshes in the laminated structure or between the stripes. The light can be emitted to the sealing material through the Therefore, the sealing material made of a photocurable resin or the like can be satisfactorily photocured.
【００３１】
また、本発明は、前記遮光膜は、定電位源に接続されていると良い。[0031]
Further, in the present invention, it is preferable that the light shielding film is connected to a constant potential source.
【００３２】
この構成によれば、遮光膜は定電位源に接続されているので、遮光膜は定電位とされる。従って、遮光膜に対向配置されるＴＦＴに対し遮光膜の電位変動が悪影響を及ぼすことはない。[0032]
According to this configuration, since the light shielding film is connected to the constant potential source, the light shielding film has a constant potential. Therefore, the potential fluctuation of the light shielding film does not adversely affect the TFT disposed opposite to the light shielding film.
【００３３】
また、本発明は、前記層間絶縁膜は、単層から構成されていると良い。[0033]
Further, in the present invention, the interlayer insulating film is preferably formed of a single layer.
【００３４】
この構成によれば、層間絶縁膜を単層から構成すればよいので、従来の場合と比較しても層の数を増加させる必要が無く、凹状に窪んだ部分とそうでない部分との膜厚を制御すれば、当該層間絶縁膜が得られる。[0034]
According to this configuration, since the interlayer insulating film may be formed of a single layer, there is no need to increase the number of layers as compared with the conventional case, and the film thickness of the recessed portion and the non-recessed portion Is controlled to obtain the interlayer insulating film.
【００３５】
また、本発明は、前記層間絶縁膜は、単層部分と多層部分とから構成されており、前記単層部分が前記凹状に窪んだ部分とされており、前記多層部分が前記凹状に窪んでいない部分とされていると良い。[0035]
Further, according to the present invention, the interlayer insulating film is composed of a single layer portion and a multilayer portion, the single layer portion is a recessed portion in the concave shape, and the multilayer portion is recessed in the concave shape. It is good if it is not a part.
【００３６】
この構成によれば、単層部分が凹状に窪んだ部分とされているので、凹状に窪んだ部分における層間絶縁膜の膜厚を、単層部分の膜厚として、比較的容易にして確実且つ高精度に制御できる。従って、この凹状に窪んだ部分における層間絶縁膜の膜厚を非常に薄くすることも可能となる。[0036]
According to this configuration, since the single layer portion is a recessed portion, the film thickness of the interlayer insulating film in the recessed portion is made relatively easy and reliable as the thickness of the single layer portion. It can control with high precision. Therefore, it is also possible to make the film thickness of the interlayer insulating film very thin in the concave portion.
【００３７】
また、本発明は、前記層間絶縁膜は、酸化シリコン膜又は窒化シリコン膜から構成されていると良い。[0037]
Further, in the present invention, the interlayer insulating film is preferably made of a silicon oxide film or a silicon nitride film.
【００３８】
この構成によれば、酸化シリコン膜又は窒化シリコン膜からなる層間絶縁膜により、遮光膜からＴＦＴ等を電気的に絶縁できると共に遮光膜からの汚染を防止できる。しかも、このように構成された層間絶縁膜は、ＴＦＴの下地膜に適している。[0038]
According to this configuration, the TFT and the like can be electrically insulated from the light shielding film and contamination from the light shielding film can be prevented by the interlayer insulating film made of the silicon oxide film or the silicon nitride film. Moreover, the interlayer insulating film configured in this way is suitable for the base film of the TFT.
【００３９】
また、本発明は、前記遮光膜は、Ｔｉ（チタン）、Ｃｒ（クロム）、Ｗ（タングステン）、Ｔａ（タンタル）、Ｍｏ（モリブデン）及びＰｂ（鉛）のうちの少なくとも一つを含むと良い。[0039]
Further, according to the present invention, preferably, the light shielding film contains at least one of Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum) and Pb (lead). .
【００４０】
この構成によれば、遮光膜は、不透明な高融点金属であるＴｉ、Ｃｒ、Ｗ、Ｔａ、Ｍｏ及びＰｂのうちの少なくとも一つを含む、例えば、金属単体、合金、金属シリサイド等から構成されるため、ＴＦＴアレイ基板上の遮光膜形成工程の後に行われるＴＦＴ形成工程における高温処理により、遮光膜が破壊されたり溶融しないようにできる。[0040]
According to this configuration, the light shielding film is made of, for example, a single metal, an alloy, a metal silicide or the like containing at least one of opaque high melting point metals Ti, Cr, W, Ta, Mo and Pb. Therefore, the light shielding film can be prevented from being broken or melted by the high temperature treatment in the TFT forming process performed after the light shielding film forming process on the TFT array substrate.
【００４１】
また、本発明は、前記ギャップ材は、前記基板間のギャップに対応する所定径を持つグラスファイバ及びガラスビーズのいずれか一方からなると良い。[0041]
Further, in the present invention, the gap material is preferably made of either one of glass fiber and glass bead having a predetermined diameter corresponding to the gap between the substrates.
【００４２】
この構成によれば、グラスファイバ或いはガラスビーズがギャップ材としてシール材中に混入されているので、シール領域の表面に対して、線状領域や点状領域の応力集中が起きる。しかし、シール領域の表面における引き出し配線の厚みに起因した凸状の突出は、層間絶縁膜の凹状に窪んだ部分の深さに応じて平坦化されている。このため、当該応力集中により引き出し配線が断線したりショートしたりする可能性は低減される。[0042]
According to this configuration, since the glass fiber or the glass bead is mixed in the sealing material as the gap material, stress concentration occurs in the linear area or the point-like area on the surface of the sealing area. However, the convex protrusion resulting from the thickness of the lead-out wiring on the surface of the seal region is flattened in accordance with the depth of the concave portion of the interlayer insulating film. For this reason, the possibility that the lead wiring is disconnected or shorted due to the concentration of stress is reduced.
【００４３】
また、本発明は、前記層間絶縁膜の凹状に窪んだ側壁部分はテーパ状に形成されていると良い。[0043]
Further, in the present invention, the recessed side wall portion of the interlayer insulating film is preferably formed in a tapered shape.
【００４４】
この構成によれば、層間絶縁膜の凹状に窪んだ側壁部分はテーパ状に形成されているので、電気光学装置の製造工程において、この凹状に窪んだ部分内に引き出し配線をフォトリソグラフィ工程、エッチング工程等により形成し、更にその上に絶縁膜や導電膜等の他の膜を積層する際に、この凹状に窪んだ部分内に残る電極残り等のエッチング後の残留物を低減することが出来る。このため、所定パターンの引き出し配線を的確に凹状に窪んだ部分内に形成することできる。[0044]
According to this configuration, since the concavely recessed side wall portion of the interlayer insulating film is formed in a tapered shape, in the manufacturing process of the electro-optical device, the lead-out wiring is photolithographically processed and etched in the concavely recessed portion When other layers such as an insulating film and a conductive film are formed by a process or the like, and residual films after etching such as electrode remaining remaining in the recessed portion can be reduced. . For this reason, it is possible to form the lead wiring of the predetermined pattern in the concave portion properly.
【００４５】
また、本発明の電気光学装置の製造方法は、前記一方の基板上の所定領域に前記遮光膜を形成する工程と、前記一方の基板及び遮光膜上に絶縁膜を形成する工程と、該絶縁膜に前記凹状に窪んだ部分に対応するレジストパターンをフォトリソグラフィで形成する工程と、該レジストパターンを介して所定時間のエッチングを行い前記凹状に窪んだ部分を形成する工程とを備えると良い。[0045]
Further, in the method of manufacturing an electro-optical device according to the present invention, a step of forming the light shielding film on a predetermined region on the one substrate, a step of forming an insulating film on the one substrate and the light shielding film, and the insulation The method may include the steps of: forming a resist pattern corresponding to the recessed portion in the film by photolithography; and forming the recessed portion by etching for a predetermined time through the resist pattern.
【００４６】
この構成によれば、先ず、一方の基板上の所定領域に遮光膜が形成され、一方の基板及びこの遮光膜上に絶縁膜が形成される。次に、該絶縁膜に凹状に窪んだ部分に対応するレジストパターンが、フォトリソグラフィで形成され、その後、ドライエッチング又はウエットエッチングが、このレジストパターンを介して所定時間だけ行われて、凹状に窪んだ部分が形成される。従って、ドライエッチング又はウエットエッチングの時間管理により、凹状に窪んだ部分の深さや膜厚を制御できる。特にウエットエッチングを行えば、凹状に窪んだ側壁部分にテーパ形状を設けることが出来るので便利である。[0046]
According to this configuration, first, the light shielding film is formed in a predetermined region on one of the substrates, and the insulating film is formed on the one substrate and the light shielding film. Next, a resist pattern corresponding to the recessed portion in the insulating film is formed by photolithography, and then dry etching or wet etching is performed for a predetermined time through the resist pattern to form a recessed portion. Ellipses are formed. Therefore, by controlling the time of dry etching or wet etching, it is possible to control the depth and film thickness of the recessed portion. In particular, if wet etching is performed, a tapered shape can be provided on the recessed side wall portion, which is convenient.
【００４７】
また、本発明の電気光学装置の製造方法は、前記一方の基板上の所定領域に前記遮光膜を形成する工程と、前記一方の基板及び遮光膜上に第１絶縁膜を形成する工程と、該第１絶縁膜に前記凹状に窪んだ部分に対応するレジストパターンをフォトリソグラフィで形成する工程と、該レジストパターンを介してエッチングを行い前記凹状に窪んだ部分に対応する前記第１絶縁膜を除去する工程と、前記一方の基板及び第１絶縁膜上に第２絶縁膜を形成する工程とを備えると良い。[0047]
In the method of manufacturing an electro-optical device according to the present invention, a step of forming the light shielding film on a predetermined area on the one substrate, a step of forming a first insulating film on the one substrate and the light shielding film, A step of forming a resist pattern corresponding to the recessed portion in the first insulating film by photolithography and etching through the resist pattern to form the first insulating film corresponding to the recessed portion It is preferable to include a removing step and a step of forming a second insulating film on the one substrate and the first insulating film.
【００４８】
この構成によれば、先ず、一方の基板上の所定領域に遮光膜が形成され、一方の基板及びこの遮光膜上に第１絶縁膜が形成される。次に、この第１絶縁膜に、凹状に窪んだ部分に対応するレジストパターンが、フォトリソグラフィで形成され、その後、ドライエッチング又はウエットエッチングが、このレジストパターンを介して行われて、凹状に窪んだ部分に対応する第１絶縁膜が除去される。その後、一方の基板及びこの第１絶縁膜上に第２絶縁膜が形成される。この結果、凹状に窪んだ部分における第１層間絶縁膜の膜厚を、第２絶縁膜の膜厚の管理により、比較的容易にして確実且つ高精度に制御できる。この場合にもウエットエッチングを行えば、凹状に窪んだ部分にテーパを設けることが出来るので便利である。[0048]
According to this configuration, first, the light shielding film is formed in a predetermined region on one of the substrates, and the first insulating film is formed on the one substrate and the light shielding film. Next, a resist pattern corresponding to the recessed portion is formed on the first insulating film by photolithography, and then dry etching or wet etching is performed via the resist pattern to recess the recessed portion. The first insulating film corresponding to the overhang portion is removed. Thereafter, a second insulating film is formed on one of the substrates and the first insulating film. As a result, the film thickness of the first interlayer insulating film in the recessed portion can be relatively easily and reliably controlled with high accuracy by managing the film thickness of the second insulating film. Also in this case, if wet etching is performed, it is convenient because the tapered portion can be provided with a taper.
【００４９】
また、本発明の電子機器は、上記電気光学装置を備えると良い。[0049]
Further, the electronic apparatus of the present invention preferably includes the above-described electro-optical device.
【００５０】
この構成によれば、電子機器は、上述した本願発明の電気光学装置を備えており、配線不良が低減され、基板間のギャップ制御が精度良く行われた信頼性の高い電気光学装置により高品位の画像表示が可能となる。[0050]
According to this configuration, the electronic apparatus includes the above-described electro-optical device according to the present invention, reduces wiring defects, and achieves high quality by a highly reliable electro-optical device in which gap control between substrates is accurately performed. Image display is possible.
Claims (15)
前記複数の引き出し配線の各々は、前記シール材の形成領域において前記層間絶縁膜の凹状に窪んだ領域に形成されていることを特徴とする電気光学装置。An electro-optical material is enclosed between a pair of substrates, and a gap material for mutually bonding the plurality of data lines and the plurality of scanning lines arranged to intersect with each other on the side of the substrate facing the electro-optical material. A sealing material mixed, a plurality of lead-out lines arranged in the extending direction of at least one of the data line and the scanning line in the formation area of the seal material, and arranged between the substrate and the lead-out line And an interlayer insulating film having a recessed region.
Each of the plurality of lead-out lines is formed in a recessed area of the interlayer insulating film in the area where the sealing material is formed.
前記各データ線及び前記各走査線に対応して設けられた薄膜トランジスタと、
該薄膜トランジスタに対応して設けられた画素電極と、
前記薄膜トランジスタの少なくともチャネル領域を前記一方の基板の側から見て各々重なる位置に設けられた遮光膜と、
前記走査線に平行に配設され前記画素電極に所定容量を付与する容量線と
を更に備えており、
前記層間絶縁膜は、前記一方の基板上の前記遮光膜が形成されている領域においては前記遮光膜上に且つ前記遮光膜が形成されていない領域においては前記一方の基板上に設けられており、前記薄膜トランジスタ、前記データ線、前記走査線及び前記容量線のうち少なくとも一つに対向する部分が前記基板のうちの他方の側から見て凹状に窪んで形成された第１層間絶縁膜を含み、該第１層間絶縁膜は、前記シール領域において前記引き出し配線に対向する部分が凹状に窪んで形成されたことを特徴とする請求項１に記載の電気光学装置。The plurality of data lines and the plurality of scan lines are provided on one of the substrates, and on the one substrate,
Thin film transistors provided corresponding to the respective data lines and the respective scanning lines;
A pixel electrode provided corresponding to the thin film transistor;
A light shielding film provided so as to overlap each other when at least a channel region of the thin film transistor is viewed from the side of the one substrate;
And a capacitance line disposed parallel to the scanning line and providing a predetermined capacitance to the pixel electrode.
The interlayer insulating film is provided on the light shielding film in a region where the light shielding film is formed on the one substrate and on the one substrate in a region where the light shielding film is not formed. A portion of the thin film transistor, the data line, the scanning line, and the capacitance line facing at least one of the first and second interlayer insulating films formed in a recessed shape when viewed from the other side of the substrate; 2. The electro-optical device according to claim 1, wherein the first interlayer insulating film is formed such that a portion facing the lead-out wiring in the seal region is recessed in a concave shape.
前記単層部分が前記凹状に窪んだ部分とされており、前記多層部分が前記凹状に窪んでいない部分とされていることを特徴とする請求項１から６のいずれか一項に記載の電気光学装置。The interlayer insulating film is composed of a single layer part and a multilayer part,
The electricity according to any one of claims 1 to 6, wherein the single-layer portion is the concave portion and the multilayer portion is the non-concave portion. Optical device.
前記一方の基板上の所定領域に前記遮光膜を形成する工程と、
前記一方の基板及び遮光膜上に絶縁膜を形成する工程と、
該絶縁膜に前記凹状に窪んだ部分に対応するレジストパターンをフォトリソグラフィで形成する工程と、
該レジストパターンを介して所定時間のエッチングを行い前記凹状に窪んだ部分を形成する工程と
を備えたことを特徴とする電気光学装置の製造方法。9. A method of manufacturing an electro-optical device according to claim 8.
Forming the light shielding film in a predetermined area on the one substrate;
Forming an insulating film on the one substrate and the light shielding film;
Forming a resist pattern corresponding to the recessed portion in the insulating film by photolithography;
And (e) etching for a predetermined time through the resist pattern to form the recessed portion.
前記一方の基板上の所定領域に前記遮光膜を形成する工程と、
前記一方の基板及び遮光膜上に第１絶縁膜を形成する工程と、
該第１絶縁膜に前記凹状に窪んだ部分に対応するレジストパターンをフォトリソグラフィで形成する工程と、
該レジストパターンを介してエッチングを行い前記凹状に窪んだ部分に対応する前記第１絶縁膜を除去する工程と、
前記一方の基板及び第１絶縁膜上に第２絶縁膜を形成する工程と
を備えたことを特徴とする電気光学装置の製造方法。10. A method of manufacturing an electro-optical device according to claim 9.
Forming the light shielding film in a predetermined area on the one substrate;
Forming a first insulating film on the one substrate and the light shielding film;
Forming a resist pattern corresponding to the recessed portion in the first insulating film by photolithography;
Etching through the resist pattern to remove the first insulating film corresponding to the recessed portion;
And a step of forming a second insulating film on the one substrate and the first insulating film.
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| JP2500999A JP3731368B2 (en) | 1998-01-30 | 1999-02-02 | ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
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| JP2000298 | 1998-01-30 | ||
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| JP10-272119 | 1998-09-25 | ||
| JP27211998 | 1998-09-25 | ||
| JP2500999A JP3731368B2 (en) | 1998-01-30 | 1999-02-02 | ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
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| JP2003207361A Division JP3664170B2 (en) | 1998-01-30 | 2003-08-12 | Electro-optical device and electronic apparatus |
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| KR100500147B1 (en) | 2002-12-31 | 2005-07-07 | 엘지.필립스 엘시디 주식회사 | The organic electro-luminescence device and method for fabricating of the same |
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| JP2006030502A (en) * | 2004-07-15 | 2006-02-02 | Sony Corp | Display apparatus and method of manufacturing display apparatus |
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