JP2006030502A - Display apparatus and method of manufacturing display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus wherein parasitic capacitance formed between a driving side substrate and a counter side substrate is reduced, waveform distortion or delay of signals caused by the parasitic capacitance is eliminated, and load on an external driving IC can be reduced, and to provide its manufacturing method. <P>SOLUTION: When the display apparatus has a wiring structure wherein signal lines 33 (33R, 33G, 33B, 33P) are wired in an area on a glass substrate 41 (driving side substrate) opposing to a second glass substrate (counter side substrate) 42, a recessed part 45 is formed on an oxide film 43 on the glass substrate 41 and the signal lines 33 are wired in the recessed part 45. Thus, the distance between a transparent electrode 44 and the signal lines 33 is increased, and the parasitic capacitance generated between the transparent electrode 44 and the signal lines 33 is reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a method for manufacturing the display device, and more particularly to a display device configured using a pair of substrates arranged to face each other and a method for manufacturing the display device.

  As a display device configured by using a pair of substrates disposed to face each other, for example, between a driving side substrate on which pixel transistors and the like are formed and a facing side substrate that is disposed to face the driving side substrate with a predetermined gap. There is known a liquid crystal display device in which a liquid crystal material is sealed in a gap between these substrates.

  Further, as a liquid crystal display device, a vertical drive circuit that sequentially selects each pixel of a pixel array unit in which pixels including liquid crystal cells are arranged in a matrix in units of rows, or a pixel in a row selected by the vertical drive circuit. On the other hand, there is a so-called drive circuit integrated type in which peripheral drive circuits such as a horizontal drive circuit for writing signals are integrally formed on the same substrate as the pixel array portion.

  In this drive circuit integrated liquid crystal display device, since various circuits are arranged in the peripheral portion of the pixel array unit, the substrate on which the pads are arranged when the pads for taking in video signals and the like from outside are arranged on the substrate. Will be limited. For this reason, a video signal or the like captured through a pad arranged on a certain side of the substrate is transmitted to a horizontal drive circuit by a long signal line wired around the periphery of the pixel array unit (see, for example, Patent Document 1). ).

  In this type of liquid crystal display device, conventionally, as shown in FIG. 8, signal lines 101 wired around the pixel array portion are formed on an oxide film 103 on a driving substrate, for example, a glass substrate 102. The configuration in which the organic film 104 is formed on the signal line 101 and the oxide film 103 has been adopted. 8A is a plan view of a part of the signal line 101, and FIG. 8B is a cross-sectional view taken along line XY in FIG. 8A. In FIG. 8B, a liquid crystal layer 107 is formed between the glass substrate 106 and the glass substrate 102 which are opposite substrates on which the transparent electrode 105 is formed.

Japanese Patent Laid-Open No. 11-7047

  Here, since the gap between the driving side substrate and the counter side electrode is very narrow, a parasitic capacitance is formed between the signal line 101 on the driving side substrate and the transparent electrode 105 on the counter side substrate. When the flat area of the signal line 101 is increased by increasing the distance of the 101, the parasitic capacitance tends to increase. As a result, this parasitic capacitance causes problems such as waveform rounding and delay in the video signal transmitted through the signal line 101, or an increase in the load on the driving IC that supplies the video signal from the outside of the substrate. Will occur.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the parasitic capacitance formed between the driving-side substrate and the counter-side substrate and to generate a signal caused by the parasitic capacitance. It is an object of the present invention to provide a display device that eliminates the waveform rounding and delay, and that can reduce the load on the external driving IC, and a method for manufacturing the same.

  The display device according to the present invention includes a pair of substrates disposed opposite to each other, an insulating film formed on one of the pair of substrates and having a recess in a region where the pair of substrates are opposed, And a signal line wired in the recess of the insulating film.

  In the display device having the above-described structure, the signal line is wired in the recess formed in the insulating film on one substrate, so that the other substrate and the signal line are compared with the case where the signal line is wired on the insulating film. Therefore, the parasitic capacitance formed between the other substrate and the signal line can be reduced by the increase in the distance.

  According to the present invention, since the parasitic capacitance formed between the other substrate and the signal line can be reduced, it is possible to eliminate signal rounding and delay caused by the parasitic capacitance, and to load the external drive IC. Can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of a configuration of a display device to which the present invention is applied, for example, a liquid crystal display device using a liquid crystal cell as an electro-optical element.

  As shown in FIG. 1, the liquid crystal display device according to this application example includes a pixel array unit 11, a vertical drive circuit 12, a horizontal drive circuit 13, a precharge circuit 14, and the like. The peripheral drive circuit of the precharge circuit 14 is formed on the same substrate 15 as the pixel array unit 11.

  In the pixel array unit 11, pixels 20 including pixel transistors and the like are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (drive side substrate). The scanning lines 16-1 to 16-m are wired for each row in the array, and the signal lines 17-1 to 17-n are wired for each column. The first glass substrate is disposed so as to face the second glass substrate (opposite side substrate) with a predetermined gap and is bonded through a sealant (not shown). Then, the liquid crystal material is sealed in a region inside the position of the sealant.

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel (pixel circuit) 20. As apparent from FIG. 2, the pixel 20 includes a pixel transistor, for example, a TFT (Thin Film Transistor) 21, a liquid crystal cell 22 in which the pixel electrode is connected to the drain electrode of the TFT 21, and one of the drain electrode of the TFT 21. And a storage capacitor 23 to which the electrodes are connected. Here, the liquid crystal cell 22 means a liquid crystal capacitance generated between a pixel electrode and a counter electrode formed opposite to the pixel electrode.

  The TFT 21 has a gate electrode connected to the scanning line 15 (15-1 to 15-m) and a source electrode connected to the signal line 16 (16-1 to 16-n). For example, the counter electrode of the liquid crystal cell 22 and the other electrode of the storage capacitor 23 are connected to the common line 18 in common for each pixel. A common voltage (counter electrode voltage) Vcom is applied to the common electrode of the liquid crystal cell 22 via the common line 18.

  The vertical drive circuit 12 includes a shift register, a buffer circuit, and the like, and selects each pixel 20 of the pixel array unit 12 in units of rows. Here, the vertical drive circuit 12 is disposed only on one side of the pixel array unit 11, but it is also possible to employ a configuration in which the vertical drive circuit 12 is disposed on both the left and right sides of the pixel array unit 11.

  The horizontal drive circuit 13 includes a shift register, a sampling switch (horizontal switch), and the like, and writes a video signal in units of pixels to each pixel 20 in a row selected by the vertical drive circuit 12. In this example, the dot sequential driving for writing the video signal to each pixel 20 in the selected row is given as an example. However, the line sequential driving for writing the video signal to each pixel 20 in the selected row. It is also possible to adopt.

  The precharge circuit 14 is configured by a precharge switch or the like disposed for each pixel 20 in the horizontal direction of the pixel array unit 11, and prior to video signal writing by the horizontal drive circuit 13 for each pixel 20 of the pixel array unit 11. Then, a precharge signal of a predetermined level is written to the signal lines 17-1 to 17-n.

  A driving IC (driving circuit) 31 for driving the present liquid crystal display device is provided outside the substrate 15. The drive IC 31 outputs R (red), G (green), and B (blue) video signals, the precharge signal, and the like. These signals are taken into the substrate 15 through a pad portion 32 provided on one side of the substrate 15, for example, the side opposite to the horizontal drive circuit 13 across the pixel array unit 11.

  Video signals R, G, and B captured through the pad unit 32 are transmitted to the horizontal drive circuit 13 through three signal lines 33R, 33G, and 33B wired along the periphery of the pixel array unit 11. The precharge signal P taken in through the pad unit 32 is transmitted to the precharge circuit 14 through the signal line 33P.

  The present invention is characterized by the wiring structure of these signal lines 33R, 33G, 33B, and 33P. A specific example of the wiring structure will be described below.

Example 1
3A and 3B are diagrams illustrating a wiring structure of the signal lines 33 (33R, 33G, 33B, and 33P) according to the first embodiment. FIG. 3A is a plan view of a part of the wiring, and FIG. It is sectional drawing along a XY line.

  3A and 3B, a first glass substrate (driving side substrate) 41 and a second glass substrate (opposing side substrate) 42 are disposed to face each other. An oxide film 43 is formed as an insulating film on the opposing surface of the first glass substrate 41, and a transparent electrode 44 such as ITO (Indium Tin Oxide) is formed on the opposing surface of the second glass substrate 42. . In the oxide film 43, a recess 45 is formed along the route of the signal line 33, and preferably the bottom surface thereof is the substrate surface of the glass substrate 41.

  The signal line 33 is wired on the bottom surface of the recess 45, in this example, on the substrate surface of the glass substrate 41 in the recess 45. For example, Ti or Al is used as the signal line 33. On the oxide film 43 after wiring of the signal line 33, an organic film 46 which is a planarizing film is formed. Then, a liquid crystal layer 47 is formed by sealing a liquid crystal material in a gap between the first glass substrate 41 and the second glass substrate 42.

  As described above, the wiring structure in which the signal lines 33 (33R, 33G, 33B, 33P) are wired in the region facing the second glass substrate (opposing substrate) 42 on the glass substrate 41 (driving substrate). In the case of adopting the method, a recess 45 is formed in the oxide film 43 on the glass substrate 41, and the signal line 33 is wired in the recess 45. The distance (interval) d between the transparent electrode 44 on the substrate 42 and the signal line 33 is increased.

  In particular, by wiring the signal line 33 on the substrate surface of the glass substrate 41 in the recess 45, the distance d between the transparent electrode 44 on the glass substrate 42 and the signal line 33 is increased on the oxide film 43. Compared with the case where the wiring 33 is wired, the oxide film 43 is enlarged by the film thickness.

  Here, the parasitic capacitance C formed between the transparent electrode 44 and the signal line 33 will be considered. Assuming that the area of the region where the transparent electrode 44 and the signal line 33 face each other is A and the dielectric constant is kε, the parasitic capacitance C is a value proportional to kε · A / d.

  As is apparent from this, even when the signal line 33 (33R, 33G, 33B, 33P) is long and the plane area of the signal line 33 is large, the transparent electrode 44 and the signal line 33 Since the parasitic capacitance C formed between the transparent electrode 44 and the signal line 33 can be reduced, the waveform rounding and delay of the signal due to the parasitic capacitance C can be eliminated. In addition, the load on the external drive IC 31 can be reduced.

  In the first embodiment, preferably, a recess 45 whose bottom surface is the substrate surface of the glass substrate 41 is formed in the oxide film 43, and the signal line 33 is formed on the substrate surface (bottom surface) of the glass substrate 41 in the recess 45. However, it is also possible to form a concave portion 45 in which the substrate surface of the glass substrate 41 is not the bottom surface, that is, the oxide film 43 itself is the bottom surface, and the signal line 33 is wired in the concave portion 45. is there.

  Even when this configuration is adopted, the distance d between the transparent electrode 44 and the signal line 33 can be increased as compared with the case where the signal line 33 is wired on the oxide film 43. The parasitic capacitance C formed between the two can be reduced. However, the distance d between the transparent electrode 44 and the signal line 33 is maximized, that is, the film thickness of the oxide film 43 when the signal line 33 is wired in the recess 45 whose bottom surface is the substrate surface of the glass substrate 41. It is preferable because it can be enlarged only.

(Example 2)
4A and 4B are diagrams illustrating the wiring structure of the signal lines 33 (33R, 33G, 33B, and 33P) according to the second embodiment, in which FIG. It is sectional drawing along the XY line of A). 4, parts that are the same as those in FIG. 3 are given the same reference numerals.

  4 (A) and 4 (B), a concave portion 45 whose bottom surface is preferably the substrate surface of the glass substrate 41 is formed in the oxide film 43 on the glass substrate 41, and the signal line 33 is wired in the concave portion 45. The wiring structure is the same as the wiring structure according to the first embodiment.

  In the second embodiment, in addition to this wiring structure, the second wiring 48 is formed along the signal line 33 on a layer different from the signal line 33, specifically, on the organic film 46, and the signal line 33 and the second line A configuration is adopted in which both of the wirings 48 are electrically connected via respective contact holes 49A and 49B at the start and end. For example, ITO or Ag is used as the second wiring 48.

  In this way, the second wiring 48 is formed along the signal line 33 in a layer different from the signal line 33, and the signal line 33 and the second wiring 48 are electrically connected to each other, thereby electrically connecting the signal line 33 and the signal line 33. The combined wiring resistance between the starting end and the terminal end of the second wiring 48 is less than each wiring resistance of the signal line 33 and the second wiring 48, and the wiring resistance of the signal line 33 can be reduced. The resulting waveform rounding and delay of the signal can be further reduced, and the load on the external drive IC 31 can be further reduced.

Example 3
FIG. 5 is a diagram illustrating a wiring structure of the signal lines 33 (33R, 33G, 33B, and 33P) according to the third embodiment. FIG. 5A is a plan view of a part of the wiring, and FIG. It is sectional drawing along a XY line. In FIG. 5, the same parts as those in FIG.

  In the third embodiment, a recess 45 whose bottom surface is the substrate surface of the glass substrate 41 is formed by removing the oxide film 46 in the preferred form of the first embodiment, and on the substrate surface of the glass substrate 41 in the recess 45. In the case of adopting a wiring structure for wiring the signal line 33, first, the third wiring 50 is formed on the substrate surface of the glass substrate 41 in the recess 45, and the signal line 33 is wired on the third wiring 50. The signal line 33 is stacked. As the third wiring 50, for example, molybdenum or the like is used.

  In this manner, the signal line 33 is not directly wired on the substrate surface of the glass substrate 41 in the recess 45, but the third wiring 50 is interposed between the substrate surface and the signal line 33, whereby the glass substrate 41 Even if there is damage such as a scratch or chipping on the substrate surface, the influence on the signal line 33 due to the damage is mitigated by the third wiring 50, and therefore, from disconnection caused by damage to the substrate surface of the glass substrate 41. The signal line 33 can be protected.

  In the third embodiment, the third wiring 50 is provided exclusively for protecting the signal line 33 from damage to the substrate surface of the glass substrate 41. However, the second wiring 48 provided in the second embodiment is not provided in the second wiring 48. As in the case of the three wirings 50, it is formed or laminated on the lower layer portion of the signal line 33, thereby reducing both the wiring resistance of the signal line 33 and protecting the signal line 33 from damage to the substrate surface of the glass substrate 41. Can be obtained at the same time.

[Production method]
Next, taking the case of the wiring structure according to the first embodiment as an example, an example of the manufacturing method will be described with reference to the process diagrams of FIGS.

  First, an oxide film 52 is formed on a substrate 51 such as a glass substrate by CVD or a thermal oxidation method as a gate insulating film for a TFT or the like formed for each pixel 20 in the pixel array unit 11 (step 1). The oxide film 52 has a structure in which, for example, a silicon oxide film or a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked, and the thickness thereof is 50 nm to 300 nm.

  Next, an interlayer insulating film 53 is formed directly on the oxide film 52 by CVD or the like (step 2). The interlayer insulating film 53 is a film for insulating between a transistor such as a TFT and the wiring. The thickness of the interlayer insulating film 53 is about 100 nm to 1 μm, and is usually about 500 nm. In FIG. 3 showing the wiring structure according to the first embodiment, the interlayer insulating film 53 is not shown.

  Next, a resist 54 is applied so as to cover the interlayer insulating film 53, and patterned by exposure and development (step 3). This patterning needs to be wide enough to form the recess 55 in a later step. Normally, a pattern drawn on CAD is printed on the mask, but the width of the recess 55 is preferably the wiring width of the signal line 33 +2.5 μm, and the applicable range is the wiring width of the signal line 33+ (1. 0 μm to 3.0 μm).

  Here, when the wiring width of the signal line 33 is set to the width of the concave portion 55 of 1.0 μm, it is the limit of the effect that the wiring does not go over the trench due to misalignment in the photolithography process, and is taken out from the outside. When the wiring width is set to the width of the trench 10 of 3.0 μm, there is a limit to the effect that the insulating film 16 does not lose flatness after coating. Therefore, the width of the recess 55 is preferably set.

  Thereafter, a part of the interlayer insulating film 33 and the oxide film 52 is etched to form the recess 55 (step 4). In this case, the interlayer insulating film 33 and the oxide film 52 are made to have a speed of 50 to 200 nm / min. Etch with.

  The step 3 of removing the interlayer insulating film 33 and the oxide film 52 is performed as the same step as the step of forming the contact hole of the different interlayer wiring. Thereby, the recessed part 55 can be formed, without increasing the process for forming the recessed part 55. FIG.

  After forming the recess 55, a metal film 33a is formed on the entire surface by a method such as sputtering (step 5). The metal film 33a is made of, for example, Al, Al—Si, Al—Si—Cu, Cu or the like.

  Thereafter, the signal line 33 is patterned by applying, exposing and developing a resist 56 (step 6). Further, anisotropic etching is performed under the following etching conditions. The etching gas is a chlorine-based gas, and Cl2 and BCl3 are used, and an appropriate high frequency power is applied to perform etching by plasma etching.

  Thereafter, the resist 56 is removed to complete the signal line 33 (step 7), and then an organic film 57 for protection, planarization, etc. is formed (step 8).

  By removing the interlayer insulating film 33 and the oxide film 52 in the same process as the formation of the contact hole of the different interlayer wiring by the above-described series of processes, the recess 55 (the recess 45 in FIG. 3 is not increased). Can be formed).

  Further, not only the wiring structure according to the first embodiment but also the wiring structure according to the second and third embodiments can be formed by creating and changing the mask pattern. That is, the above wiring structure can be formed without requiring a new process compared to the conventional manufacturing process.

  In the above-described embodiment, the signal lines 33 are described by taking the signal lines 33R, 33G, and 33B that transmit R, G, and B video signals and the signal line 33P that transmits the precharge signal as examples. The present invention is not limited to the above-described signal lines, and can be applied to all signal lines that are wired on the one substrate of a pair of substrates arranged opposite to each other and in a region where the pair of substrates are opposed to each other.

  In the above embodiment, the case where the present invention is applied to a liquid crystal display device in which liquid crystal is sealed between a pair of substrates arranged opposite to each other has been described as an example. However, the present invention is not limited thereto, and The present invention can be applied to all display devices in which signal lines are wired on one substrate of a pair of substrates disposed and in a region where the pair of substrates are opposed to each other.

It is a block diagram which shows the outline of a structure of the liquid crystal display device with which this invention is applied. It is a circuit diagram which shows an example of the circuit structure of a pixel. 2A and 2B are diagrams illustrating a wiring structure of signal lines according to the first embodiment, where FIG. 3A is a plan view of a part of the wiring, and FIG. 3B is a cross-sectional view taken along line XY in FIG. FIG. 6 is a diagram illustrating a wiring structure of signal lines according to a second embodiment, where (A) is a plan view of a starting end portion and a terminating portion of the wiring, and (B) is a cross-sectional view taken along line XY in (A). . It is a figure which shows the wiring structure of the signal line which concerns on Example 3, (A) is a top view of a part with wiring, (B) is sectional drawing along the XY line of (A). It is process drawing (the 1) which shows an example of the manufacturing method of this invention. It is process drawing (the 2) which shows an example of the manufacturing method of this invention. It is a figure which shows the wiring structure of the signal wire | line concerning a prior art example, (A) is a top view of a part with wiring, (B) is sectional drawing along the XY line of (A).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel array part, 12 ... Vertical drive circuit, 13 ... Horizontal drive circuit, 14 ... Precharge circuit, 20 ... Pixel, 21 ... TFT (thin film transistor), 22 ... Liquid crystal cell, 23 ... Retention capacity, 31 ... Drive IC, 33 (33R, 33G, 33B, 33P) ... Signal line, 41,42 ... Glass substrate, 43 ... Oxide film, 44 ... Transparent electrode, 45 ... Recess, 46 ... Organic film, 47 ... Liquid crystal layer (liquid crystal material)

Claims (6)

A pair of opposed substrates;
An insulating film formed on one substrate of the pair of substrates and having a recess in a region facing the pair of substrates;
And a signal line wired in the recess of the insulating film. The display device according to claim 1, further comprising a second wiring that is wired along the signal line and is electrically connected to the signal line at a start end and a termination end. The display device according to claim 1, wherein a bottom surface of the recess is the one substrate surface. Having a third wiring wired on the one substrate surface in the recess,
The display device according to claim 3, wherein the signal line is formed on the third wiring. The display device according to claim 4, wherein the third wiring is electrically connected to the signal line at a start end and a termination end. A method of manufacturing a display device in which a signal line is wired on one substrate of a pair of substrates disposed opposite to each other and in a region where the pair of substrates are opposed to each other,
A part of the region of the insulating film formed on the one substrate is deleted in the same process as the formation of the contact hole of the different interlayer wiring, and a recess is formed in the insulating film,
Thereafter, the signal line is formed in the recess. A method of manufacturing a display device, comprising:

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