JP3718334B2 - Manufacturing method of semiconductor device and manufacturing method of substrate for liquid crystal panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device such as a thin film transistor (hereinafter simply referred to as a TFT) formed on a glass substrate, and in particular, recovers the properties of the substrate surface damaged by heat treatment or CVD treatment. And a technique for removing impurities and residues attached to the surface. Furthermore, the present invention relates to a semiconductor device, a liquid crystal panel substrate using the semiconductor device, and a liquid crystal panel.
[0002]
[Prior art]
In a conventional semiconductor device manufacturing method, for example, a TFT manufacturing method, the gate electrode 2a is formed as follows. That is, first, after depositing polysilicon, amorphous silicon or the like on the substrate 10, patterning is performed to form an active layer 1a to be a source / drain / channel, and second, a surface of the active layer 1a is formed. A gate insulating film 12 is formed by thermal oxidation or the like, and thirdly, a conductive layer is subsequently deposited and then patterned to form a gate electrode 2a as shown in FIG. 2 (5). The
[0003]
[Problems to be solved by the invention]
By the way, if the substrate 10 on which the TFT active layer 1a is formed is left for a long period of time for some reason, a crystallized product is deposited on the surface of the substrate 10, and there is a problem in that it adversely affects the subsequent process.
[0004]
Considering this cause, it is thought that this is due to the following reasons. First, since CVD or the like is used to deposit the polysilicon layer 1 on the surface of the substrate 10, some damage occurs on the surface of the substrate 10. Second, due to this damage, even if the surface of the substrate 10 is cleaned after the TFT active layer 1a is formed, the cleaning solution or the like cannot be completely removed. Thirdly, this residue is thought to precipitate crystallized substances as a result of adsorbing hydrocarbons in the air.
[0005]
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to deposit a silicon layer on an insulating substrate like a TFT and form the substrate in a predetermined pattern. An object of the present invention is to provide a semiconductor manufacturing method, a semiconductor device, a liquid crystal panel substrate using this element, and a liquid crystal panel using this substrate, which do not adversely affect subsequent processes even if left for a period of time.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, in the present invention, a first step of forming a second layer of polysilicon serving as an active layer of a semiconductor device on the insulating first layer by a CVD method;
In a method of manufacturing a semiconductor device having at least a second step of forming the second layer in a predetermined island pattern,
In the second step, the unnecessary portion of the second layer formed by the first step is etched, and the first layer exposed by the etching of the unnecessary portion is damaged by the CVD method. At the same time, the surface portion subjected to the etching is etched by reactive ion etching using CHF ₃ gas and SF ₆ gas.
In order to solve the above-described problem, in the present invention, the semiconductor device is a thin film transistor connected to a plurality of scanning lines and a plurality of data lines and formed corresponding to each pixel. The layer 1 is an insulating substrate.
[0007]
Usually, CVD, sputtering, or the like is used for depositing the layer, so that the surface of the first layer is damaged to some extent. However, according to the present invention, since the surface of the first layer is etched, the damaged portion is removed, and the original properties of the first layer can be extracted. In addition, accompanying this etching, impurities attached to the surface of the first layer and residues left during cleaning are also removed.
[0008]
The method for manufacturing a substrate for a liquid crystal panel of the present invention includes a step of depositing a polysilicon layer serving as an active layer of a thin film transistor on an insulating substrate by a CVD method,
Step of simultaneously performing island-shaped patterning of the polysilicon layer and light etching of the exposed portion damaged by the CVD method on the insulating substrate by reactive ion etching using CHF ₃ gas and SF ₆ gas When,
Forming a gate insulating film so as to cover the patterned polysilicon layer;
Forming a gate electrode on the gate insulating film. According to the present invention, as the gate insulating film is etched, the exposed surface of the substrate is also etched, so that impurities and the like are removed, and adverse effects on the substrate can be prevented.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0010]
<Embodiment>
In the present embodiment, a polysilicon TFT for driving each pixel of an active matrix liquid crystal display device is used as a semiconductor device. FIG. 1A shows one pixel in a liquid crystal panel substrate to which the TFT is applied. FIG. FIG. 1B is a cross-sectional view showing the structure of the TFT along the line AA in FIG.
[0011]
First, in FIG. 1A, reference numeral 1a denotes a first polysilicon layer, which constitutes an active layer (source / drain / channel region) of a TFT. A scanning line 2a is a gate electrode in the case of a TFT. Reference numeral 3a denotes a data line, which supplies a voltage to be applied to the source region of the TFT arranged so as to cross the scanning line 2a. Here, the scanning line 2a is formed of a second polysilicon layer, and the data line 3a is formed of a conductive layer such as an aluminum layer.
[0012]
Further, the contact hole 4 is provided to connect the pixel electrode 6a made of an ITO (Indium-Tin Oxide) film and the drain region (or source region) of the TFT in the polysilicon layer 1, and the contact hole 5 is , Provided to connect the data line 3a and the source region of the TFT in the polysilicon layer 1a.
[0013]
Next, in FIG.1 (b), the board | substrate 10 is comprised with insulating substrates, such as a glass substrate (for example, non-alkali board | substrate) and a quartz substrate. The gate insulating film 12 is formed on the surface of the polysilicon layer 1 serving as an active layer of the TFT by performing a thermal oxidation process or the like. The first interlayer insulating film 13 and the second interlayer insulating film 15 are each composed of a SiO ₂ film (NSG film), a BPSG film (silicate glass film containing boron and phosphorus), and the like, as will be described later. It is formed by.
[0014]
A manufacturing process of the TFT having such a configuration will be described with reference to FIGS.
[0015]
First, in the step (1), the polysilicon layer 1 is deposited on the upper surface of the substrate 10 to a thickness of 500 to 2000 angstrom, preferably less than 1000 angstrom, for example, by a low pressure CVD method.
[0016]
Next, in step (2), the polysilicon layer 1 deposited on the substrate 10 is patterned by etching that reacts with polysilicon and the material of the substrate 10 to form an island-shaped active layer 1a in the TFT. Then, the exposed surface of the substrate 10 is slightly etched. That is, in this step, when an unnecessary portion of the polysilicon layer 1 is removed, the exposed substrate 10 surface is also slightly etched. Here, for the etching in the step (2), for example, the following RIE (reactive ion etching) is effective. That is, when the RIE conditions are gas pressure: 1600 [m torr], CHF ₃ : 5 [sccm], SF ₆ : 15 [sccm], He: 80 [sccm], and power: 250 [W] The etching selectivity is 1: 1 between the polysilicon layer 1 and the substrate 10, and the etching rate is 2000 angstroms per minute.
[0017]
Therefore, if the etching process time under this condition is set to 30 [seconds] and the thickness of the polysilicon layer 1 deposited in the step (1) is set to a preferable thickness of less than 1000 angstroms, the polysilicon layer 1a is not required. It can be seen that the portion is removed and the exposed surface of the substrate 10 is also etched in a small amount. For this reason, the surface of the substrate 10 is slightly etched to remove damaged portions, impurities, residues, and the like.
[0018]
As a result, the surface portion of the substrate 10 damaged by the step (1) is removed, and the inherent properties of the substrate 10 can be extracted. Furthermore, as a result of light etching of the substrate 10, impurities attached to the surface thereof and residues left at the time of cleaning are also removed, so that the inconvenience that crystallized substances are deposited is also eliminated. In addition, these effects can be achieved without adding a new process.
[0019]
In the step (3), the surface of the active layer 1a is thermally oxidized to form the gate insulating film 12 on the surface of the active layer 1a. By this step, the active layer 1a finally has a thickness of 300 to 1500 angstrom, preferably 350 to 450 angstrom, and the gate insulating film 12 has a thickness of about 600 to 1500 angstrom.
[0020]
Here, impurities (for example, phosphorous) are added to the extending portion 1b (see FIG. 1A) that extends upward along the data line 3a of the polysilicon layer constituting the active layer 1a to form a storage capacitor. ) At an appropriate dose (for example, 3 × 10 ¹⁴ [atms / cm ² ]) to lower the resistance of the polysilicon layer in that portion. The lower limit of the dose is determined from the viewpoint of securing the conductivity necessary for forming the storage capacity of the polysilicon layer, and the upper limit is determined from the viewpoint of suppressing the deterioration of the gate oxide film.
[0021]
Then, in the step (4), a low resistance polysilicon layer 2 to be a gate electrode and a scanning line is deposited on the gate insulating film 12 and the substrate 10 in the TFT by a low pressure CVD method or the like. Here, as a material of the gate electrode, in addition to polysilicon, a refractory metal such as Mo, Ta, Ti, W, or a metal silicide thereof can be used.
[0022]
Turning now to FIG. 3, in step (5), the polysilicon layer 2 is patterned by chemical dry etching to form a gate electrode 2a including a TFT scanning line.
[0023]
In the step (6), impurities (for example, phosphorus) ions are implanted using the gate electrode 2a as a mask to form high-concentration semiconductor regions to be self-aligned source and drain regions in the active layer 1a of the TFT. The source / drain regions are lightly doped with impurities (phosphorus) at a dose of 1 × 10 ^{13 to} 3 × 10 ¹³ [atms / cm ² ] to form a low concentration region, and then the width of the gate electrode. A wider mask layer is formed on the scanning line 2a, and further, an impurity (phosphorus) is implanted at a dose of 1 × 10 ^{15 to} 3 × 10 ¹⁵ [atms / cm ² ], so that the masked region is lightly read. A doped drain (LDD) structure may be used. Alternatively, the pattern is formed using a mask wider than the width of the gate electrode 2a without lightly doping, and then the source and drain are formed by implanting ions, and then the gate electrode is overetched, thereby offset. You may make it become a structure.
[0024]
In the step (7), the first interlayer insulating film 13 is deposited to a thickness of 5000 to 15000 angstroms at a temperature of 800 degrees by, for example, a CVD method so as to cover the gate electrode 2a.
[0025]
In the step (8), a contact hole 5 is formed in the first interlayer insulating film 13 at a position corresponding to the source region of the TFT by dry etching or the like.
[0026]
Here, the contact hole 5 is formed so as to penetrate the stacked film of the gate insulating film 12 and the first interlayer insulating film 13.
[0027]
Next, with reference to FIG. 4, in the step (9), a low resistance conductive layer 3 such as aluminum to be a data line that also serves as a source electrode is deposited by sputtering. The low-resistance conductive layer 3 is connected to the source region of the active layer 1a through a contact hole 5 of the TFT.
[0028]
In step (10), the low-resistance conductive layer 3 is patterned by photoetching to form the data line 3a that also serves as the source electrode of the TFT.
[0029]
In the step (11), the second interlayer insulating film 15 is formed to have a thickness of 5000 to 15000 angstroms at a low temperature of 500 degrees, for example, by the CVD method so as to cover the data lines 3a.
[0030]
Next, the explanation will be shifted to FIG. 5. In the step (12), the second interlayer insulating film 15, the first interlayer insulating film 13 and the gate insulating film 12 under the second interlayer insulating film 15, At the position corresponding to the drain region, first, dry etching is performed to form holes by anisotropic etching, and second, the holes are penetrated to the active layer 1a by wet etching to contact the TFT. Hole 4 is formed.
[0031]
In the step (13), the ITO film 6 to be the pixel electrode is formed by sputtering, for example, to a thickness of 1500 angstroms. At this time, in the TFT, the ITO film 6 is connected to the drain region of the active layer 1 a through the contact hole 4.
[0032]
In the step (14), the pixel electrode 6a of the TFT is formed by patterning the ITO film 6 by photoetching.
[0033]
A plurality of such TFTs are actually formed on the substrate 10 corresponding to each pixel.
[0034]
As described above, according to the semiconductor manufacturing method of the present embodiment, after depositing the polysilicon layer 1 on the substrate 10 and then patterning it by etching, the active layer 1a is formed. By slightly etching the exposed surface of the substrate 10 together with unnecessary portions of the polysilicon layer 1, impurities, residues, and the like are removed. Therefore, the problem that the crystallized material is deposited on the surface of the substrate 10 on which the active layer 1a is formed, and the adverse effect in the subsequent process is solved.
[0035]
<Application example>
Next, an application example in which the TFT formed according to the present embodiment is applied to an active matrix type liquid crystal panel will be described.
[0036]
FIG. 6 is a block diagram showing a configuration of the substrate 10 on which TFTs are formed in the liquid crystal panel according to the application example.
[0037]
In the figure, reference numerals 90, 90,... Denote pixels, which are respectively arranged corresponding to the intersections of the scanning lines 2 and the data lines 3 arranged so as to intersect each other. Each pixel 90 includes a pixel electrode 6a made of ITO or the like and a TFT 91 for applying a voltage corresponding to an image signal on the data line 3 to the pixel electrode 6a. The TFTs 91 in the same row have their gate electrodes connected to the same scanning line 2 and their drains connected to the corresponding pixel electrode 6a. The source electrodes of the TFTs 91 in the same column are connected to the same data line 3. In this application example, the transistors constituting the peripheral circuits (X and Y shift registers and sampling means) 50 and 60 are constituted by so-called polysilicon TFTs having a polysilicon layer as an operation layer in the same manner as TFTs for driving pixels. Yes. Therefore, the transistors constituting the peripheral circuits 50 and 60 are simultaneously formed by the same process together with the pixel driving TFT.
[0038]
In the figure, a shift register (hereinafter referred to as an X shift register) 51 for sequentially selecting the data lines 3 is disposed at the upper end of the display area (pixel matrix) 20, while the left end of the pixel matrix is disposed at the left end of the pixel matrix. A shift register (hereinafter referred to as a Y shift register) 61 for sequentially selecting and driving the scanning lines 2 is provided. Further, a buffer 63 is provided at the next stage of the Y shift register 61 as necessary. A sampling switch 52 composed of a TFT is provided at one end of each data line 3. These sampling switches 52 are connected between the video signal lines 54, 55, and 56 that transmit the image signals VID 1 to VID 3 input to the external terminals 74, 75, and 76, and are output from the X shift register 51. It is configured to be sequentially turned on / off by a sampling signal. The X shift register 51 selects a sampling signal X1 that sequentially selects all the data lines 3 once in a horizontal scanning period based on clock signals CLX1 and CLK2 input from the outside via terminals 72 and 73. , X2, X3,..., Xn are formed and supplied to the control terminal of the sampling switch 52. On the other hand, the Y shift register 61 is operated in synchronization with clock signals CLY1 and CLY2 input from the outside via terminals 77 and 78, and sequentially drives each scanning line 2. The terminals 72 to 78 and the like are arranged as a pad electrode group in a line along the peripheral edge of the substrate 10 as will be described later.
[0039]
Next, the configuration of the entire liquid crystal panel will be described. FIG. 7A is a cross-sectional view showing a configuration of a liquid crystal panel to which the substrate in FIG. 6 is applied, and FIG. 7B is a plan view showing the layout thereof.
[0040]
First, as shown in FIG. 7A, a liquid crystal panel 30 includes a substrate 10 on which TFTs and pixel electrodes are formed, a counter substrate 31 having a transparent conductive film such as ITO as a counter electrode (common electrode) 33, and Are bonded by a sealing material 36 so that the electrodes face each other and at an appropriate interval, and a TN (Twisted Nematic) type or SH (Super) is formed in the gap. Homeotropic) type liquid crystal 37 is filled. Here, on the upper surface (lower side in the figure) of the counter electrode 33 in the counter substrate 31, a black matrix layer that shields light other than the portion corresponding to the pixel electrode in the substrate 10, and a color filter layer as necessary are provided. (Not shown).
[0041]
The upper part of the peripheral circuits 50 and 60 is configured to be shielded from light by, for example, a black matrix layer provided on the counter substrate 31. Reference numeral 38 denotes a liquid crystal injection port provided on the counter substrate 31 side, and reference numeral 39 denotes a parting light shielding layer made of a chromium layer or the like provided on the counter substrate 31. In addition, as necessary for the liquid crystal panel, a polarizing plate for selecting the polarization direction of incident / exited light, an alignment film for determining the molecular arrangement of the liquid crystal 37, and a gap between the substrate 10 and the counter substrate 31 are kept constant over the entire surface. Although a spacer etc. are mentioned, suppose that illustration is abbreviate | omitted.
[0042]
As shown in FIG. 7B, the counter substrate 31 has a shape slightly smaller than the substrate 10 on which the TFTs are formed. Therefore, the pad electrode group 70 disposed on the peripheral edge of the substrate 10 It is exposed to the outside of the substrate 31 for convenience when used as an external input terminal for inputting a clock signal, a start signal, a video signal or the like to the peripheral circuits 50 and 60 described above.
[0043]
In addition to the pad electrode group 70, a pad electrode group 170 as an inspection terminal used for inputting / outputting a signal at the time of inspection by a probe is provided on the peripheral portion of the substrate 10. On the other hand, the counter substrate 31 is also provided with a pad electrode group 270 as an inspection terminal. These pad electrode groups are used for input / output of signals for inspecting a short circuit of a data line, a defect of a pixel electrode, or the like. Is done.
[0044]
Reference numeral 80 denotes a terminal for connecting between the upper and lower substrates for applying a common potential from the substrate 10 on which the TFT is formed to the counter electrode 33 of the counter substrate 31, with a conductive adhesive having a predetermined diameter interposed therebetween. The substrate 10 and the counter substrate 31 are electrically connected.
[0045]
Next, an example of connection between the liquid crystal panel and an external circuit will be described with reference to FIG. As shown in this figure, one pad electrode 71 in a pad electrode group 70 and an FPC (Film Printed Circuit) 102 connected to an external circuit and supplying signals such as a clock signal, a start signal, and a video signal are shown. The terminal electrode 103 is physically fixed and held by the adhesive 101 while being electrically connected by the conductive particles 100 dispersed in the adhesive 101.
[0046]
Here, if the concentration of the conductive particles 100 in the adhesive 101 is set appropriately, conduction is allowed in the vertical direction of the adhesive layer (the direction connecting the pad electrode 71 and the terminal electrode 103), but in the plane direction of the adhesive layer. An anisotropic conductive junction that does not allow conduction is realized. The anisotropic conductive bonding is efficient because a large number of terminals with a narrow interval can be connected together.
[0047]
The FPC 102 is formed, for example, by patterning a copper foil laminated on a polyimide film by a known photolithography process, an etching process, or the like. For the conductive particles 100, metal particles such as solder nickel, metal plated plastic balls, or the like is used.
[0048]
<Application example of liquid crystal panel (1)>
Next, an example in which the liquid crystal panel according to the application example is used as a display device will be described.
[0049]
First, a video projector using this liquid crystal panel as a light valve will be described. FIG. 9 is a plan view showing a configuration example of a video projector.
[0050]
As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the video projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by a plurality of mirrors 1106, 1106,... Is incident on the liquid crystal panels 1110R, 1110B and 1110G as light valves.
[0051]
The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are as described above, and are driven by R, G, and B primary color signals supplied from a video signal processing circuit (not shown). Now, the light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light goes straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.
[0052]
<Application example of liquid crystal panel (2)>
Next, an example in which the liquid crystal panel according to the application example is applied to a personal computer will be described. FIG. 10 is a front view showing the configuration of the personal computer. In the figure, a personal computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display 1206. The liquid crystal display 1206 is configured by adding a color filter and a backlight to the liquid crystal panel according to the application example described above.
[0053]
Although the video projector 1100 and the personal computer 1200 have been described as application examples of the liquid crystal panel, it goes without saying that the present invention can be applied to various other electronic devices.
[0054]
【The invention's effect】
As described above, according to the present invention, the surface of the first layer exposed by the patterning of the second layer is etched, so that a portion damaged by CVD or the like is removed, and the original of the first layer is removed. A natural character. Further, this etching also removes impurities attached to the surface of the insulating substrate and residues left during cleaning. Therefore, it is possible to prevent the crystallized product from being precipitated and to prevent adverse effects on the subsequent steps.
[Brief description of the drawings]
FIG. 1A is a plan view showing a layout for one pixel of a liquid crystal panel substrate to which a TFT according to a manufacturing method of a semiconductor device according to an embodiment of the present invention is applied, and FIG. It is sectional drawing of an AA line.
FIGS. 2A to 2D are diagrams showing manufacturing steps of the TFT according to the embodiment. FIGS.
FIGS. 3A to 3E are diagrams showing a manufacturing process of the TFT according to the embodiment. FIGS.
4 (9) to (11) are views showing a manufacturing process of the TFT according to the embodiment, respectively. FIG.
FIGS. 5A to 5D are diagrams showing a manufacturing process of the TFT according to the embodiment; FIGS.
FIG. 6 is a block diagram showing a configuration of a liquid crystal panel substrate having TFTs to which the semiconductor device manufacturing method according to the embodiment is applied.
7A is a cross-sectional view showing the configuration of a liquid crystal panel having TFTs to which the method for manufacturing a semiconductor device according to the present embodiment is applied, and FIG. 7B is a plan view showing the configuration of the liquid crystal panel. It is.
FIG. 8 is a cross-sectional view showing an anisotropic conductive joint structure between the liquid crystal panel and an external circuit.
FIG. 9 is a plan view showing a configuration of a video projector using the liquid crystal panel as a light valve.
FIG. 10 is a plan view showing a configuration of a personal computer using the liquid crystal panel as a display device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Polysilicon layer, 1a ... Active layer, 2a ... Scan line (gate electrode), 3a ... Data line (source electrode), 4, 5 ... Contact hole, 6 ... ITO film, 6a ... Pixel electrode, 10 ... Substrate, DESCRIPTION OF SYMBOLS 12 ... Gate insulating film, 13 ... 1st interlayer insulating film, 15 ... 2nd interlayer insulating film, 20 ... Display area, 30 ... Liquid crystal panel, 31 ... Opposite substrate

Claims (3)

A first step of forming a second layer of polysilicon, which becomes an active layer of a semiconductor device, on the insulating first layer by a CVD method;
In a method for manufacturing a semiconductor device having at least a second step of forming the second layer in a predetermined island pattern,
In the second step, the unnecessary portion of the second layer formed in the first step is etched and the first layer exposed by the etching of the unnecessary portion is damaged by the CVD method. A method for manufacturing a semiconductor device, characterized in that the surface portion subjected to the etching is simultaneously etched by reactive ion etching using CHF ₃ gas and SF ₆ gas.   The semiconductor device is a thin film transistor connected to each of a plurality of scanning lines and a plurality of data lines and formed corresponding to each pixel, and the first layer is an insulating substrate. Item 12. A method for manufacturing a semiconductor device according to Item 1. Depositing a polysilicon layer as an active layer of a thin film transistor on an insulating substrate by a CVD method;
Step of simultaneously performing island-shaped patterning of the polysilicon layer and light etching of an exposed portion damaged by the CVD method on the insulating substrate by reactive ion etching using CHF ₃ gas and SF ₆ gas When,
Forming a gate insulating film so as to cover the patterned polysilicon layer;
And a step of forming a gate electrode on the gate insulating film.

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