JP2004260209A - Liquid crystal panel and liquid crystal panel manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a next process from accepting harmful effect even if an insulating substrate 10 is left as it is for a long period of time after depositing polysilicon layers to form the active layers of a semiconductor device on the substrate 10 and forming it into a designated pattern. <P>SOLUTION: In an etching process in which an active layer 1a of the semiconductor device is formed on by patterning a polysilicon layer after depositing the polysilicon layers on the insulating substrate 10, front surface of the substrate 10 exposed by removing the polysilicon layer is also slightly etched. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device such as a thin film transistor (hereinafter, simply referred to as a TFT) formed on a glass substrate, and particularly, to recover properties of a substrate surface damaged by a heat treatment or a CVD process. In addition, the present invention relates to a technique for removing impurities and residues adhering to the surface. Further, the present invention relates to the semiconductor device, a liquid crystal panel substrate and a liquid crystal panel using the same.

  In a conventional method of manufacturing a semiconductor device, for example, a method of manufacturing a TFT, the gate electrode 2a is formed as follows. That is, first, polysilicon, amorphous silicon, or the like is deposited on the substrate 10 and then patterned to form an active layer 1a serving as a source, a drain, and a channel. Second, the surface of the active layer 1a is Third, a gate insulating film 12 is formed by thermal oxidation or the like, and thirdly, a conductive layer is deposited and then patterned to form a gate electrode 2a as shown in FIG. 2 (5). You.

  However, if the substrate 10 on which the TFT active layer 1a is formed is left for a long period of time for some reason, a crystallized substance is deposited on the surface, which has a problem of adversely affecting later steps.

  When examining the cause, it is considered that the reason is as follows. First, since CVD or the like is used to deposit the polysilicon layer 1 on the surface of the substrate 10, some damage occurs on the surface of the substrate 10. Second, even if the surface of the substrate 10 is cleaned after forming the active layer 1a of the TFT due to the damage, the cleaning liquid or the like cannot be completely removed. Third, it is considered that this residue adsorbs hydrocarbons in the air, and as a result, crystallizes.

  The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to deposit a silicon layer on an insulating substrate like a TFT, form the silicon layer in a predetermined pattern, and then elongate the substrate. An object of the present invention is to provide a semiconductor manufacturing method, a semiconductor device, a liquid crystal panel substrate using the element, and a liquid crystal panel using the substrate, which do not adversely affect a subsequent process even if left for a period.

  In order to solve the above problems, in the present invention, a first step of depositing a second layer on a first layer and a second step of forming the second layer in a predetermined pattern In the method of manufacturing a semiconductor device having at least the following, in the second step, an unnecessary portion of the second layer deposited in the first step and an exposed surface of the exposed first layer are etched. And

  Usually, CVD, sputtering, or the like is used for depositing the layer, so that the surface of the first layer is considerably damaged. However, according to the present invention, since the surface of the first layer is etched, the damaged portion is removed, and it is possible to bring out the intrinsic properties of the first layer. In addition, along with this etching, impurities attached to the surface of the first layer, residues from cleaning, and the like are also removed.

  The method for manufacturing a liquid crystal panel according to the present invention includes a plurality of data lines formed on a substrate, a plurality of scanning lines intersecting the plurality of data lines, and a plurality of data lines connected to the plurality of data lines and the scanning lines. In a method for manufacturing a liquid crystal panel having a thin film transistor and a plurality of pixel electrodes connected to the plurality of thin film transistors, a step of depositing and patterning a silicon layer to be an active layer of the thin film transistor on the substrate; Forming a gate insulating film so as to cover the gate insulating film, light etching the exposed portion of the gate insulating film and the substrate, and forming a gate electrode on the lightly etched gate insulating film. It is characterized by the following. According to the present invention, since the exposed surface of the substrate is also etched along with the etching of the gate insulating film, impurities and the like are removed, and the adverse effect of the substrate can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment>
In this embodiment, as a semiconductor device, a polysilicon TFT driving each pixel of an active matrix liquid crystal display device is used. FIG. 1A shows one pixel on a liquid crystal panel substrate to which the TFT is applied. FIG. 3 is a plan view showing a layout of FIG. FIG. 1B is a cross-sectional view showing the structure of the TFT along the line AA in FIG. 1A.

  First, in FIG. 1A, reference numeral 1a denotes a first polysilicon layer, which forms an active layer (source / drain / channel region) of a TFT. Reference numeral 2a denotes a scanning line, which becomes a gate electrode in a TFT. A data line 3a supplies a voltage to be applied to a source region of a TFT disposed so as to intersect with the scanning line 2a. Here, the scanning line 2a is formed by a second polysilicon layer, and the data line 3a is formed by a conductive layer such as an aluminum layer.

  Further, a contact hole 4 is provided for connecting a pixel electrode 6a made of an ITO (Indium-Tin Oxide) film to a drain region (or a source region) of the TFT in the polysilicon layer 1, and the contact hole 5 is provided. , For connecting the data line 3a to the source region of the TFT in the polysilicon layer 1a.

Next, in FIG. 1B, the substrate 10 is formed of an insulating substrate such as a glass substrate (for example, a non-alkali substrate) or a quartz substrate. The gate insulating film 12 is formed on the surface of the polysilicon layer 1 serving as an active layer of the TFT by subjecting the polysilicon layer 1 to thermal oxidation or the like. The first interlayer insulating film 13 and the second interlayer insulating film 15 are each made of a SiO ₂ film (NSG film), a BPSG film (silicate glass film containing boron and phosphorus), and the like, as described later. Formed by

  The manufacturing process of the TFT having such a configuration will be described with reference to FIGS.

  First, in the step (1), the polysilicon layer 1 is deposited on the upper surface of the substrate 10 to a thickness of 500 to 2,000 angstroms, preferably, a little less than 1,000 angstroms by, for example, a low pressure CVD method.

Next, in step (2), the polysilicon layer 1 deposited on the substrate 10 is patterned by etching that reacts with the polysilicon and the material of the substrate 10 to form an island-like active layer 1a in the TFT. Then, the exposed surface of the substrate 10 is slightly etched. That is, in this step, when the unnecessary portion of the polysilicon layer 1 is removed, the exposed surface of the substrate 10 is slightly etched. Here, for the etching in the step (2), for example, the following RIE (reactive ion etching) is effective. That is, when the RIE conditions are as follows: gas pressure: 1600 [m torr], CHF ₃ : 5 [sccm], SF ₆ : 15 [sccm], He: 80 [sccm], and power: 250 [W] The etching selectivity is 1: 1 between the polysilicon layer 1 and the substrate 10, and the etching rate is 2000 angstroms per minute.

  Therefore, if the etching time under this condition is set to 30 [seconds] and the thickness of the polysilicon layer 1 deposited in the step (1) is set to a preferable thickness of less than 1000 angstroms, the polysilicon layer 1a becomes unnecessary. It can be seen that the portion is removed and the exposed surface of the substrate 10 is also etched with a small amount. For this reason, the surface of the substrate 10 is slightly etched, and the damaged portion, impurities, residue, and the like are removed.

  As a result, the surface portion of the substrate 10 that has been damaged in the step (1) is removed, and the properties inherent to the substrate 10 can be brought out. Further, with the light etching of the substrate 10, impurities attached to the surface thereof and residues left during cleaning are also removed, so that the inconvenience of crystallized product is also eliminated. In addition, these effects can be achieved without adding a new step.

  Now, in the step (3), the surface of the active layer 1a is subjected to a thermal oxidation treatment to form the gate insulating film 12 on the surface of the active layer 1a. By this step, the active layer 1a finally has a thickness of 300 to 1500 angstroms, preferably 350 to 450 angstroms, and the gate insulating film 12 has a thickness of about 600 to 1500 angstroms.

Here, an impurity (for example, phosphorus) is added to an extension 1b (see FIG. 1A) of the polysilicon layer constituting the active layer 1a, which extends upward along the data line 3a and forms a storage capacitor. ) At an appropriate dose (for example, 3 × 10 ¹⁴ [atms / cm ² ]) to lower the resistance of the polysilicon layer in that portion. The lower limit of the dose is determined from the viewpoint of securing the conductivity necessary for forming the storage capacitor of the polysilicon layer, and the upper limit is determined from the viewpoint of suppressing the deterioration of the gate oxide film.

  Then, in the step (4), a low-resistance polysilicon layer 2 to be a gate electrode and a scanning line is deposited on the gate insulating film 12 and the substrate 10 of the TFT by a low pressure CVD method or the like. Here, as a material of the gate electrode, a high melting point metal such as Mo, Ta, Ti, W, or a metal silicide thereof can be used in addition to polysilicon.

  Turning now to FIG. 3, in step (5), the polysilicon layer 2 is patterned by chemical dry etching to form a gate electrode 2a including a scanning line of a TFT.

In the step (6), impurities (for example, phosphorus) ions are implanted using the gate electrode 2a as a mask to form a self-aligned high-concentration semiconductor region serving as a source region and a drain region in the active layer 1a of the TFT. Note that the source / drain region is lightly doped with an impurity (phosphorus) at a dose of 1 × 10 ^{13 to} 3 × 10 ¹³ [atms / cm ² ] to form a low-concentration region. A wide mask layer is formed on the scanning line 2a, and impurities (phosphorus) are implanted at a dose of 1 × 10 ^{15 to} 3 × 10 ¹⁵ [atms / cm ² ], so that the masked region is lightly -A doped drain (LDD) structure may be adopted. Alternatively, the pattern is formed using a mask wider than the width of the gate electrode 2a without lightly doping, and then the gate electrode is over-etched after forming the source / drain by implanting ions. You may make it become a structure.

  In the step (7), the first interlayer insulating film 13 is deposited so as to cover the gate electrode 2a to a thickness of 5000 to 15000 angstroms at a temperature of 800.degree.

  In the step (8), a contact hole 5 is formed in the first interlayer insulating film 13 at a position corresponding to the source region of the TFT by dry etching or the like.

  Here, the contact hole 5 is formed so as to penetrate the stacked film of the gate insulating film 12 and the first interlayer insulating film 13.

  Turning now to FIG. 4, in the step (9), a low-resistance conductive layer 3 of aluminum or the like to be a data line also serving as a source electrode is deposited by sputtering. This low resistance conductive layer 3 is connected to the source region of the active layer 1a at the contact hole 5 of the TFT.

  In the step (10), the low-resistance conductive layer 3 is patterned by photoetching to form a data line 3a also serving as a source electrode of the TFT.

  In the step (11), the second interlayer insulating film 15 is formed to have a thickness of 5000 to 15000 angstroms at a low temperature such as 500 degrees by, for example, the CVD method so as to cover the data lines 3a.

  Next, referring to FIG. 5, in the step (12), the laminated film is composed of the second interlayer insulating film 15, the first interlayer insulating film 13 under the second interlayer insulating film 15, and the gate insulating film 12, At a position corresponding to the drain region, first, dry etching is performed to form a hole by anisotropic etching, and second, the hole is penetrated to the active layer 1a by wet etching to form a TFT contact. A hole 4 is formed.

  In the step (13), the ITO film 6 to be a pixel electrode is formed to a thickness of, for example, 1500 angstroms by a sputtering method. At this time, in the TFT, the ITO film 6 is connected to the drain region of the active layer 1a through the contact hole 4.

  In the step (14), the pixel electrode 6a of the TFT is formed by patterning the ITO film 6 by photoetching.

  In practice, a plurality of such TFTs are formed on the substrate 10 corresponding to each pixel.

  As described above, according to the method of manufacturing a semiconductor according to the present embodiment, when the polysilicon layer 1 is deposited on the substrate 10 and then patterned by etching to form the active layer 1a, By slightly etching the exposed surface of the substrate 10 together with the unnecessary portion of the polysilicon layer 1, impurities and residues are removed. Therefore, the problem that a crystallized substance is deposited on the surface of the substrate 10 on which the active layer 1a is formed and adversely affects a subsequent process can be solved.

<Application example>
Next, an application example in which the TFT formed according to this embodiment is applied to an active matrix type liquid crystal panel will be described.

  FIG. 6 is a block diagram showing a configuration of a substrate 10 on which a TFT is formed, of a liquid crystal panel according to an application example.

  In the figure, reference numerals 90, 90,... Denote pixels, which are respectively arranged corresponding to the intersections of the scanning lines 2 and the data lines 3 arranged so as to cross each other. Each pixel 90 includes a pixel electrode 6a made of ITO or the like and a TFT 91 for applying a voltage corresponding to an image signal on the data line 3 to the pixel electrode 6a. The TFTs 91 in the same row have their gate electrodes connected to the same scanning line 2 and their drains connected to the corresponding pixel electrodes 6a. The source electrodes of the TFTs 91 in the same column are connected to the same data line 3. In this application example, transistors constituting peripheral circuits (X, Y shift registers and sampling means) 50 and 60 are constituted by so-called polysilicon TFTs having a polysilicon layer as an operation layer, similarly to TFTs for driving pixels. I have. Therefore, the transistors constituting the peripheral circuits 50 and 60 are formed simultaneously with the pixel driving TFT by the same process.

In the drawing, a shift register (hereinafter, referred to as an X shift register) 51 for sequentially selecting the data lines 3 is arranged at one upper end of a display area (pixel matrix) 20, and at a left end of the pixel matrix. , A shift register (hereinafter referred to as a Y shift register) 61 for sequentially selecting and driving the scanning lines 2 is provided. A buffer 63 is provided at the next stage of the Y shift register 61 as necessary. One end of each data line 3 is provided with a sampling switch 52 composed of a TFT. These sampling switches 52 are connected between video signal lines 54, 55, and 56 transmitting image signals VID <b> 1 to VID <b> 3 input to external terminals 74, 75, 76, and output from the X shift register 51. It is configured to be sequentially turned on / off by a sampling signal. The X shift register 51 selects a sampling signal X1 for sequentially selecting all the data lines 3 once during one horizontal scanning period based on clock signals CLX1 and CLK2 input from the outside via the terminals 72 and 73. , X2, X3,..., Xn are supplied to the control terminal of the sampling switch 52. On the other hand, the Y shift register 61 is operated in synchronization with clock signals CLY1 and CLY2 input from the outside via terminals 77 and 78, and sequentially drives each scanning line 2. In addition, the terminals 72 to 78 and the like are arranged as a pad electrode group in a line along the periphery of the substrate 10 as described later.

  Next, the configuration of the entire liquid crystal panel will be described. FIG. 7A is a cross-sectional view illustrating a configuration of a liquid crystal panel to which the substrate in FIG. 6 is applied, and FIG. 7B is a plan view illustrating a layout thereof.

  First, as shown in FIG. 7A, a liquid crystal panel 30 includes a substrate 10 on which TFTs and pixel electrodes are formed, and a counter substrate 31 having a transparent conductive film such as ITO as a counter electrode (common electrode) 33. Are bonded by a sealing material 36 such that the electrodes face each other and at an appropriate interval, and further, a TN (Twisted Nematic) type or SH (Super (Homeotropic) type liquid crystal 37 is filled. Here, on the upper surface (lower side in the figure) of the counter electrode 33 on the counter substrate 31, a black matrix layer that shields the portion other than the portion corresponding to the pixel electrode on the substrate 10 and a color filter layer as necessary are provided. (Not shown).

  The upper part of the peripheral circuits 50 and 60 is configured to be shielded from light by, for example, a black matrix layer provided on the counter substrate 31. Reference numeral 38 denotes a liquid crystal injection port provided on the counter substrate 31 side, and reference numeral 39 denotes a parting light-shielding layer formed of a chrome layer or the like provided on the counter substrate 31. In addition, as necessary for the liquid crystal panel, a polarizing plate for selecting the polarization direction of the incoming and outgoing light, an alignment film for determining the molecular arrangement of the liquid crystal 37, and a gap for maintaining the gap between the substrate 10 and the counter substrate 31 constant over the entire surface. Although a spacer and the like are mentioned, illustration is omitted.

  Now, as shown in FIG. 7B, the counter substrate 31 has a shape slightly smaller than the substrate 10 on which the TFT is formed, so that the pad electrode group 70 disposed on the peripheral portion of the substrate 10 Exposure outside the substrate 31 is convenient for use as an external input terminal for inputting signals such as a clock signal, a start signal, and a video signal to the peripheral circuits 50 and 60 described above.

  In addition, a pad electrode group 170 as an inspection terminal used for inputting / outputting a signal at the time of inspection by a probe is provided on the periphery of the substrate 10 in addition to the pad electrode group 70. On the other hand, a pad electrode group 270 as an inspection terminal is also provided on the opposite substrate 31. These pad electrode groups are used for input / output of signals for inspecting a short circuit of a data line, a defect of a pixel electrode, and the like. Is done.

  Reference numeral 80 denotes a terminal for conduction between the upper and lower substrates for applying a common potential from the substrate 10 on which the TFT is formed to the counter electrode 33 of the counter substrate 31 via a conductive adhesive having a predetermined diameter. , The substrate 10 and the opposing substrate 31 are electrically connected.

  Next, an example of connection between a liquid crystal panel and an external circuit will be described with reference to FIG. As shown in this figure, one pad electrode 71 of the pad electrode group 70 and a film printed circuit (FPC) 102 connected to an external circuit and supplying signals such as a clock signal, a start signal, and a video signal. The terminal electrode 103 is physically fixed and held by the adhesive 101, and is electrically connected by the conductive particles 100 dispersed in the adhesive 101.

  Here, if the concentration of the conductive particles 100 in the adhesive 101 is appropriately set, conduction is allowed in the vertical direction of the adhesive layer (the direction connecting the pad electrode 71 and the terminal electrode 103), but in the planar direction of the adhesive layer. Realizes an anisotropic conductive junction that does not allow conduction. According to the anisotropic conductive bonding, a large number of terminals having a small interval can be connected collectively, which is efficient.

  The FPC 102 is formed, for example, by patterning a copper foil laminated on a polyimide film by a known photolithography process, an etching process, or the like. As the conductive particles 100, metal particles such as solder nickel or metal-plated plastic balls are used.

<Application example 1 of liquid crystal panel>
Next, an example in which a liquid crystal panel according to an application example is used as a display device will be described.

  First, a video projector using this liquid crystal panel as a light valve will be described. FIG. 9 is a plan view showing a configuration example of the video projector.

  As shown in the figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside a video projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by a plurality of mirrors 1106, 1106,... And two dichroic mirrors 1108 arranged in the light guide 1104, and corresponds to each primary color. To the liquid crystal panels 1110R, 1110B and 1110G as light valves.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are as described above, and are driven by R, G, and B primary color signals supplied from a video signal processing circuit (not shown). The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B lights are refracted by 90 degrees, while the G light travels straight. Accordingly, as a result of combining the images of the respective colors, a color image is projected on a screen or the like via the projection lens 1114.

<Application example 2 of liquid crystal panel>
Next, an example in which the liquid crystal panel according to the application example is applied to a personal computer will be described. FIG. 10 is a front view showing the configuration of this personal computer. In the figure, a personal computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display 1206. The liquid crystal display 1206 is configured by adding a color filter and a backlight to the liquid crystal panel according to the application example described above.

  Although the video projector 1100 and the personal computer 1200 have been described as application examples of the liquid crystal panel, it is needless to say that the liquid crystal panel can be applied to various other electronic devices.

  As described above, according to the present invention, the surface of the first layer exposed by the patterning of the second layer is etched, so that the portion damaged by CVD or the like is removed, and the original of the first layer is removed. Characteristic is brought out. In addition, by this etching, impurities adhered to the surface of the insulating substrate and residues left during cleaning are also removed. Therefore, it is possible to prevent the precipitation of the crystallized substance and to prevent the subsequent steps from being adversely affected.

(A) is a plan view showing a layout for one pixel of a liquid crystal panel substrate to which a TFT is applied by a method of manufacturing a semiconductor device according to an embodiment of the present invention, and (b) is a line AA thereof. FIG. (1)-(4) are figures which show the manufacturing process of TFT which concerns on the same embodiment, respectively. (5) to (8) are diagrams illustrating steps of manufacturing the TFT according to the same embodiment. (9)-(11) are figures which show the manufacturing process of the TFT concerning the embodiment, respectively. (12)-(14) are each a view showing a manufacturing process of the TFT according to the same embodiment. FIG. 2 is a block diagram illustrating a configuration of a liquid crystal panel substrate having a TFT to which the method of manufacturing a semiconductor device according to the embodiment is applied. FIG. 2A is a cross-sectional view illustrating a configuration of a liquid crystal panel substrate having a TFT to which the semiconductor device manufacturing method according to the embodiment is applied, and FIG. 2B is a plan view illustrating the configuration of the liquid crystal panel. It is sectional drawing which shows the anisotropic conductive joining structure of the same liquid crystal panel and an external circuit. FIG. 2 is a plan view showing a configuration of a video projector using the same liquid crystal panel as a light valve. It is a top view showing the composition of the personal computer which used the same liquid crystal panel for the display.

Explanation of reference numerals

1 {polysilicon layer 1a} active layer 2a} scanning line (gate electrode)
3a @ data line (source electrode)
4,5 contact hole 6 ITO film 6a pixel electrode 10 substrate 12 gate insulating film 13 first interlayer insulating film 15 second interlayer insulating film 20 display area 30 liquid crystal panel 31 counter substrate

Claims (2)

Depositing and patterning a silicon layer to be an active layer of a thin film transistor on a substrate, forming a gate insulating film so as to cover the silicon layer, and light-etching the gate insulating film and an exposed portion on the substrate. And forming a gate electrode on the light-etched gate insulating film. A silicon layer serving as an active layer of the thin film transistor on the substrate, a gate insulating film covering the silicon layer, and a gate electrode on the gate insulating film; and the exposed portions on the gate insulating film and the substrate are light-etched. Liquid crystal panel characterized by being done.

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