JP2011090288A - Thin-film transistor array panel and method of manufacturing the same - Google Patents

Thin-film transistor array panel and method of manufacturing the same Download PDF

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JP2011090288A
JP2011090288A JP2010190891A JP2010190891A JP2011090288A JP 2011090288 A JP2011090288 A JP 2011090288A JP 2010190891 A JP2010190891 A JP 2010190891A JP 2010190891 A JP2010190891 A JP 2010190891A JP 2011090288 A JP2011090288 A JP 2011090288A
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liquid crystal
display device
crystal display
conductor pattern
common voltage
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JP5683874B2 (en
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Seiei Lee
成 榮 李
Dong-Gyo Kim
東 奎 金
Jun-Jung Cho
允 淨 趙
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13398—Spacer materials; Spacer properties
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/64—Normally black display, i.e. the off state being black

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Geometry (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of blocking light in a column spacer region without reducing the aperture ratio. <P>SOLUTION: The liquid crystal display device is in a normally black mode where a screen is black when a voltage difference between a first insulating substrate and a second insulating substrate is zero, wherein a column spacer is positioned between the first insulating substrate and the second insulating substrate, and the column spacer is brought into contact with a common voltage conductor pattern, formed on the first insulating substrate and with a common electrode formed on the second insulating substrate, and the voltage difference between the common voltage conductor pattern and the common electrode becomes zero. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、開口率の減少なしにカラムスペーサ部を光遮断する液晶表示装置に関する。   The present invention relates to a liquid crystal display device that blocks light of a column spacer without reducing the aperture ratio.

液晶表示装置（ｌｉｑｕｉｄ ｃｒｙｓｔａｌ ｄｉｓｐｌａｙ ｄｅｖｉｃｅ）は、現在、最も幅広く使用されている平板表示装置（ｆｌａｔ ｐａｎｅｌ ｄｉｓｐｌａｙ ｄｅｖｉｃｅ）の一つであって、画素電極と共通電極など電界生成電極（ｆｉｅｌｄ ｇｅｎｅｒａｔｉｎｇ ｅｌｅｃｔｒｏｄｅ）が形成される二枚の表示板（ｄｉｓｐｌａｙ ｐａｎｅｌ）と、その間に挿入される液晶層とを含んでいる。液晶表示装置は、電界生成電極に電圧を印加して液晶層に電界を生成し、これを通じて液晶層の液晶分子の方向を決定して、入射光の偏光を制御することによって映像を表示している。   The liquid crystal display device is one of the most widely used flat panel display devices, and includes a field generating electrode such as a pixel electrode and a common electrode. It includes two display panels to be formed and a liquid crystal layer inserted between them. A liquid crystal display device displays an image by applying a voltage to an electric field generating electrode to generate an electric field in a liquid crystal layer, determining the direction of liquid crystal molecules in the liquid crystal layer through this, and controlling the polarization of incident light. Yes.

垂直配向方式（ｖｅｒｔｉｃａｌ ａｌｉｇｎｍｅｎｔ；ＶＡ）などのノーマリブラックモード（ｎｏｒｍａｌｌｙ ｂｌａｃｋ ｍｏｄｅ）においては、二つの表示板の間に電圧差がゼロとなる場合、ブラック画面が実現される。   In a normally black mode, such as a vertical alignment (VA), a black screen is realized when the voltage difference between the two display panels is zero.

液晶表示装置の二つの表示板は、薄膜トランジスタアレイパネル（ｔｈｉｎ ｆｉｌｍ ｔｒａｎｓｉｓｔｏｒ ａｒｒａｙ ｐａｎｅｌ）と共通電極基板２００などによって構成されている。   The two display panels of the liquid crystal display device include a thin film transistor array panel, a common electrode substrate 200, and the like.

薄膜トランジスタアレイパネルの上には、ゲート配線及びデータ配線などの信号線、透明画素電極などが形成されている。また、薄膜トランジスタアレイパネルの上には、ゲート配線またはデータ配線と同一の物質で共通電圧配線が形成されている。   On the thin film transistor array panel, signal lines such as gate lines and data lines, transparent pixel electrodes, and the like are formed. A common voltage wiring is formed on the thin film transistor array panel using the same material as the gate wiring or the data wiring.

共通電極基板の上には、カラーフィルタ層または光遮断ブラックマトリックス層が形成され、カラーフィルタ層または光遮断ブラックマトリックス層の上には透明共通電極が形成され、透明共通電極には薄膜トランジスタアレイパネル上の共通電圧配線と同一の電圧が印加される。   A color filter layer or a light blocking black matrix layer is formed on the common electrode substrate, a transparent common electrode is formed on the color filter layer or the light blocking black matrix layer, and the transparent common electrode is disposed on the thin film transistor array panel. The same voltage as that of the common voltage wiring is applied.

また、薄膜トランジスタアレイパネルと共通電極基板との間にはセルギャップを維持するためのカラムスペーサ（ｃｏｌｕｍｎ ｓｐａｃｅｒ）が配置される。ところが、カラムスペーサ周辺では液晶配向が乱れるようになって光漏れが発生し、その周辺でテクスチャ（ｔｅｘｔｕｒｅ）が形成されて画質不良を招く恐れがある。これを防止するために、カラムスペーサ領域に光遮断のためのブラックマトリックスやゲート配線などの不透明膜を形成している。   A column spacer for maintaining a cell gap is disposed between the thin film transistor array panel and the common electrode substrate. However, the liquid crystal alignment is disturbed around the column spacer and light leakage occurs, and a texture may be formed around the column spacer, which may lead to poor image quality. In order to prevent this, an opaque film such as a black matrix or a gate wiring for blocking light is formed in the column spacer region.

韓国公開特許第２００６−０１０６３３３号公報Korean Published Patent No. 2006-0106333 韓国登録特許第１０−０４８９２８２号公報Korean Registered Patent No. 10-0489282

しかし、カラムスペーサ領域に形成されたブラックマトリックスやゲート配線などの不透明膜は、画素の開口率を減少させて、透過率を落とす要因となっていた。   However, an opaque film such as a black matrix or a gate wiring formed in the column spacer region reduces the aperture ratio of the pixel and decreases the transmittance.

本発明は上記課題に鑑みてなされたものであり、開口率の減少なしにカラムスペーサ領域の光を遮断する液晶表示装置を提供することにある。   The present invention has been made in view of the above problems, and it is an object of the present invention to provide a liquid crystal display device that blocks light in a column spacer region without reducing the aperture ratio.

本発明の一実施形態に係る液晶表示装置は、第１絶縁基板と第２絶縁基板との間の電圧差がゼロの場合、画面がブラック状態となるノーマリブラックモードであり、両絶縁基板の間にカラムスペーサが位置し、カラムスペーサが位置する領域は両絶縁基板間の電圧差がゼロとなるように、カラムスペーサが第１絶縁基板上に形成された共通電圧導電体パターン及び第２絶縁基板上に形成された共通電極と接触する。   The liquid crystal display device according to an embodiment of the present invention is a normally black mode in which the screen is in a black state when the voltage difference between the first insulating substrate and the second insulating substrate is zero. A column spacer is located between the common voltage conductor pattern formed on the first insulation substrate and the second insulation so that the voltage difference between the two insulation substrates is zero in the region where the column spacer is located. Contact with the common electrode formed on the substrate.

このような液晶表示装置は、第１絶縁基板上に形成された共通電圧導電体パターンと、前記共通電圧導電体パターンのすぐ上に形成されたカラムスペーサとを含み、第１絶縁基板と対向する第２絶縁基板上には共通電極が形成され、カラムスペーサが第２絶縁基板の共通電極と接触するノーマリブラックモードであってもよい。   Such a liquid crystal display device includes a common voltage conductor pattern formed on a first insulating substrate and a column spacer formed immediately above the common voltage conductor pattern, and faces the first insulating substrate. A normally black mode in which a common electrode is formed on the second insulating substrate and the column spacer is in contact with the common electrode of the second insulating substrate may be used.

または、このような液晶表示装置は、第２絶縁基板上の共通電極上に形成されたカラムスペーサが、第２絶縁基板と対向する第１絶縁基板上に形成された共通電圧導電体パターンと接触するノーマリブラックモードであってもよい。   Alternatively, in such a liquid crystal display device, the column spacer formed on the common electrode on the second insulating substrate is in contact with the common voltage conductor pattern formed on the first insulating substrate facing the second insulating substrate. A normally black mode may be used.

共通電圧導電体パターンは透明なものであってもよい。   The common voltage conductor pattern may be transparent.

共通電圧導電体パターンとゲート配線及びデータ配線などの不透明金属配線との間には、有機膜またはカラーフィルタなどを形成してもよい。   An organic film or a color filter may be formed between the common voltage conductor pattern and opaque metal wiring such as gate wiring and data wiring.

前記共通電圧導電体パターンの広さは前記カラムスペーサの底面が占める領域より広くしてもよい。   The common voltage conductor pattern may be wider than a region occupied by a bottom surface of the column spacer.

前記カラムスペーサの底面が占める領域は不透明金属配線と重ならない部分を含んでもよい。   The region occupied by the bottom surface of the column spacer may include a portion that does not overlap the opaque metal wiring.

本発明の一実施形態に係る液晶表示装置は、両絶縁基板の電圧差がゼロの場合、画面がブラック状態となるノーマリブラックモードの表示装置において、第１絶縁基板上に同一の電圧が印加される共通電圧導電体パターンを形成し、前記共通電圧導電体パターンのすぐ上にカラムスペーサを形成し、第１絶縁基板と対向する第２絶縁基板上には第１絶縁基板上の共通電圧配線と同一の電圧が印加される共通電極を形成し、カラムスペーサが第２絶縁基板の共通電極と接触してもよい。   The liquid crystal display device according to an embodiment of the present invention applies the same voltage to the first insulating substrate in a normally black mode display device in which the screen is in a black state when the voltage difference between the two insulating substrates is zero. A common voltage conductor pattern is formed, a column spacer is formed immediately above the common voltage conductor pattern, and a common voltage wiring on the first insulating substrate is disposed on the second insulating substrate facing the first insulating substrate. A common electrode to which the same voltage is applied may be formed, and the column spacer may be in contact with the common electrode of the second insulating substrate.

したがって、カラムスペーサは第１絶縁基板上の共通電圧導電体パターンと第２絶縁基板上の共通電極との間に位置し、カラムスペーサの上部と下部には常に同一の電圧が印加されるので、カラムスペーサの底面が占める領域はノーマリブラックモードの表示装置で常に画面がブラック状態を実現するようになり、これによって別途の光遮断パターンを不要にしてもよい。   Therefore, the column spacer is positioned between the common voltage conductor pattern on the first insulating substrate and the common electrode on the second insulating substrate, and the same voltage is always applied to the upper and lower portions of the column spacer. The area occupied by the bottom surface of the column spacer is a normally black mode display device so that the screen always realizes a black state, and thus a separate light blocking pattern may be unnecessary.

また、共通電圧が印加される共通電圧導電体パターンは、第１絶縁基板上の配向膜のすぐ下に位置する画素電極と同一の透明電極で形成して、共通電圧導電体パターンがカラムスペーサを通じて共通電極と導通することで、第１絶縁基板の共通電圧導電体パターンと第２絶縁基板の共通電極との間に電圧差が発生するのを防止する。   In addition, the common voltage conductor pattern to which the common voltage is applied is formed of the same transparent electrode as the pixel electrode located immediately below the alignment film on the first insulating substrate, and the common voltage conductor pattern passes through the column spacer. Conduction with the common electrode prevents a voltage difference from occurring between the common voltage conductor pattern of the first insulating substrate and the common electrode of the second insulating substrate.

共通電圧導電体パターンは、カラムスペーサ全体を覆うために、カラムスペーサの底面が占める領域より大きく形成することが好ましい。   The common voltage conductor pattern is preferably formed larger than the region occupied by the bottom surface of the column spacer in order to cover the entire column spacer.

この時、共通電圧導電体パターンとゲート配線及びデータ配線などの不透明金属配線との間には、有機膜またはカラーフィルタなどの低誘電率膜を形成して、共通電圧導電体パターンと不透明金属配線とが重なるようにして、共通電圧導電体パターンの大きさが大きくなっても、これによる開口率の減少がないようにすることが好ましい。   At this time, a low dielectric constant film such as an organic film or a color filter is formed between the common voltage conductor pattern and the opaque metal wiring such as the gate wiring and the data wiring. It is preferable that the aperture ratio does not decrease even when the size of the common voltage conductor pattern increases.

このように、電圧を印加してカラムスペーサの底面が占める領域を常にブラック状態とするので、カラムスペーサの底面が占める領域には不透明金属配線が重ならなくてもよい。   As described above, since the area occupied by the bottom surface of the column spacer is always in a black state by applying a voltage, the opaque metal wiring does not have to overlap the area occupied by the bottom surface of the column spacer.

または、カラムスペーサの底面が占める領域に不透明金属配線が重なる場合においても、カラムスペーサの底面が占める領域と重なる不透明金属配線の大きさがカラムスペーサの底面が占める領域より小さくてもよい。   Alternatively, even when the opaque metal wiring overlaps the region occupied by the bottom surface of the column spacer, the size of the opaque metal wiring overlapping the region occupied by the bottom surface of the column spacer may be smaller than the region occupied by the bottom surface of the column spacer.

本発明によれば、開口率の減少なしにカラムスペーサ領域の光を遮断する液晶表示装置を提供することができる。   According to the present invention, it is possible to provide a liquid crystal display device that blocks light in the column spacer region without reducing the aperture ratio.

本発明の一実施形態に係る液晶表示装置を示す概念図である。It is a conceptual diagram which shows the liquid crystal display device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る液晶表示装置を示す配置図である。1 is a layout view showing a liquid crystal display device according to an embodiment of the present invention. 図２のＩＩＩ−ＩＩＩ’線に沿った断面図である。FIG. 3 is a cross-sectional view taken along line III-III ′ in FIG. 2. 本発明の他の実施形態に係る液晶表示装置を示す配置図である。FIG. 6 is a layout view showing a liquid crystal display device according to another embodiment of the present invention. 図４のＶ−Ｖ’線に沿った断面図である。FIG. 5 is a cross-sectional view taken along line V-V ′ of FIG. 4. 本発明の他の実施形態に係る液晶表示装置を示す配置図である。FIG. 6 is a layout view showing a liquid crystal display device according to another embodiment of the present invention. 図６のＶＩＩ−ＶＩＩ’線に沿った断面図である。FIG. 7 is a cross-sectional view taken along line VII-VII ′ in FIG. 6.

添付した図面を参照して、本発明の実施形態について本発明が属する技術分野における通常の知識を有する者が容易に実施できるように詳細に説明する。本発明は種々の異なる実施形態に実現でき、ここで説明する実施形態に限定されない。図面において、本発明を明確に説明するために説明上不必要な部分は省略し、明細書の全体にわたって同一または類似する構成要素に対しては同一の符号が付されている。また、広く知られている公知技術の場合、その具体的な説明は省略する。   DETAILED DESCRIPTION Exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily implement the embodiments. The invention can be implemented in various different embodiments and is not limited to the embodiments described herein. In the drawings, parts unnecessary for the description are omitted in order to clearly describe the present invention, and the same or similar components are denoted by the same reference numerals throughout the specification. Further, in the case of a publicly known technique, a specific description thereof is omitted.

図面において、種々の層及び領域を明確に表現するために厚さを誇張して示した。層、膜、領域、パネルなどの部分が他の部分の“上に”あるというとき、これは他の部分の“すぐ上に”ある場合だけでなく、その中間に他の部分がある場合も含む。一方、ある部分が他の部分の“すぐ上に”あるという時には、中間に他の部分がないことを意味する。反対に、層、膜、領域、板などの部分が他の部分の“下に”あるという時、これは他の部分の“下に”ある場合だけでなく、その中間に他の部分がある場合も含む。一方、ある部分が他の部分の“すぐ下に”あるという時には、中間に他の部分がないことを意味する。   In the drawings, the thickness is exaggerated in order to clearly represent the various layers and regions. When a layer, film, region, panel, or other part is “on top” of another part, this is not only when it is “immediately above” another part, but also when there is another part in the middle Including. On the other hand, when a part is “just above” another part, it means that there is no other part in the middle. Conversely, when a layer, film, region, plate, or other part is “under” another part, this is not only when it is “under” another part, but there is another part in the middle Including cases. On the other hand, when a part is “just below” another part, it means that there is no other part in the middle.

また、本発明の実施形態において、第１絶縁基板の最上層と第２絶縁基板の最上層に設けられた配向膜は考慮しなかった。したがって、“共通電圧導電体パターンまたは共通電極と接触するという時には、実際には共通電圧導電体パターンまたは共通電極の上に設けられた配向膜と接触する”ということを意味しうる。   In the embodiment of the present invention, the alignment film provided on the uppermost layer of the first insulating substrate and the uppermost layer of the second insulating substrate is not considered. Therefore, it may mean “when it comes into contact with the common voltage conductor pattern or the common electrode, it actually contacts with the alignment film provided on the common voltage conductor pattern or the common electrode”.

以下、本発明の一実施形態に係る液晶表示装置用の薄膜トランジスタアレイパネルについて、図１〜図３を参照して詳細に説明する。   Hereinafter, a thin film transistor array panel for a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to FIGS.

図１は、本発明の一実施形態に係る液晶表示装置を示す概念図である。   FIG. 1 is a conceptual diagram showing a liquid crystal display device according to an embodiment of the present invention.

液晶表示装置は、画素電極ＰＥと共通電極ＣＥなど電界生成電極（ｆｉｅｌｄ ｇｅｎｅｒａｔｉｎｇ ｅｌｅｃｔｒｏｄｅ）が形成されている二枚の表示板１００、２００及びその間に挿入されている液晶層（図示せず）を含む。液晶表示装置は、画素電極ＰＥと共通電極ＣＥなど電界生成電極に電圧を印加して、液晶層に電界を生成し、これを通じて液晶層の液晶分子の方向を決定して入射光の偏光を制御することによって、映像を表示する。   The liquid crystal display device includes two display panels 100 and 200 on which field generating electrodes such as a pixel electrode PE and a common electrode CE are formed, and a liquid crystal layer (not shown) inserted therebetween. . The liquid crystal display device applies a voltage to the electric field generating electrode such as the pixel electrode PE and the common electrode CE to generate an electric field in the liquid crystal layer, thereby determining the direction of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light. By doing so, an image is displayed.

垂直配向方式（ｖｅｒｔｉｃａｌｌｙ ａｌｉｇｎｅｄ；ＶＡ）モードなどのノーマリブラックモード（ｎｏｒｍａｌｌｙ ｂｌａｃｋ ｍｏｄｅ）の液晶表示装置においては、二つの表示板の間の電圧差がゼロとなる場合、ブラック画面が実現される。   In a normally black mode liquid crystal display device such as a vertically aligned (VA) mode, a black screen is realized when the voltage difference between the two display panels becomes zero.

液晶表示装置の二つの表示板は、薄膜トランジスタアレイパネル１００と共通電極基板２００などで構成されている。   The two display panels of the liquid crystal display device are composed of a thin film transistor array panel 100, a common electrode substrate 200, and the like.

薄膜トランジスタアレイパネル１００の上には、ゲート配線ＧＬ及びデータ配線ＤＬなどの信号線と、透明画素電極ＰＥなどが形成され、ゲート配線ＧＬまたはデータ配線ＤＬと同一の物質で共通電圧配線ＳＬが形成されている。   On the thin film transistor array panel 100, signal lines such as a gate line GL and a data line DL, a transparent pixel electrode PE, and the like are formed, and a common voltage line SL is formed using the same material as the gate line GL or the data line DL. ing.

共通電極基板の上には、カラーフィルタＣＦまたはブラックマトリックス（図示せず）が形成され、カラーフィルタまたは光遮断ブラックマトリックスの上には透明共通電極ＣＥが形成され、透明共通電極ＣＥには薄膜トランジスタアレイパネル１００の上の共通電圧配線ＳＬと同一の電圧が印加される。   A color filter CF or a black matrix (not shown) is formed on the common electrode substrate, a transparent common electrode CE is formed on the color filter or the light blocking black matrix, and a thin film transistor array is formed on the transparent common electrode CE. The same voltage as the common voltage line SL on the panel 100 is applied.

また、薄膜トランジスタアレイパネル１００と共通電極基板２００との間にはセルギャップを維持するためのカラムスペーサ（図示せず）が配置される。   A column spacer (not shown) for maintaining a cell gap is disposed between the thin film transistor array panel 100 and the common electrode substrate 200.

次に、本発明の一実施形態に係る薄膜トランジスタアレイパネル１００について、図２及び図３を参照して詳細に説明する。   Next, a thin film transistor array panel 100 according to an embodiment of the present invention will be described in detail with reference to FIGS.

図２は、本発明の一実施形態に係る液晶表示装置を示す配置図であり、図３は、図２のＩＩＩ−ＩＩＩ’線に沿った断面図である。   FIG. 2 is a layout view showing a liquid crystal display device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along the line III-III 'of FIG.

まず、薄膜トランジスタアレイパネル１００について説明する。   First, the thin film transistor array panel 100 will be described.

薄膜トランジスタアレイパネル１００は、絶縁基板１１０、絶縁基板１１０の上にゲート配線３００と共通電圧配線３０１、３０２が形成されている。ゲート配線３００の形成時に共通電圧配線３０１、３０２を同時に形成するが、このとき、次の工程で形成されるカラムスペーサ３１１の周辺を覆うために配線の幅を広く形成する必要がない。   In the thin film transistor array panel 100, an insulating substrate 110 and gate wiring 300 and common voltage wirings 301 and 302 are formed on the insulating substrate 110. The common voltage wirings 301 and 302 are formed at the same time when the gate wiring 300 is formed. At this time, it is not necessary to widen the wiring width to cover the periphery of the column spacer 311 formed in the next step.

ゲート配線３００と共通電圧配線３０１、３０２の上には第１絶縁膜３０３が形成され、第１絶縁膜３０３の上にはアモルファスシリコン（ａｍｏｒｐｈｏｕｓ ｓｉｌｉｃｏｎ）などからなる半導体層３０４が形成されている。半導体層３０４の上にはｎ型不純物でドーピングされたアモルファスシリコンなどからなるオーミックコンタクト（ｏｈｍｉｃ ｃｏｎｔａｃｔ）層３１６が形成されている。オーミックコンタクト層３１６の上には金属からなるデータ線、ソース電極、ドレイン電極３２２、３２３、及び降圧電極３２４を含むデータ配線３０５が形成されている。データ配線３０５の上には第２絶縁膜３０６が形成され、第２絶縁膜３０６の上には第３絶縁膜３０７が形成されている。第１絶縁膜３０３と第２絶縁膜３０６は、窒化ケイ素（ＳｉＮｘ）、酸化ケイ素（ＳｉＯ２）などの無機物質で形成してもよく、第３絶縁膜３０７は有機物質で形成してもよい。第１絶縁膜３０３、第２絶縁膜３０６、及び第３絶縁膜３０７は、共通電圧配線３０２を露出するコンタクトホール３０８を有し、第２絶縁膜３０６と第３絶縁膜３０７は二つのドレイン電極３２２、３２３を露出するコンタクトホール３１７、３１８を有する。 A first insulating film 303 is formed on the gate wiring 300 and the common voltage wirings 301 and 302, and a semiconductor layer 304 made of amorphous silicon or the like is formed on the first insulating film 303. An ohmic contact layer 316 made of amorphous silicon doped with n-type impurities is formed on the semiconductor layer 304. On the ohmic contact layer 316, a data line 305 including a metal data line, a source electrode, drain electrodes 322 and 323, and a step-down electrode 324 is formed. A second insulating film 306 is formed on the data wiring 305, and a third insulating film 307 is formed on the second insulating film 306. The first insulating film 303 and the second insulating film 306 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiO 2 ), and the third insulating film 307 may be formed of an organic material. . The first insulating film 303, the second insulating film 306, and the third insulating film 307 have a contact hole 308 that exposes the common voltage wiring 302, and the second insulating film 306 and the third insulating film 307 have two drain electrodes. Contact holes 317 and 318 exposing the holes 322 and 323 are provided.

第３絶縁膜３０７の上には透明な導電物質からなる画素電極３０９、３１９と共通電圧導電体パターン３１０が形成されている。共通電圧導電体パターン３１０はコンタクトホール３１８を通じて共通電圧配線３０２と電気的に接続され、二つの画素電極３０９、３１９はそれぞれコンタクトホール３１７、３１８を通じて二つのドレイン電極３２２、３２３と電気的に接続されている。   On the third insulating film 307, pixel electrodes 309 and 319 and a common voltage conductor pattern 310 made of a transparent conductive material are formed. The common voltage conductor pattern 310 is electrically connected to the common voltage wiring 302 through the contact hole 318, and the two pixel electrodes 309 and 319 are electrically connected to the two drain electrodes 322 and 323 through the contact holes 317 and 318, respectively. ing.

共通電圧導電体パターン３１０の上にはカラムスペーサ３１１が形成されている。カラムスペーサ３１１は有機物質で形成してもよい。ここで、共通電圧導電体パターン３１０はカラムスペーサ領域全体を覆うために、カラムスペーサ３１１の底面より広く形成してもよい。   A column spacer 311 is formed on the common voltage conductor pattern 310. The column spacer 311 may be formed of an organic material. Here, the common voltage conductor pattern 310 may be formed wider than the bottom surface of the column spacer 311 to cover the entire column spacer region.

カラムスペーサ領域とは、カラムスペーサの底面が占める領域を意味する。   The column spacer region means a region occupied by the bottom surface of the column spacer.

カラムスペーサ３１１が位置した領域には不透明金属配線が配置されていないか、または配置されてもカラムスペーサ３１１と重なる不透明金属配線の広さをカラムスペーサの領域より小さくしてもよい。   In the region where the column spacer 311 is located, the opaque metal wiring is not arranged, or even if it is arranged, the width of the opaque metal wiring overlapping the column spacer 311 may be made smaller than the column spacer region.

この時、共通電圧導電体パターン３１０と、ゲート配線３００及びデータ配線３０５などの不透明金属配線との間には、有機膜またはカラーフィルタ層などの低誘電率膜を形成して、共通電圧導電体パターン３１０と不透明金属配線が重なるように、共通電圧導電体パターン３１０の大きさが大きくなっても、これによる開口率の減少がないようにする。   At this time, a low dielectric constant film such as an organic film or a color filter layer is formed between the common voltage conductor pattern 310 and the opaque metal wiring such as the gate wiring 300 and the data wiring 305, and the common voltage conductor is formed. As the size of the common voltage conductor pattern 310 is increased so that the pattern 310 and the opaque metal wiring overlap, the aperture ratio is not reduced by this.

次に、共通電極基板２００について説明する。   Next, the common electrode substrate 200 will be described.

共通電極基板２００は、絶縁基板１０１、絶縁基板１０１の上に順次に形成されているカラーフィルタ３１２、オーバーコート層３１３、及び共通電極３１４を含む。   The common electrode substrate 200 includes an insulating substrate 101, a color filter 312, an overcoat layer 313, and a common electrode 314 that are sequentially formed on the insulating substrate 101.

共通電極基板２００と薄膜トランジスタアレイパネル１００とを整列して結合した状態で、カラムスペーサ３１１は共通電極基板２００と薄膜トランジスタアレイパネル１００の間の間隔を維持する。   In a state where the common electrode substrate 200 and the thin film transistor array panel 100 are aligned and coupled, the column spacer 311 maintains a distance between the common electrode substrate 200 and the thin film transistor array panel 100.

以上のように、カラムスペーサ３１１の上部及び下部に同一の電圧が印加される共通電極３１４と共通電圧導電体パターン３１０とを形成すれば、カラムスペーサ３１１周辺の液晶分子が垂直配向状態を維持してブラック状態が維持される。これによって、カラムスペーサ３１１を通過する光の偏光が変化しないので、直交に配置された上下偏光板によって全て遮断されて、ブラック状態が維持される。   As described above, if the common electrode 314 and the common voltage conductor pattern 310 to which the same voltage is applied are formed above and below the column spacer 311, the liquid crystal molecules around the column spacer 311 maintain the vertical alignment state. The black state is maintained. Thereby, since the polarization of the light passing through the column spacer 311 does not change, the light is completely blocked by the upper and lower polarizing plates arranged orthogonally, and the black state is maintained.

以上、説明したように、一つの画素に同一の第１薄膜トランジスタが接続されている二つの画素電極３０９、３１９を配置して、二つの画素電極３０９、３１９に一定の電圧差を形成するために、一つの画素電極３０９に第２薄膜トランジスタを通じて降圧電極３２４を接続した構造の薄膜トランジスタアレイパネル１００に共通電圧導電体パターン３１０を適用した場合について説明したが、他の構造の薄膜トランジスタアレイパネル１００にも共通電圧導電体パターン３１０を適用してもよい。以下、多様に変形する実施形態の中で２つを説明する。   As described above, in order to form a certain voltage difference between the two pixel electrodes 309 and 319 by arranging the two pixel electrodes 309 and 319 having the same first thin film transistor connected to one pixel. In the above description, the common voltage conductor pattern 310 is applied to the thin film transistor array panel 100 having the structure in which the step-down electrode 324 is connected to one pixel electrode 309 through the second thin film transistor. The voltage conductor pattern 310 may be applied. Hereinafter, two of the various modified embodiments will be described.

図４は、本発明の他の実施形態に係る液晶表示装置を示す配置図であり、図５は、図４のＶ−Ｖ’線に沿った断面図である。   FIG. 4 is a layout view showing a liquid crystal display device according to another embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line V-V ′ of FIG. 4.

絶縁基板１１０の上にゲート配線３００と共通電圧配線３０２が形成されている。共通電圧配線３０２は隣接した二つのゲート配線３００から等間隔に位置し、幅が拡張された部分を有する。   A gate wiring 300 and a common voltage wiring 302 are formed on the insulating substrate 110. The common voltage line 302 is located at an equal interval from two adjacent gate lines 300 and has a portion whose width is expanded.

ゲート配線３００と共通電圧配線３０２の上には第１絶縁膜３０３が形成され、第１絶縁膜３０３の上にはアモルファスシリコンなどからなる半導体層３０４が形成されている。半導体層３０４の上にはｎ型不純物でドーピングされたアモルファスシリコンなどからなるオーミックコンタクト層３１６が形成されている。オーミックコンタクト層３１６の上には金属からなるデータ線、ソース電極、及びドレイン電極３２２を含むデータ配線３０５が形成されている。データ配線３０５の上には第２絶縁膜３０６が形成され、第２絶縁膜３０６の上には第３絶縁膜３０７が形成されている。第１絶縁膜３０３と第２絶縁膜３０６は窒化ケイ素（ＳｉＮｘ）、酸化ケイ素（ＳｉＯ２）などの無機物質で形成してもよく、第３絶縁膜３０７は有機物質で形成してもよい。第２絶縁膜３０６と第３絶縁膜３０７はドレイン電極３２２を露出するコンタクトホール３１７を有する。 A first insulating film 303 is formed on the gate wiring 300 and the common voltage wiring 302, and a semiconductor layer 304 made of amorphous silicon or the like is formed on the first insulating film 303. On the semiconductor layer 304, an ohmic contact layer 316 made of amorphous silicon doped with an n-type impurity is formed. On the ohmic contact layer 316, a data line 305 including a metal data line, a source electrode, and a drain electrode 322 is formed. A second insulating film 306 is formed on the data wiring 305, and a third insulating film 307 is formed on the second insulating film 306. The first insulating film 303 and the second insulating film 306 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiO 2 ), and the third insulating film 307 may be formed of an organic material. The second insulating film 306 and the third insulating film 307 have a contact hole 317 exposing the drain electrode 322.

第３絶縁膜３０７の上には透明な導電物質からなる画素電極３０９と共通電圧導電体パターン３１０が形成されている。画素電極３０９はコンタクトホール３１７を通じてドレイン電極３２２と電気的に接続され、共通電圧配線３０２を中心として対称をなす切開部を有する。共通電圧導電体パターン３１０はデータ線に沿って延長され、共通電圧配線３０２の幅が拡張された部分と重なる突出部を含む。共通電圧導電体パターン３１０は画面表示領域を逸脱した周辺領域にまで延長されており、周辺領域に形成されている配線や駆動回路を通じて共通電圧配線３０２と同一の電圧が印加されるように配線されている。   A pixel electrode 309 and a common voltage conductor pattern 310 made of a transparent conductive material are formed on the third insulating film 307. The pixel electrode 309 is electrically connected to the drain electrode 322 through the contact hole 317, and has a cutout portion that is symmetric about the common voltage wiring 302. The common voltage conductor pattern 310 is extended along the data line, and includes a protrusion that overlaps the extended portion of the common voltage wiring 302. The common voltage conductor pattern 310 is extended to a peripheral area that deviates from the screen display area, and is wired so that the same voltage as the common voltage wiring 302 is applied through a wiring and a drive circuit formed in the peripheral area. ing.

共通電極基板２００は、絶縁基板１０１、絶縁基板１０１の上に順次形成されるカラーフィルタ３１２、オーバーコート層３１３、及び共通電極３１４を含み、共通電極３１４のすぐ上にはカラムスペーサ３１１が形成されている。カラムスペーサ３１１は薄膜トランジスタアレイパネル上に形成された共通電圧導電体パターン３１０と接触するように配置されている。   The common electrode substrate 200 includes an insulating substrate 101, a color filter 312 that is sequentially formed on the insulating substrate 101, an overcoat layer 313, and a common electrode 314. A column spacer 311 is formed immediately above the common electrode 314. ing. The column spacer 311 is disposed so as to contact the common voltage conductor pattern 310 formed on the thin film transistor array panel.

図６は、本発明の他の実施形態に係る液晶表示装置を示す配置図であり、図７は、図６のＶＩＩ−ＶＩＩ’線に沿った断面図である。   6 is a layout view showing a liquid crystal display device according to another embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line VII-VII ′ of FIG.

絶縁基板１１０の上にはゲート配線３００と共通電圧配線３０２が形成されている。共通電圧配線３０２は隣接した二つのゲート配線３００から等間隔に位置し、上下に延びて画素電極３０９のデータ線と隣接した辺と重なる枝部（ｂｒａｎｃｈ ｐａｒｔ）を有する。   A gate wiring 300 and a common voltage wiring 302 are formed on the insulating substrate 110. The common voltage line 302 is located at equal intervals from two adjacent gate lines 300 and has a branch part that extends vertically and overlaps a side adjacent to the data line of the pixel electrode 309.

ゲート配線３００と共通電圧配線３０２の上には第１絶縁膜３０３が形成され、第１絶縁膜３０３の上にはアモルファスシリコンなどからなる半導体層（図示せず）が形成されている。半導体層の上にはｎ型不純物でドーピングされたアモルファスシリコンなどからなるオーミックコンタクト層が形成されている。オーミックコンタクト層の上には金属からなるデータ線、ソース電極、及びドレイン電極３２２を含むデータ配線３０５が形成されている。データ配線３０５の上には第２絶縁膜３０６が形成され、第２絶縁膜３０６の上には第３絶縁膜３０７が形成されている。第１絶縁膜３０３と第２絶縁膜３０６には、窒化ケイ素（ＳｉＮｘ）、酸化ケイ素（ＳｉＯ２）などの無機物質で形成してもよく、第３絶縁膜３０７は有機物質で形成してもよい。第１絶縁膜３０３、第２絶縁膜３０６、及び第３絶縁膜３０７は共通電圧配線３０２を露出するコンタクトホール３０８を有し、第２絶縁膜３０６と第３絶縁膜３０７はドレイン電極３２２を露出するコンタクトホール３１７を有する。 A first insulating film 303 is formed on the gate wiring 300 and the common voltage wiring 302, and a semiconductor layer (not shown) made of amorphous silicon or the like is formed on the first insulating film 303. An ohmic contact layer made of amorphous silicon doped with an n-type impurity is formed on the semiconductor layer. A data line 305 including a data line made of metal, a source electrode, and a drain electrode 322 is formed on the ohmic contact layer. A second insulating film 306 is formed on the data wiring 305, and a third insulating film 307 is formed on the second insulating film 306. The first insulating film 303 and the second insulating film 306 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiO 2 ), and the third insulating film 307 may be formed of an organic material. Good. The first insulating film 303, the second insulating film 306, and the third insulating film 307 have contact holes 308 that expose the common voltage wiring 302, and the second insulating film 306 and the third insulating film 307 expose the drain electrode 322. A contact hole 317 is formed.

第３絶縁膜３０７の上には透明な導電物質からなる画素電極３０９と共通電圧導電体パターン３１０が形成されている。画素電極３０９はコンタクトホール３１７を通じてドレイン電極３２２と電気的に接続されており、共通電圧配線３０２を中心として対称をなす切開部を有する。共通電圧導電体パターン３１０は共通電圧配線３０２と重なる位置に島型に形成され、コンタクトホール３１８を通じて共通電圧配線３０２と電気的に接続されている。したがって、共通電圧導電体パターン３１０には共通電圧配線３０２と同一の電圧が印加される。   A pixel electrode 309 and a common voltage conductor pattern 310 made of a transparent conductive material are formed on the third insulating film 307. The pixel electrode 309 is electrically connected to the drain electrode 322 through the contact hole 317, and has a cutout portion that is symmetric about the common voltage wiring 302. The common voltage conductor pattern 310 is formed in an island shape so as to overlap with the common voltage wiring 302 and is electrically connected to the common voltage wiring 302 through the contact hole 318. Therefore, the same voltage as the common voltage wiring 302 is applied to the common voltage conductor pattern 310.

共通電圧導電体パターン３１０のすぐ上には有機物質からなるカラムスペーサ３１１が形成されている。   A column spacer 311 made of an organic material is formed immediately above the common voltage conductor pattern 310.

共通電極基板は、絶縁基板１０１と、その上に順次に形成されているカラーフィルタ３１２、オーバーコート層３１３、及び共通電極３１４を含む。   The common electrode substrate includes an insulating substrate 101, a color filter 312, an overcoat layer 313, and a common electrode 314 that are sequentially formed thereon.

本発明の単純な変形や変更は、この分野の通常の知識を有する者によって容易に実施でき、このような変形や変更は全て本発明の領域に含まれるものとみなされる。   Simple variations and modifications of the present invention can be easily implemented by those having ordinary knowledge in the field, and all such variations and modifications are considered to be within the scope of the present invention.

１００ 薄膜トランジスタアレイパネル
１０１ 絶縁基板
２００ 共通電極基板
３０１、３０２ 共通電圧配線
３０３、３０６、３０７ 第１、２、３絶縁膜
３０９、３１９ 画素電極
３１０ 共通電圧導電体パターン
３１７、３１８ コンタクトホール
３１２ カラーフィルタ
３１３ オーバーコート
３１４ 共通電極
３２２、３２３ ドレイン電極 100 Thin-film transistor array panel 101 Insulating substrate 200 Common electrode substrate 301, 302 Common voltage wiring 303, 306, 307 First, second, third insulating film 309, 319 Pixel electrode 310 Common voltage conductor pattern 317, 318 Contact hole 312 Color filter 313 Overcoat 314 Common electrode 322, 323 Drain electrode

Claims (18)

共通電圧導電体パターンを含む第１絶縁基板と、
共通電極を含む第２絶縁基板と、
前記第１絶縁基板と前記第２絶縁基板との間の間隔を維持して、前記共通電圧導電体パターン及び前記共通電極と重なる位置に配置されるカラムスペーサと、を含み、
前記共通電圧導電体パターンと前記共通電極には同一の電圧が印加されるノーマリブラックモードであることを特徴とする液晶表示装置。 A first insulating substrate including a common voltage conductor pattern;
A second insulating substrate including a common electrode;
A column spacer disposed at a position overlapping the common voltage conductor pattern and the common electrode while maintaining a gap between the first insulating substrate and the second insulating substrate;
2. A liquid crystal display device according to claim 1, wherein the liquid crystal display device is a normally black mode in which the same voltage is applied to the common voltage conductor pattern and the common electrode. 前記共通電圧導電体パターンは透明であることを特徴とする請求項１に記載の液晶表示装置。   The liquid crystal display device according to claim 1, wherein the common voltage conductor pattern is transparent. 前記共通電圧導電体パターンの広さは前記カラムスペーサの底面が占める領域より広いことを特徴とする請求項２に記載の液晶表示装置。   3. The liquid crystal display device according to claim 2, wherein the common voltage conductor pattern is wider than a region occupied by a bottom surface of the column spacer. 前記カラムスペーサの底面が占める領域は不透明金属配線と重ならない部分を含むことを特徴とする請求項３に記載の液晶表示装置。   4. The liquid crystal display device according to claim 3, wherein the area occupied by the bottom surface of the column spacer includes a portion that does not overlap the opaque metal wiring. 前記不透明金属配線はゲート配線及びデータ配線を含み、前記共通電圧導電体パターンと前記ゲート配線及び前記データ配線との間には有機膜またはカラーフィルタが配置されることを特徴とする請求項４に記載の液晶表示装置。   5. The opaque metal line includes a gate line and a data line, and an organic film or a color filter is disposed between the common voltage conductor pattern and the gate line and the data line. The liquid crystal display device described. 前記ゲート配線と同一層に形成される共通電極配線と、をさらに含み、
前記有機膜またはカラーフィルタは前記共通電極配線を露出するコンタクトホールを有し、前記共通電圧導電体パターンは前記コンタクトホールを通じて前記共通電極配線と電気的に接続されることを特徴とする請求項５に記載の液晶表示装置。 A common electrode wiring formed in the same layer as the gate wiring,
6. The organic film or the color filter has a contact hole exposing the common electrode wiring, and the common voltage conductor pattern is electrically connected to the common electrode wiring through the contact hole. A liquid crystal display device according to 1. 第１薄膜トランジスタに接続される第１画素電極及び第２画素電極と、
前記第２画素電極に接続される第２薄膜トランジスタと、
前記第２薄膜トランジスタに接続される降圧電極と、
をさらに含むことを特徴とする請求項６に記載の液晶表示装置。 A first pixel electrode and a second pixel electrode connected to the first thin film transistor;
A second thin film transistor connected to the second pixel electrode;
A step-down electrode connected to the second thin film transistor;
The liquid crystal display device according to claim 6, further comprising: 前記共通電圧導電体パターンの広さは前記カラムスペーサの底面が占める領域より広いことを特徴とする請求項１に記載の液晶表示装置。   2. The liquid crystal display device according to claim 1, wherein the common voltage conductor pattern is wider than a region occupied by a bottom surface of the column spacer. 前記カラムスペーサの底面が占める領域は不透明金属配線と重ならない部分を含むことを特徴とする請求項８に記載の液晶表示装置。   9. The liquid crystal display device according to claim 8, wherein the area occupied by the bottom surface of the column spacer includes a portion that does not overlap with the opaque metal wiring. 前記不透明金属配線はゲート配線及び前記データ配線を含み、前記共通電圧導電体パターンと前記ゲート配線及び前記データ配線との間には有機膜またはカラーフィルタが配置されることを特徴とする請求項９に記載の液晶表示装置。   10. The opaque metal line includes a gate line and the data line, and an organic film or a color filter is disposed between the common voltage conductor pattern and the gate line and the data line. A liquid crystal display device according to 1. 前記カラムスペーサの底面が占める領域は不透明金属配線と重ならない部分を含むことを特徴とする請求項１に記載の液晶表示装置。   The liquid crystal display device according to claim 1, wherein a region occupied by a bottom surface of the column spacer includes a portion that does not overlap an opaque metal wiring. 前記不透明金属配線はゲート配線及び前記データ配線を含み、前記共通電圧導電体パターンと前記ゲート配線及び前記データ配線との間には有機膜またはカラーフィルタが配置されることを特徴とする請求項１１に記載の液晶表示装置。   12. The opaque metal line includes a gate line and the data line, and an organic film or a color filter is disposed between the common voltage conductor pattern and the gate line and the data line. A liquid crystal display device according to 1. 前記不透明金属配線はゲート配線及び前記データ配線を含み、前記共通電圧導電体パターンと前記ゲート配線及び前記データ配線との間には有機膜またはカラーフィルタが配置されることを特徴とする請求項１に記載の液晶表示装置。   2. The opaque metal line includes a gate line and the data line, and an organic film or a color filter is disposed between the common voltage conductor pattern and the gate line and the data line. A liquid crystal display device according to 1. 前記カラムスペーサの底面が占める領域は不透明金属配線と重ならない部分を含むことを特徴とする請求項２に記載の液晶表示装置。   3. The liquid crystal display device according to claim 2, wherein the area occupied by the bottom surface of the column spacer includes a portion that does not overlap the opaque metal wiring. 前記不透明金属配線はゲート配線及び前記データ配線を含み、前記共通電圧導電体パターンと前記ゲート配線及び前記データ配線との間には有機膜またはカラーフィルタが配置されることを特徴とする請求項１４に記載の液晶表示装置。   15. The opaque metal line includes a gate line and the data line, and an organic film or a color filter is disposed between the common voltage conductor pattern and the gate line and the data line. A liquid crystal display device according to 1. 前記不透明金属配線はゲート配線及び前記データ配線を含み、前記共通電圧導電体パターンと前記ゲート配線及び前記データ配線との間には有機膜またはカラーフィルタが配置されることを特徴とする請求項２に記載の液晶表示装置。   3. The opaque metal line includes a gate line and the data line, and an organic film or a color filter is disposed between the common voltage conductor pattern and the gate line and the data line. A liquid crystal display device according to 1. 前記ゲート配線と同一層に形成される共通電極配線と、をさらに含み、
前記有機膜またはカラーフィルタは前記共通電極配線を露出するコンタクトホールを有し、前記共通電圧導電体パターンは前記コンタクトホールを通じて前記共通電極配線と電気的に接続されることを特徴とする請求項３に記載の液晶表示装置。 A common electrode wiring formed in the same layer as the gate wiring,
4. The organic film or the color filter has a contact hole exposing the common electrode wiring, and the common voltage conductor pattern is electrically connected to the common electrode wiring through the contact hole. A liquid crystal display device according to 1. 前記不透明金属配線はゲート配線及び前記データ配線を含み、前記共通電圧導電体パターンと前記ゲート配線及び前記データ配線との間には有機膜またはカラーフィルタが配置されることを特徴とする請求項８に記載の液晶表示装置。   9. The opaque metal line includes a gate line and the data line, and an organic film or a color filter is disposed between the common voltage conductor pattern and the gate line and the data line. A liquid crystal display device according to 1.
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150083956A (en) 2014-01-10 2015-07-21 삼성디스플레이 주식회사 Display apparatus and method of manufacturing the same
US9939688B2 (en) 2015-12-01 2018-04-10 Wuhan China Star Optoelectronics Technology Co. Ltd. Liquid crystal display panel having photo spacers extending into openings defined by common electrode layer
CN105372881B (en) * 2015-12-01 2018-04-20 武汉华星光电技术有限公司 Liquid crystal display panel
KR102507718B1 (en) 2016-03-29 2023-03-09 삼성디스플레이 주식회사 Display device and manufacturing method thereof
JP2019101095A (en) * 2017-11-29 2019-06-24 シャープ株式会社 Liquid crystal panel
KR102530472B1 (en) * 2018-09-18 2023-05-09 삼성디스플레이 주식회사 Display device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000193984A (en) * 1998-12-25 2000-07-14 Sony Corp Liquid crystal light valve device
JP2002182221A (en) * 2000-12-18 2002-06-26 Hitachi Ltd Liquid crystal display device
US20080239225A1 (en) * 2007-04-02 2008-10-02 Innolux Display Corp. Liquid crystal panel having elements for electrically coupling common electrode and common lines
JP2009109656A (en) * 2007-10-29 2009-05-21 Nec Lcd Technologies Ltd Liquid crystal display device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2975570B2 (en) 1997-05-08 1999-11-10 シャープ株式会社 Active matrix display device
KR100489282B1 (en) 2003-06-17 2005-05-17 엘지.필립스 엘시디 주식회사 Thin Film Transistor Array Substrate And Fabricating Method Thereof
JP4679067B2 (en) 2004-04-23 2011-04-27 富士通株式会社 Liquid crystal display device
KR101107239B1 (en) * 2004-12-23 2012-01-25 엘지디스플레이 주식회사 Liquid Crystal Display Panel And Method Of Fabricating The Same
DE102005059789B4 (en) * 2004-12-23 2010-07-22 Lg Display Co., Ltd. Liquid crystal display device
KR101182318B1 (en) 2005-02-01 2012-09-20 엘지디스플레이 주식회사 In-Plane Switching mode Liquid Crystal Display Device and Method for Manufacturing the Same
KR100965572B1 (en) 2005-04-08 2010-06-23 엘지디스플레이 주식회사 Liquid Crystal Display Device
KR100740041B1 (en) 2005-06-30 2007-07-16 엘지.필립스 엘시디 주식회사 Liquid crystal panel having dual column spacer, and method for manufacturing the same
KR20070068577A (en) 2005-12-27 2007-07-02 엘지.필립스 엘시디 주식회사 Liquid crystal display panel and method of manufaturing the same
JP2007192944A (en) 2006-01-17 2007-08-02 Toshiba Matsushita Display Technology Co Ltd Liquid crystal display device and manufacturing method therefor
JP2008083291A (en) 2006-09-27 2008-04-10 Epson Imaging Devices Corp Liquid crystal display and electronic equipment
US9052550B2 (en) * 2006-11-29 2015-06-09 Beijing Boe Optoelectronics Technology Co., Ltd Thin film transistor liquid crystal display
US7812918B2 (en) * 2007-07-12 2010-10-12 Lg Display Co., Ltd. Liquid crystal display device and method for fabricating the same
TWI391735B (en) * 2009-07-06 2013-04-01 Au Optronics Corp Color filter array on pixel array substrate and display panel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000193984A (en) * 1998-12-25 2000-07-14 Sony Corp Liquid crystal light valve device
JP2002182221A (en) * 2000-12-18 2002-06-26 Hitachi Ltd Liquid crystal display device
US20080239225A1 (en) * 2007-04-02 2008-10-02 Innolux Display Corp. Liquid crystal panel having elements for electrically coupling common electrode and common lines
JP2009109656A (en) * 2007-10-29 2009-05-21 Nec Lcd Technologies Ltd Liquid crystal display device

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