JP3760008B2 - Liquid crystal panel substrate, liquid crystal panel using the same, and projection display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of an external input / output terminal of a liquid crystal panel used for an active matrix liquid crystal display device and a method for manufacturing the same, and in particular, a pixel electrode is driven by a polysilicon thin film transistor (hereinafter referred to as TFT) formed on a substrate. The present invention relates to a technique suitable for application to a liquid crystal panel for an active matrix liquid crystal display device, a substrate constituting the liquid crystal panel, and a method of manufacturing the same. The present invention further relates to a technique suitable for use in a projection display apparatus.
[0002]
[Prior art]
Conventionally, as an active matrix liquid crystal display device, pixel electrodes made of ITO (Indium-Tin Oxide) or the like are formed in a matrix on a glass substrate, and amorphous silicon or polysilicon is used corresponding to each pixel electrode. A liquid crystal display device having a configuration in which a TFT is formed and a liquid crystal is driven by applying a voltage to each pixel electrode by the TFT has been put into practical use.
[0003]
Of the active matrix liquid crystal display devices, devices using polysilicon TFTs are suitable for high integration because transistors forming peripheral circuits such as shift registers and drive circuits can be formed in the same process. Has been.
[0004]
In a conventional active matrix type liquid crystal display device using a polysilicon TFT, it becomes an external input / output terminal such as a connection terminal for connecting to an external drive IC or the like, or an inspection terminal to which a probe is contacted during inspection. An electrode called a pad is formed of the same aluminum layer or aluminum alloy layer as a conductive layer used for internal wiring (for example, a data line for supplying a voltage applied to the pixel electrode via each TFT).
[0005]
[Problems to be solved by the invention]
If the pad electrode is made of aluminum as described above, it may be corroded by the etching solution for patterning the ITO film or by sputtering during the formation of the ITO film, so the pad with the interlayer insulating film until the patterning of the ITO film is completed. There is a problem that the number of processes increases because it is necessary to perform etching to cover the electrode and remove the insulating film on the pad electrode after forming the pixel electrode made of the ITO film to open the hole.
[0006]
In the case of a pad electrode composed of an aluminum layer or an aluminum alloy layer, the tip of the probe is brought into contact with the pad electrode during probe inspection, and the surface of the pad electrode rises when it is cut off after completion of the inspection. It may turn up and form a protrusion.
[0007]
By the way, the inspection terminal may be formed not at the periphery of the substrate but at a position facing the portion of the counter substrate where the counter electrode is formed for the sake of layout. In such a case, if the above-described protrusion is generated on the surface of the pad electrode by the probe inspection, the protrusion may come into contact with the counter electrode provided on the counter substrate, so that a desired circuit operation may not be performed. Furthermore, the pixel electrodes arranged in a matrix form have a very narrow interval, and when there are many defects that short-circuit between adjacent pixel electrodes due to defective patterning, etc. An etching process called a regeneration process for separating the film may be performed again. In that case, since the aluminum constituting the pad electrode has poor etching resistance, the hole portion on the pad electrode is covered with a resist. It has been found that there is a problem that the etching solution penetrates along the protrusions and corrodes the pad electrode to cause a defective product.
[0008]
The present invention solves the above-mentioned problems, and an object of the present invention is to provide a pad electrode forming method that becomes a terminal capable of reducing the number of steps of the manufacturing process.
[0009]
Another object of the present invention is an active matrix type liquid crystal display device in which a protrusion is not formed on the surface of the electrode even when the tip of the probe contacts a pad electrode as an external terminal during probe inspection. It is to provide a high substrate.
[0010]
[Means for Solving the Problems]
A substrate for a liquid crystal panel according to the present invention includes a plurality of scanning lines and a plurality of data lines arranged in a matrix on the substrate, and a plurality of thin film transistors provided corresponding to the plurality of scanning lines and the plurality of data lines. And a liquid crystal panel substrate having a plurality of pixel electrodes provided corresponding to the plurality of thin film transistors, a terminal for connection with an inspection terminal or an external circuit, and a wiring connected to the terminal, The terminal includes a first pad electrode part formed of the same polysilicon layer as the gate electrode of the thin film transistor, and a second ITO film formed of the same ITO film as the pixel electrode on the surface of the first pad electrode part. It is composed of a pad electrode part, and the wiring is made of the same aluminum layer as the data line provided via an insulating film on the thin film transistor or an alloy layer thereof. Made is characterized in that it is connected via a first contact hole formed in the insulating film to the pad electrode portion.
[0011]
The substrate for a liquid crystal panel according to the present invention includes a plurality of scanning lines and a plurality of data lines arranged in a matrix on the substrate, and a plurality of scanning lines and a plurality of data lines provided corresponding to the plurality of scanning lines and the plurality of data lines. A thin film transistor, a plurality of pixel electrodes provided corresponding to the plurality of thin film transistors, a terminal for connection to an inspection terminal or an external circuit, and a wiring connected to the terminal The terminal is formed of a first pad electrode part formed of the same metal silicide layer as the gate electrode of the thin film transistor, and an ITO film same as the pixel electrode on the surface of the first pad electrode part. The wiring is composed of a second pad electrode portion, and the wiring is the same aluminum layer or the same as the data line provided via an insulating film on the thin film transistor. It is formed of an alloy layer, characterized in that it is connected via a first contact hole formed in the insulating film to the pad electrode portion.
[0012]
The method for manufacturing a substrate for a liquid crystal panel according to the present invention is provided corresponding to the plurality of scanning lines and the plurality of data lines arranged in a matrix on the substrate, and the plurality of scanning lines and the plurality of data lines. In a method for manufacturing a substrate for a liquid crystal panel, comprising: a plurality of thin film transistors; a plurality of pixel electrodes provided corresponding to the plurality of thin film transistors; and a terminal for inspection or an external circuit. Forming the active layer, forming the gate electrode of the thin film transistor and the first pad electrode constituting the terminal with the same polysilicon layer, and above the active layer, the gate electrode and the scanning line A step of forming a first interlayer insulating film; and a contact hole is formed in the first interlayer insulating film to be connected to the thin film transistor Simultaneously forming a data line, forming a contact hole in the first interlayer insulating film to form the wiring connected to the first pad electrode with the same material as the data line, and the data line and A step of forming a second interlayer insulating film on the wiring; and the pixel electrode comprising an ITO film connected to the thin film transistor by opening a contact hole in the second interlayer insulating film and the first interlayer insulating film At the same time, a contact hole is formed in the second interlayer insulating film and the first interlayer insulating film, and a second pad is formed on the surface of the first pad constituting the terminal with the same material as the pixel electrode. And a step of performing.
The method for manufacturing a liquid crystal panel substrate according to the present invention may be a metal silicide layer instead of the polysilicon layer having the above characteristics.
[0013]
According to the above-described means, since the pad electrode is made of an ITO film having a higher film strength than aluminum, the above-described protrusion is hardly generated on the surface of the pad electrode by the probe inspection, and is thereby provided on the counter substrate. Prevents vertical conduction failure caused by contact with the counter electrode. In general, pixel electrodes may be short-circuited due to residual resist during the ITO photolithography process, resulting in point defects. In such a case, the pixel electrode short-circuited portion is again masked for ITO pattern formation. Since the pad electrode is not corroded by the etching liquid by performing the photolithography process using the photolithography process, the regeneration process can be performed.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings while comparing a pixel portion and a pad electrode portion.
[0015]
1 and 2 show a plan layout and a sectional view of a first embodiment of a liquid crystal panel substrate to which the present invention is applied. 1A and 2A show the layout and cross-sectional structure of one pixel portion of the pixels arranged in a matrix, and FIGS. 1B and 2B show the pad electrode portion. A layout and a cross-sectional structure are shown. 2A is a cross-sectional structure taken along line AA in FIG. 1A, and FIG. 2B is a cross-sectional view taken along line BB in FIG. 1B.
[0016]
First, the pixel portion will be described. In FIG. 1A, reference numeral 1a denotes a first polysilicon layer constituting an active layer (source / drain / channel region) of the TFT, and is formed on the surface of the polysilicon layer 1a. As shown in FIG. 2A, a gate insulating film 12 is formed by thermal oxidation. 2a is a scanning line to be a gate electrode of the TFT, 3a is a data line for supplying a voltage to be applied to the pixel electrode to the source region (or drain region) of the TFT disposed so as to cross the scanning line 2a, The scanning line 2a is formed by a second polysilicon layer, and the data line 3a is formed by a conductive layer such as an aluminum layer.
[0017]
Reference numeral 4 is a contact hole for connecting the pixel electrode 6a made of an ITO film and the drain region (or source region) of the TFT of the polysilicon layer 1, and 5 is the source of the TFT of the data line 3a and the polysilicon layer 1a. This is a contact hole for connecting the region.
[0018]
In FIG. 2A, which shows a cross section taken along line AA in FIG. 1A, 10 is a substrate such as a glass substrate or a quartz substrate, and 12 is a surface of a polysilicon layer 1a that becomes an active layer of a TFT. A gate insulating film such as a formed silicon oxide film is formed by thermal oxidation or the like. Reference numeral 13 denotes a first interlayer insulating film made of an NSG film (silicate glass film not containing boron or phosphorus), and 15 denotes a second interlayer insulating film made of a BPSG film (silicate glass film containing boron and phosphorus). . As described later, these are formed by high-temperature CVD and low-temperature CVD, respectively.
[0019]
Next, the pad electrode portion will be described. As shown in FIG. 2A, the pad electrode of this embodiment has a two-layer structure in which a second pad electrode 26 made of an ITO film is formed on a first pad electrode 22 made of a polysilicon layer. . The first pad electrode 22 is composed of the same polysilicon layer as the polysilicon layer constituting the gate electrode 2 of the TFT. On the other hand, the second pad electrode 26 is composed of the same ITO film as the ITO film constituting the pixel electrode 6a. The first pad electrode 22 and the second pad electrode 26 are connected via a contact hole 24 formed in the second interlayer insulating film 15. One end of a wiring layer 23 made of an aluminum layer is connected to the first pad electrode 22 through a contact hole 25 formed in the first interlayer insulating film 13. The wiring layer 23 is composed of the same aluminum layer as that of the data line 3.
[0020]
In this embodiment, since the second pad electrode 26 is made of an ITO film having a film strength higher than that of aluminum, even when the probe is contacted during panel inspection using the probe, a protrusion is formed on the surface of the electrode. It becomes difficult to occur. In addition, as described below, the manufacturing process is simplified.
[0021]
In this embodiment, the case where an ITO film is used as the conductive transparent electrode film has been described. However, the present invention is not limited to this. For example, a metal oxide having a high melting point such as SnOx or ZnOx is used. It is also possible to use a transparent electrode material.
[0022]
In this embodiment, the case where the second pad electrode 26 made of an ITO film is formed directly on the first pad electrode 22 made of a polysilicon layer has been described. However, molybdenum (Mo), tantalum (Ta), titanium An ITO film may be provided through a buffer layer such as (Ti).
[0023]
Next, an example of a manufacturing process of the liquid crystal panel substrate of this embodiment will be described with reference to FIGS. 3 to 5 show the step of forming the TFT portion for driving the pixels in sequence, and FIGS. 6 to 8 show the step of forming the pad electrode portion, respectively, and (1) to (14) in FIGS. The steps and the steps (1) to (14) in FIGS. 6 to 8 correspond to each other. 3 to 5 show cross sections along the line AA in FIG. 1A, and FIGS. 6 to 8 show cross sections along the line BB in FIG. 1B. Hereinafter, the steps of the TFT portion and the pad electrode portion will be described while comparing the same steps of FIGS. 3 to 5 and FIGS.
[0024]
First, in the step (1), the polysilicon layer 1 is formed on the substrate 10 such as a glass substrate (for example, an alkali-free substrate) or a quartz substrate by a low pressure CVD method or the like, such as 500 to 2000 angstrom, preferably about 1000 angstrom. It is deposited on the entire surface of the substrate with an appropriate thickness.
[0025]
In the step (2), the polysilicon layer 1 is patterned by a photolithography process, an etching process, etc., thereby forming an island-shaped active layer 1a in the TFT portion (FIG. 3). At this time, the polysilicon layer 1 is completely removed from the pad electrode portion, and the surface of the substrate 10 is exposed (FIG. 6).
[0026]
In the step (3), a gate insulating film 12 is formed on the active layer 1a by thermally oxidizing the surface of the polysilicon layer (1a) (FIG. 3). By this step, the active layer 1a finally has a thickness of 300 to 1500 angstrom, preferably 350 to 450 angstrom, and the gate insulating film 12 has a thickness of about 600 to 1500 angstrom.
[0027]
Next, an impurity (for example, phosphorus) is appropriately applied to the extending portion 1b (see FIG. 1) extending upward along the data line 3 of the polysilicon layer constituting the active layer 1a to form a storage capacitor. Large dose (eg 3 × 10 ¹² atms / cm ² ) To lower the resistance of the polysilicon layer (1b) for that portion. The lower limit of the dose is determined from the viewpoint of securing the conductivity necessary for forming the storage capacity of the polysilicon layer, and the upper limit is determined from the viewpoint of suppressing the deterioration of the gate oxide film. At this time, since there is no polysilicon layer in the pad portion, nothing is done.
[0028]
In the step (4), a low-resistance polysilicon layer 2 to be a gate electrode and a scanning line is formed on the gate insulating film 12 in the TFT portion and directly on the insulating substrate in the pad electrode portion by a low pressure CVD method or the like. accumulate.
[0029]
In the step (5), the polysilicon layer 2 is patterned by photoetching, the gate electrode (including the scanning line) 2a is formed in the TFT portion, and the first layer electrode (first pad electrode) 22 is formed in the pad electrode portion. Form. As a material for the scanning line 2a and the first pad electrode 22, in addition to polysilicon, a refractory metal such as Mo, Ta, Ti, W, or a metal silicide thereof can be used.
[0030]
In the step (6), high concentration semiconductor regions serving as a source region and a drain region self-aligned with the active layer 1a are formed in the TFT portion by ion implantation of impurities (for example, phosphorus) using the gate electrode 2a as a mask. At this time, in the pad electrode portion, the first pad electrode 22 is entirely ion-implanted to reduce the resistance.
[0031]
The source / drain region contains 1 × 10 impurities (phosphorus). ¹³ / Cm ² ~ 3x10 ¹³ / Cm ² After light doping at a dose of a low concentration region is formed, a mask layer wider than the width of the gate electrode is formed on the scanning line 2a, and further an impurity (phosphorus) is added by 1 × 10. ¹⁵ / Cm ² ~ 3x10 ¹⁵ / Cm ² The region masked by implanting at a dose may have a lightly doped drain (LDD) structure. Alternatively, an offset structure is formed by forming a pattern using a mask wider than the width of the gate electrode 2 without lightly doping, and subsequently implanting ions to form a source / drain and then over-etching the gate electrode. You may make it become.
[0032]
In the step (7) (see FIGS. 4 and 7), a first interlayer insulation made of an NSG film (a silicate glass film not containing boron and phosphorus) or the like is formed so as to cover the gate electrode 2a and the first pad electrode 22. The film 13 is deposited to a thickness of 5000 to 15000 angstroms at a temperature of, for example, 800 degrees by, for example, a CVD method.
[0033]
In the step (8) (see FIGS. 4 and 7), the first interlayer insulating film 13 is subjected to dry etching or the like, so that the contact hole 5 is formed at a position corresponding to the source region in the TFT portion and the first in the pad electrode portion. Contact holes 25 are opened at positions corresponding to the edge of the 1-pad electrode 22 on the center side of the substrate.
[0034]
Here, the contact hole 5 is formed so as to penetrate the stacked film of the gate insulating film 12 and the first interlayer insulating film 13, and the contact hole 25 is formed so as to penetrate only the first interlayer insulating film 13. The
[0035]
Further, when the contact hole 5 is formed, the polysilicon layer 1 functions as an etching stopper, and when the contact hole 25 is formed, the first pad electrode 22 functions as an etching stopper.
[0036]
In the step (9), a low-resistance conductive layer 3 such as aluminum to be the data line 3a that also serves as the source electrode is deposited by sputtering. The low-resistance conductive layer 3 is connected to the source region of the active layer 1a through the contact hole 5 in the TFT portion, and to the first pad electrode 22 through the contact hole 25 in the pad electrode portion.
[0037]
In the step (10), the low-resistance conductive layer 3 is patterned by photoetching to connect the data line 3a which also serves as the source electrode in the TFT portion, and the first pad electrode 22 and the data line in the pad electrode portion. The wiring 23 is formed.
[0038]
In the step (11) (see FIGS. 5 and 8), a second interlayer insulating film 15 such as a BPSG film (a silicate glass film containing boron and phosphorus) is formed so as to cover the data line 3a and the wiring 23. For example, it is formed to a thickness of 5000 to 15000 angstroms at a low temperature of, for example, 500 degrees by CVD.
[0039]
In the step (12), in the TFT portion, the second interlayer insulating film 15 and the overlying film composed of the first interlayer insulating film 13 and the gate insulating film 12 thereunder corresponded to the drain region by dry etching or the like. A contact hole 4 is formed at the position. In the pad electrode portion, a contact hole is formed at a position corresponding to the center of the first pad electrode 22 by dry etching or the like with respect to the second interlayer insulating film 15 and the overlying film formed of the first interlayer insulating film 13 thereunder. 24 is opened. At this time, if the resistance at the distance L from the contact hole end 24 to the wiring 23 is 10Ω or less, there is no practical problem.
[0040]
In the step (13), the ITO film 6 to be the pixel electrode 6a is formed in the pad electrode portion by sputtering, for example, to a thickness of 1500 angstroms. At this time, in the TFT portion, the ITO film 14 is connected to the drain region of the active layer 1 a through the contact hole 4, and in the pad electrode portion, the ITO film 6 is connected to the first pad electrode 22 through the contact hole 24.
[0041]
In the step (14), the ITO film 6 is patterned by photoetching to form the pixel electrode 6a in the TFT portion and the second pad electrode 26 in the pad electrode portion.
From the above description, it can be seen that in the process, the structure of the pad electrode portion is realized simultaneously with the manufacturing process of the pixel TFT portion.
[0042]
In this embodiment, the case of using ITO has been described. However, the present invention is not limited to this. For example, a transparent electrode material made of a metal oxide having a high melting point such as SnOx or ZnOx should be used. In this case, the step coverage inside the contact hole is practical.
[0043]
Further, since the ITO film 6 is formed at the final stage of the entire manufacturing process, the substrate is less likely to be contaminated with tin (Sn) or indium (In), which are ITO compositions. Further, the pixel electrodes 6a may be short-circuited to cause a point defect due to a resist residue or the like during the ITO photolithography process. In such a case, if the pixel electrode is short-circuited as a result of the inspection after the above step, the step of cutting the short-circuited portion between the pixel electrodes again by performing a photolithography process using the ITO pattern etching mask Can be added.
[0044]
Although not shown, an alignment film made of polyimide or the like is formed on the pixel electrode 6a and the second interlayer insulating film 15 to a thickness of about 200 to 1000 angstroms and then rubbed (alignment treatment). Thus, a liquid crystal panel substrate is obtained.
[0045]
Next, with reference to FIGS. 9 to 11, the process for the liquid crystal panel substrate of this embodiment having a two-layer pad electrode of a polysilicon layer and an ITO film has a pad electrode made of an aluminum layer of the conventional example. The reason why the number of steps is reduced as compared with the reference process of the liquid crystal panel substrate will be described.
[0046]
FIG. 16A shows a plan view of one pixel pattern, and FIG. 16B shows a plan view of a layout of terminal portions. 17A shows a cross-sectional view taken along the line AA in FIG. 16A, and FIG. 17B shows a cross-sectional view taken along the line BB in FIG. 16B.
[0047]
9 to 11 show a conventional pad portion forming process, and the steps (1 ′) to (14 ′) in FIGS. 9 to 11 are the same as the steps (1) to (14) in FIGS. This corresponds to the steps and the steps (1) to (14) in FIGS.
[0048]
As is apparent from the steps (1 ′) to (8 ′) shown in FIGS. 9 and 10, a conventional process for manufacturing a substrate for a liquid crystal panel having pad electrodes formed of aluminum or an aluminum alloy. In FIG. 2, the polysilicon layer 1 serving as the active layer 1a of the TFT and the polysilicon layer 2 serving as the scanning line 2a are completely removed at the pad electrode portion, and only the first interlayer insulating film 13 remains on the substrate. When the data line 3a made of an aluminum layer is formed in the TFT portion in the steps (9 ′) and (10 ′), the aluminum layer 3 formed by the sputtering method is patterned in the pad electrode portion by etching. Electrode 3b is formed.
[0049]
Thereafter, in the step (11 ′), the second interlayer insulating film 15 is simultaneously formed in the TFT portion and the pad electrode portion, but the contact hole 4 for connecting to the drain region of the pixel electrode is formed in the TFT portion ( 12 ′), the pad electrode portion is covered with a resist or the like, and no contact hole is formed. Even if the ITO film 6 is formed in the step (13 ′), the pad electrode portion is formed for the next pixel electrode formation. The ITO film 6 in the pad electrode portion is removed during the etching step (14 ′). Thereafter, an etching step (15 ′) for forming the opening 7 in the pad electrode portion is performed.
[0050]
FIG. 12 shows a comparative process diagram of the manufacturing process in which FIGS. 6 to 11 are shown in one drawing. In FIG. 12, the left side shows the reference process of the conventional example, and the right side shows the process of this embodiment. As apparent from FIG. 12, in order to manufacture a conventional liquid crystal panel substrate having a pad electrode portion formed of aluminum or an aluminum alloy, an interlayer insulating film above the pad electrode is formed after the structure of the TFT portion is completed. It can be seen that an extra step (15) is required only for the step of forming the apertures 7 at 13 and 15.
[0051]
On the other hand, according to the liquid crystal panel substrate having the pad electrode portion having the two-layer structure of the polysilicon layer and the ITO film as in the present embodiment, the second interlayer insulating film 15 and the underlying layer are formed as described above. Since the opening portion can be formed at once by passing through the laminated film made of the first interlayer insulating film 13, the formation process of the opening portion is completed once, and the entire manufacturing process is referred to the conventional example. There is an advantage that the process can be simplified.
[0052]
FIG. 13 shows a system configuration example of the substrate on the TFT side of the liquid crystal panel of this embodiment. In the figure, reference numerals 90 denote pixels arranged corresponding to the intersections of the scanning lines 2 and the data lines 3 arranged so as to cross each other, and each pixel 90 includes a pixel electrode 6a made of ITO or the like and this pixel electrode. 6a includes a TFT 91 for applying a voltage corresponding to an image signal on the data line 3. The TFTs 91 in the same row have their gate electrodes connected to the same scanning line 2 and their drains connected to the corresponding pixel electrodes 14. The source electrodes of the TFTs 91 in the same column are connected to the same data line 3. In this embodiment, the transistors constituting the peripheral circuits (X and Y shift registers and sampling means) 50 and 60 are constituted by so-called polysilicon TFTs having a polysilicon layer as an operation layer in the same manner as TFTs for driving pixels. The transistors forming the peripheral circuits 50 and 60 are simultaneously formed by the same process together with the pixel driving TFT.
[0053]
In this embodiment, a shift register (hereinafter referred to as an X shift register) 51 for sequentially selecting the data lines 3 is arranged on one side (upper side in the figure) of the display area (pixel matrix) 20, and the other one of the pixel matrix. On the side, a shift register (hereinafter referred to as a Y shift register) 61 for sequentially selecting and driving the scanning lines 2 is provided. A sampling switch 52 composed of a TFT is provided at the other end of each data line 3 where a buffer 63 is provided if necessary at the next stage of the Y shift register 61, and these sampling switches 52 are provided. Is connected between video signal lines 54, 55 and 56 for transmitting image signals VID1 to VID3 input to external terminals 74, 75 and 76, and is sequentially turned on / off by a sampling signal output from X shift register 51. It is configured to be. The X shift register 51 selects a sampling signal X1 that sequentially selects all the data lines 3 once in a horizontal scanning period based on clock signals CLX1 and CLK2 input from the outside via terminals 72 and 73. , X2, X3,... Xn are formed and supplied to the control terminal of the sampling switch 52. On the other hand, the Y shift register 61 is operated in synchronization with clock signals CLY1 and CLY2 inputted from the outside via terminals 77 and 78, and sequentially drives each scanning line 2.
[0054]
14A and 14B show a cross-sectional configuration and a planar layout configuration of a liquid crystal panel 30 to which the liquid crystal panel substrate is applied. As shown in FIG. 14A, a counter electrode 33 made of a transparent conductive film (ITO) and a black matrix (a color filter layer may be provided if necessary) 13 on the surface side of the liquid crystal panel substrate 10. An incident-side counter substrate 31 having a gap is arranged at an appropriate interval, and a TN (Twisted Nematic) type liquid crystal or SH (Super Homeotropic) type liquid crystal 37 is filled in a gap sealed with a sealing material 36 around the periphery. Thus, the liquid crystal panel 30 is configured. Further, the upper part of the peripheral circuits 50 and 60 is configured to be shielded from light by, for example, black matrix provided on the counter substrate 31. 38 is a liquid crystal injection port provided on the counter substrate 31 side, and 39 is a light shielding layer for parting made of a chromium layer or the like provided on the counter substrate 31.
[0055]
As shown in FIG. 14B, the counter substrate 31 is slightly smaller than the TFT side substrate 10, and a pad electrode as an external input terminal is formed on the surface of the TFT side substrate 10 exposed outside the counter substrate 31. 70 is formed and used to input a clock signal, a start signal, a video signal, and the like to the peripheral circuits 50 and 60 as described above.
[0056]
Next, the connection between the liquid crystal panel of this embodiment and an external circuit will be described with reference to FIG. FIG. 18 shows an anisotropic conductive film (hereinafter referred to as ACF) in which the second pad electrode 26 of the pad electrode portion 70 which is an external input terminal of this embodiment and the conductive particles 100 are dispersed in the adhesive 101. Sectional drawing connected with the terminal electrode 103 of FPC (Film Printed Circuit) 102 which has arranged the terminal on the polyimide tape is shown. An ACF is sandwiched between the second pad electrode 26 on the TFT side substrate and the terminal electrode 103 of the FPC, electrically connected via the conductive particles 100 by heating and pressing, and the two electrodes are fixedly held by the adhesive 101. To do. Since a large number of terminals can be connected together at a fine pitch, this is an efficient method. As the conductive particles 100, metal particles such as solder nickel, metal plated plastic balls, or the like is used.
[0057]
Further, as shown in FIG. 14B, in addition to the external input / output pad electrode portion 70 as described above, signals are input / output at the peripheral portion of the TFT side substrate 10 during the inspection by the probe. A pad electrode 170 is provided as an inspection terminal used for this. On the other hand, the counter substrate 31 is also provided with pad electrodes 270 as inspection terminals, and these pad electrodes are used for input / output of signals for inspecting a short circuit of a data line, a defect of a pixel electrode, or the like. .
[0058]
Reference numeral 80 denotes a connection terminal between the upper and lower substrates for applying a common electrode potential from the TFT substrate 10 side to the counter electrode 33 provided on the counter substrate side. This connection terminal 80 is also the above-described embodiment (FIG. 2B). )), And is configured to be electrically connected to the counter substrate by interposing a conductive adhesive having a predetermined diameter on the pad electrode having such a structure.
[0059]
FIG. 15 shows a configuration example of a video projector as an example of a projection display device in which the liquid crystal panel of the present embodiment is applied as a light valve.
[0060]
In FIG. 15, 370 is a light source such as a halogen lamp or a metal halide lamp, 371 is a parabolic mirror, 372 is a heat ray filter, 373, 375 and 376 are dichroic mirrors for blue reflection, green reflection and red reflection, and 374 and 377 are respectively. Reflection mirrors 378, 379, and 380 are light valves formed of the liquid crystal panel of this embodiment, and 383 is a dichroic prism.
[0061]
In the video projector of this embodiment, the white light emitted from the light source 370 is collected by the parabolic mirror 371, passes through the heat ray cut filter 372, and heat rays in the infrared region are blocked, so that only visible light is dichroic mirror system. Is incident on. First, blue light (wavelength of approximately 50 nm or less) is reflected by the blue reflecting dichroic mirror 373, and other light (yellow light) is transmitted. The reflected blue light changes its direction by the reflecting mirror 374 and enters the blue modulation light valve 378.
[0062]
On the other hand, the light transmitted through the blue reflecting dichroic mirror 373 is incident on the green reflecting dichroic mirror 375, the green light (wavelength of approximately 500 to 600 nm) is reflected, and the other light is red light (wavelength of approximately 600 nm or more). Is transparent. The green light reflected by the dichroic mirror 375 enters the green modulation light valve 379. The red light transmitted through the dichroic mirror 375 is changed in direction by the reflection mirrors 376 and 377 and is incident on the red modulation light valve 380.
[0063]
The light valves 378, 379, and 380 are respectively driven by blue, green, and red primary color signals supplied from a video signal processing circuit (not shown), and light incident on each light valve is modulated by the respective light valve. It is synthesized by the dichroic prism 383. The dichroic prism 383 is formed so that the red reflecting surface 381 and the blue reflecting surface 382 are orthogonal to each other. The color image synthesized by the dichroic prism 383 is enlarged and projected on the screen by the projection lens 384 and displayed.
[0064]
Since the liquid crystal panel substrate of the above embodiment has little leakage at the TFT, a display image with high contrast can be obtained in the video projector using the liquid crystal panel using this as a light valve.
[0065]
【The invention's effect】
As described above, conventionally, when the pad electrode portion as a terminal is made of aluminum, it may be corroded by an etching solution for patterning ITO or sputtering at the time of ITO formation, so until the patterning of ITO is completed. The pad was covered with an interlayer insulating film, and etching to open the insulating film on the pad had to be performed after the ITO pixel electrode was formed. Therefore, there has been a problem that the number of processes increases.
[0066]
In contrast, in the method for manufacturing a substrate for a liquid crystal panel according to the present invention, the first conductive layer (first pad electrode) constituting the pad electrode portion as the terminal is the same as the polysilicon layer constituting the TFT. In addition to forming in the process, the second conductive layer (second pad electrode) constituting the pad electrode portion is formed in the same process as the ITO film constituting the pixel electrode. As described above, according to the method of the present invention, the opening in the pad electrode portion is formed simultaneously with the formation of the contact hole for connecting the pixel electrode and the drain region of the TFT, and the pad is formed simultaneously with the pixel electrode. Since the electrode can be formed, it is possible to omit the step of forming a hole in the pad electrode portion, and the manufacturing process can be simplified.
[0067]
In the liquid crystal panel substrate according to the present invention, the pad electrode as a terminal is made of a conductive transparent electrode film such as an ITO film constituting the pixel electrode, so that the pad electrode is stronger than aluminum. Since it is composed of a high ITO film, it is difficult for protrusions to be generated on the surface of the pad electrode by probe inspection, thereby preventing a vertical conduction failure caused by contact with the counter electrode provided on the counter substrate and short-circuiting between the pixel electrodes 6a. Since the pad electrode is not corroded by the etching solution when the portion is cut again by the photolithography process using the mask for the ITO pattern, there is an effect that the regeneration process can be performed.
[Brief description of the drawings]
1A is a plan layout view of one pixel and FIG. 1B is a plan view of a terminal portion in an embodiment of a liquid crystal panel substrate to which the present invention is applied;
FIG. 2 is a cross-sectional view of an embodiment of a liquid crystal panel substrate to which the present invention is applied.
FIG. 3 is a cross-sectional view showing the manufacturing process (first half) of the TFT portion of the liquid crystal panel substrate of the embodiment in order of steps.
FIG. 4 is a cross-sectional view illustrating a manufacturing process (middle panel) of a TFT portion of a liquid crystal panel substrate according to an example in order of steps.
FIG. 5 is a cross-sectional view showing the manufacturing process (second half) of the TFT portion of the liquid crystal panel substrate of the embodiment in the order of steps.
6 is a cross-sectional view showing the manufacturing process (first half) of the pad portion of the liquid crystal panel substrate of the embodiment in the order of steps. FIG.
7 is a cross-sectional view showing a manufacturing process (middle panel) of a pad portion of a liquid crystal panel substrate of an embodiment in the order of steps. FIG.
FIG. 8 is a cross-sectional view showing the manufacturing process (second half) of the pad portion of the liquid crystal panel substrate of the embodiment in order of steps.
FIG. 9 is a sectional view showing a manufacturing process (first half) of a pad portion of a conventional liquid crystal panel substrate in the order of steps.
FIG. 10 is a cross-sectional view showing a manufacturing process (middle stage) of a pad portion of a conventional liquid crystal panel substrate in the order of steps.
FIG. 11 is a cross-sectional view showing a manufacturing process (second half) of a pad portion of a conventional liquid crystal panel substrate in the order of steps.
12 is a comparative process diagram of the manufacturing process showing FIGS. 3 to 11 in one drawing. FIG.
FIG. 13 is a block diagram showing a system configuration example of a liquid crystal panel substrate that is suitable for application of the present embodiment.
14A and 14B are a cross-sectional view and a plan view illustrating a configuration example of a liquid crystal panel using the liquid crystal panel substrate according to the present embodiment.
FIG. 15 is a schematic configuration diagram of a video projector as an example of a projection display device in which an LCD using the liquid crystal panel substrate of the embodiment is applied as a light valve.
16A is a plan view of one pixel, and FIG. 16B is a plan view of a terminal portion in a conventional liquid crystal panel substrate.
17A is a cross-sectional view taken along line AA in FIG. 16A, and FIG. 17B is a cross-sectional view taken along line BB in FIG. 16B in a conventional liquid crystal panel substrate.
FIG. 18 is a cross-sectional view showing an example of a liquid crystal panel using the liquid crystal panel substrate according to this example.
[Explanation of symbols]
1 Polysilicon layer
1a Semiconductor layer (active layer)
2a Scan line (gate electrode)
3 Low resistance conductive layer (aluminum layer)
3a Data line
4 Contact hole between pixel electrode and TFT drain region
5 Contact hole between data line and TFT source region
10 Glass substrate or quartz substrate
12 Gate insulation film
13 First interlayer insulating film
6 ITO film
6a Pixel electrode
15 Second interlayer insulating film
20 display area
30 LCD panel
31 Counter substrate
33 Counter electrode
36 Sealing material
37 LCD
50,60 peripheral circuit
51 X shift register
52 Sampling switch
54-56 Video signal line
61 Y shift register
72 to 78 External input terminals
90 pixels
91 Pixel drive TFT
370 lamp
373, 375, 376 Dichroic mirror
374,377 Reflective mirror
378, 379, 380 Light valve
383 Dichroic Prism
384 projection lens

Claims (7)

A plurality of scanning lines and a plurality of data lines arranged in a matrix on the substrate; a plurality of thin film transistors provided corresponding to the plurality of scanning lines and the plurality of data lines; and corresponding to the plurality of thin film transistors. In a liquid crystal panel substrate having a plurality of provided pixel electrodes, a terminal for connection with an inspection terminal or an external circuit, and a wiring connected to the terminal,
The terminal includes a first pad electrode part formed of the same polysilicon layer as the gate electrode of the thin film transistor, and a second ITO film formed of the same ITO film as the pixel electrode on the surface of the first pad electrode part. It consists of a pad electrode part,
The wiring is formed of the same aluminum layer as the data line provided via an insulating film on the thin film transistor or an alloy layer thereof, and through a contact hole formed in the insulating film in the first pad electrode portion. A liquid crystal panel substrate characterized by being connected. A plurality of scanning lines and a plurality of data lines arranged in a matrix on the substrate; a plurality of thin film transistors provided corresponding to the plurality of scanning lines and the plurality of data lines; and corresponding to the plurality of thin film transistors. In a liquid crystal panel substrate having a plurality of provided pixel electrodes, a terminal for connection with an inspection terminal or an external circuit, and a wiring connected to the terminal,
The terminal includes a first pad electrode part formed of the same metal silicide layer as the gate electrode of the thin film transistor, and a second ITO film formed of the same ITO film as the pixel electrode on the surface of the first pad electrode part. It consists of a pad electrode part,
The wiring is formed of the same aluminum layer as the data line provided via an insulating film on the thin film transistor or an alloy layer thereof, and through a contact hole formed in the insulating film in the first pad electrode portion. A liquid crystal panel substrate characterized by being connected.   3. The liquid crystal panel substrate according to claim 1 and the counter substrate having a counter electrode are arranged at an appropriate interval, and within the gap between the liquid crystal panel substrate and the counter substrate. A liquid crystal panel in which liquid crystal is sealed.   4. A liquid crystal panel having a configuration according to claim 3 that modulates and transmits or reflects light from the light source, and projection optical means that condenses and expands the light modulated by these liquid crystal panels. A projection display device characterized by that. A plurality of scanning lines and a plurality of data lines arranged in a matrix on the substrate; a plurality of thin film transistors provided corresponding to the plurality of scanning lines and the plurality of data lines; and corresponding to the plurality of thin film transistors. In a method for manufacturing a substrate for a liquid crystal panel having a plurality of provided pixel electrodes and a terminal for inspection or a terminal for connection to an external circuit,
Forming an active layer of the thin film transistor on the insulating substrate;
Forming a gate electrode of the thin film transistor and a first pad electrode constituting the terminal with the same polysilicon layer;
Forming a first interlayer insulating film above the active layer and the gate electrode and scanning line;
A contact hole is opened in the first interlayer insulating film to form a data line connected to the thin film transistor, and at the same time, a contact hole is opened in the first interlayer insulating film and made of the same material as the data line. Forming the wiring connected to one pad electrode;
Forming a second interlayer insulating film on the data line and the wiring;
A contact hole is opened in the second interlayer insulating film and the first interlayer insulating film to form the pixel electrode made of an ITO film connected to the thin film transistor. At the same time, the second interlayer insulating film and the first interlayer are formed. And a step of forming a second pad on the surface of the first pad constituting the terminal with the same material as the pixel electrode by opening a contact hole in the insulating film. Production method. A plurality of scanning lines and a plurality of data lines arranged in a matrix on the substrate; a plurality of thin film transistors provided corresponding to the plurality of scanning lines and the plurality of data lines; and corresponding to the plurality of thin film transistors. In a method for manufacturing a substrate for a liquid crystal panel having a plurality of provided pixel electrodes and a terminal for inspection or a terminal for connection to an external circuit,
Forming an active layer of the thin film transistor on the insulating substrate;
Forming a gate electrode of the thin film transistor and a first pad electrode constituting the terminal with the same metal silicide layer;
Forming a first interlayer insulating film above the active layer and the gate electrode and scanning line;
A contact hole is opened in the first interlayer insulating film to form a data line connected to the thin film transistor, and at the same time, a contact hole is opened in the first interlayer insulating film and made of the same material as the data line. Forming the wiring connected to one pad electrode;
Forming a second interlayer insulating film on the data line and the wiring;
A contact hole is opened in the second interlayer insulating film and the first interlayer insulating film to form the pixel electrode made of an ITO film connected to the thin film transistor. At the same time, the second interlayer insulating film and the first interlayer are formed. And a step of forming a second pad on the surface of the first pad constituting the terminal with the same material as the pixel electrode by opening a contact hole in the insulating film. Production method. The method for manufacturing a substrate for a liquid crystal panel according to claim 5 or 6, wherein the second pad electrode is connected to an electrode disposed on a polyimide tape via an anisotropic conductive film.

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