JPH08130313A - Inverted staggered thin-film transistor and its manufacture - Google Patents

Abstract

PURPOSE: To provide an inverted staggered thin-film transistor which reduces a contact resistance to improve and stabilize its characteristics, and suppresses a drop in reliability due to a dielectric breakdown and to provide the manufacturing method of a thin-film transistor whose productivity is high. CONSTITUTION: At least a gate electrode 103, a gate interconnection 104, a gate insulating film 105, a semiconductor active layer 106, a source electrode 109, a drain electrode 110 and a passivation film in a channel part 111 for the semiconductor active layer are formed sequentially on a substrate 101. A source interconnection and a drain interconnection are connected respectively to the source electrode and the drain electrode. The film thickness of an insulating film formed between the interconnections at the crossing part of the gate interconnection with the source interconnection is nearly equal to the sum of the film thickness of the gate insulating film 105 and the film thickness of the passivation film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverted stagger type thin film transistor and a method of manufacturing the same, and more particularly to a thin film transistor having high driving capability and high reliability.

[0002]

2. Description of the Related Art A conventional device having a large number of thin film transistors
A thin film transistor substrate and a method of manufacturing the same will be described with reference to FIG.
explain. On a substrate 301 such as glass, 100 nm C
an external connection terminal 302 composed of r, a gate electrode 303,
The gate wiring 304 is formed. Next, a-SiNx30
0 nm gate insulating film 305, i-type a-Si 100 nm
Semiconductor active layers 306, n ⁺Type a-Si 20nm
The semiconductor contact layer 307 is formed and the semiconductor active layer 30 is formed.
6 and ohmic contact layer 307 are the same resist
Etching with a mask between the transistor elements
Separate (FIG. 1 (a)).

Next, after a-SiNx 305 is etched to form a contact hole 313, Cr 308,
Al (309, 310) is 50 nm and 300 n, respectively.
m film formation and etching to form source electrode and source wiring,
A drain electrode, a drain wiring, and a channel 311 are formed (FIG. 1B). Finally, a-SiNx is formed to a thickness of 400 nm as the passivation film 312, and necessary windows are opened to complete the thin film transistor (FIG. 1).
(C)).

However, when the thin film transistor is manufactured by such a conventional method for manufacturing a thin film transistor, the on-current of the thin film transistor is lower than the design value, and it varies between elements.
There was a problem that the design margin could not be taken. Therefore, in order to solve these problems, the present inventors conducted a fundamental study of the manufacturing method and conditions, and as a result, the main cause of this problem is the ohmic contact layer at the interface between the ohmic contact layer and the electrode layer. It turned out to be oxidation. That is, it has been found that the oxidation of the ohmic contact layer increases the value of the contact resistance and the variation thereof, and as a result, the on-current of the transistor decreases and varies.

In addition, the gate wiring 304 and the source wiring 30
Since the insulating film 314 at the intersection with 9 is composed of only a thin gate insulating film, a sufficient withstand voltage cannot be obtained, and dielectric breakdown occurs due to static electricity during the manufacturing process or repeated operation during actual use. Happened a lot. However, if the gate insulating film is thickened to increase the reliability of the insulation, the on-current will be insufficient because the capacity will decrease, and the thin film transistor will have to be designed large accordingly, for example, when the thin film transistor is applied to a liquid crystal display element As a result, there is a problem in that the aperture ratio is reduced, and if an attempt is made to increase the film thickness only at the intersecting portions, a film forming and patterning process is required, and the number of steps is increased and productivity is lowered.

[0006]

[Problems to be Solved by the Invention] In the above situation,
It is an object of the present invention to provide an inverted stagger type thin film transistor that reduces contact resistance to improve and stabilize characteristics and suppresses deterioration in reliability due to dielectric breakdown, and a method for manufacturing a highly productive thin film transistor.

[0007]

The first gist of the present invention is as follows.
At least a gate electrode and a gate wiring, a gate insulating film, a semiconductor active layer, a source electrode and a drain electrode, and a passivation film of a channel portion of the semiconductor active layer are sequentially formed on a substrate. A source wiring and a drain wiring are respectively connected to the electrodes, and a film thickness of an insulating film provided between the wirings at an intersection of the gate wiring and the source wiring is equal to a film thickness of the gate insulating film and the passivation. It exists in an inverted stagger type thin film transistor characterized by being approximately equal to the sum of the film thickness.

A second aspect of the present invention is to provide at least a gate electrode and a gate wiring, a gate insulating film, a semiconductor active layer, an ohmic contact layer, a source electrode and a drain electrode, and a channel portion of the semiconductor active layer on a substrate. A passivation film is sequentially formed, and at the time of forming the gate insulating film and when forming the passivation film, at least on a gate wiring at an intersection of the gate wiring and a source wiring connected to the source electrode. Film formation at the same time,
An insulating film between the source wiring and the gate wiring at the intersection is composed of the gate insulating film and the passivation film,
Further, there is a method of manufacturing an inverted stagger type thin film transistor characterized in that a source wiring and a drain wiring are connected to the source electrode and the drain electrode, respectively.

[0009]

In the method of manufacturing an inverted stagger type thin film transistor according to the present invention, since the step of forming a passivation film on the channel portion of the semiconductor active layer is performed before the source / drain wiring is formed, the gate wiring is formed at the time of forming the passivation film on the channel portion. It is possible to form a passivation film also at the intersection of the source wiring and the source wiring. Therefore, it is possible to increase the film thickness of the insulating film at the intersection to the film thickness obtained by adding the passivation film to the gate insulating film without increasing the number of steps.

As a result, the withstand voltage of the insulating film is sufficiently high, and a highly reliable thin film transistor can be obtained. Also,
The ohmic contact layer and the electrode layer on the ohmic contact layer are continuously formed so that the oxidizable ohmic contact layer does not come into contact with the atmosphere. As a result, the contact resistance between the ohmic contact layer and the electrode layer is remarkably reduced, and the variation is also reduced. For example, it is possible to increase the on-current and make it uniform among the elements.

As described above, it is preferable to form the ohmic contact layer and the electrode layer continuously, but in order to form a clean interface and further improve the characteristics, the gate insulating film, the semiconductor active layer, It is preferable to continuously form four layers of the ohmic contact layer and the electrode layer. In addition, in the etching process of the electrode layer, the ohmic contact layer, and the semiconductor active layer for separating the thin film transistor elements, or the etching process of the electrode layer and the ohmic contact layer for forming the channel, the pattern accuracy is improved and the characteristics are uniform. It is preferable to perform etching with the same mask in order to realize the same. Furthermore, in order to prevent the resist from peeling off and to carry out etching without steps, it is preferable to carry out the etching collectively using the same etching solution. metal,
As a batch etching solution for the ohmic contact layer and the semiconductor active layer, for example, when the metal is W, Mo, Ti or the like and the semiconductor is Si, a HIO ₃ based etching solution is used.

Si ₃ N ₄ is preferable as the gate insulating film of the thin film transistor of the present invention. Since the permittivity is higher than that of SiO ₂ , the thin film transistor can be designed small, and higher integration and higher aperture ratio are possible. Also, as the passivation film, it is preferable to use Si ₃ N _4, which has a lower transmittance of Na or the like than SiO ₂ . These insulating film and passivation film are plasma CVD (PECVD)
The film is preferably formed by the method. By the PECVD method, a film having excellent step coverage and pressure resistance can be formed at a relatively low temperature (even if a glass substrate is used). The semiconductor active layer and ohmic contact layer are formed of a-Si and po.
Ly-Si is preferably used, but needless to say, it can be applied to other semiconductors.

Further, as a material of the electrode, a metal which is hard to diffuse into the semiconductor layer and hard to oxidize, or a silicide thereof is preferably used. Specifically, for example, W,
Mo, Ti, Cr and the like and their silicides. As the material of the wiring, Al, Cu or the like having a low specific resistance is used.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The inverted staggered thin film transistor and the method of manufacturing the same according to the present invention will be described more specifically with reference to FIGS. 1 and 2 are conceptual diagrams showing a part of a substrate having a large number of thin film transistors. First, a 100 nm Cr film is formed on a 4-inch square glass substrate 101 by a sputtering method, and is etched to form external connection terminals 102,
The gate electrode 103 and the gate wiring 104 were formed.

Next, a gate insulating film (a-SiNx300
nm) 105, semiconductor active layer (i-type a-Si100n
m) 106 and ohmic contact layer (n ⁺ type aS)
i) 107 is an electrode layer (W50 nm) 1 by PECVD method
No. 08 was continuously formed by a sputtering method without being exposed to the atmosphere (FIG. 1A). In addition, for the film formation of these four layers,
An in-line type film forming apparatus having three PECVD film forming chambers and one sputtering chamber was used.

Next, the electrode layer 108, the ohmic contact layer 107, and the semiconductor active layer 106 are formed by using the same resist mask and the same etching solution (HF 0.5 wt%, HIO).
₃ 1.0 wt%) to collectively separate the transistor elements (FIG. 1B). Subsequently, the electrode layer 108 on the channel and the ohmic contact layer 107 were collectively etched with the same mask using the above etching solution to form the source electrode 109, the drain electrode 110, and the channel portion 111 (FIG. 1C).

Next, a passivation film (a-SiNx
200 nm) 112 was formed on the entire surface (FIG. 2A).
Further, contact hole 1 for connecting source / drain wiring
14 window openings and contact holes 11 for external connection terminals
After opening the window of No. 3 (Fig. 2 (b)), Al (300n
m) was deposited by a sputtering method and patterned to form a source wiring 109 ′ and a drain wiring 110 ′ (FIG. 2 (c)).

In the manufacturing method of this embodiment, the number of etching baths used can be reduced by one compared with the conventional method. The thickness of the insulating film (intersection of the gate wiring and the source wiring) manufactured as described above is 465 nm, which is approximately equal to the sum of the thicknesses of the gate insulating film (300 nm) and the passivation film (200 nm). Met. The reason why the film thickness at the intersection became smaller than 500 nm is considered to be that the gate insulating film was etched by the etching at the time of separating the transistor elements.

The on-resistance of the manufactured transistor is 10 to 10.
20% reduction. This is considered to be due to the reduction in contact resistance between the ohmic contact layer and the metal. Also, the variation was reduced to half that of the conventional one. Furthermore, since the film thickness of the insulating film at the intersection of the source wiring and the gate wiring is 465 nm, the withstand voltage of the insulating film is improved, the insulating film is not destroyed by static electricity during the process, and the operation test is repeated 10 times. No defects occurred even after the above, and the yield and reliability were improved.

[0020]

According to the present invention, it is possible to provide a highly reliable thin film transistor in which the withstand voltage of the insulating portion can be increased. Further, the contact resistance can be reduced to a level that can be ignored, and as a result, the on-current can be stably increased and the speed of the device can be increased, so that it is possible to provide a higher performance thin film transistor.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a method of manufacturing an inverted stagger type thin film transistor of the present invention.

FIG. 2 is a conceptual diagram showing a method of manufacturing an inverted stagger type thin film transistor of the present invention.

FIG. 3 is a conceptual diagram showing a method of manufacturing a conventional inverted stagger type thin film transistor.

[Explanation of symbols]

101, 301 glass substrate, 102, 302 ITO, 103, 303 gate electrode, 104, 304 gate wiring, 105, 305 gate insulating film, 106, 306 semiconductor active layer (i-type a-Si), 107, 307 ohmic contact layer (N ⁺ type a-
Si), 108 electrode layer, 109 source electrode, 109 'source wiring, 110 drain electrode, 110' drain wiring, 111, 311 channel, 112, 312 passivation film, 113, 114, 313 contact hole, 115, 314 wiring intersection 308 electrode layer (barrier metal layer), 309 source electrode / wiring, 310 drain electrode / wiring

Front page continued (72) Inventor Hirofumi Fukui 1-7 Yukiya Otsukacho, Ota-ku, Tokyo Alps Electric Co., Ltd. (72) Inventor Yasuhiko Kasama 1-7 Yukiya Otsuka-cho, Ota-ku, Tokyo Alps Electric Co., Ltd. In-house (72) Inventor Tadahiro Omi 301-1 of 2-1, Yonegabukuro, Aoba-ku, Sendai-shi, Miyagi 301

Claims (8)

[Claims] 1. At least a gate electrode and a gate wiring, a gate insulating film, a semiconductor active layer, a source electrode and a drain electrode, and a passivation film of a channel portion of the semiconductor active layer are sequentially formed on a substrate, A source wiring and a drain wiring are respectively connected to the source electrode and the drain electrode, and a film thickness of an insulating film provided between the wirings at an intersection of the gate wiring and the source wiring is
An inverted stagger type thin film transistor, which is approximately equal to the sum of the thickness of the gate insulating film and the thickness of the passivation film. 2. The inverted stagger type thin film transistor according to claim 1, wherein an insulating film between the gate wiring and the source wiring is composed of the gate insulating film and the passivation film. 3. The insulating film between the gate wiring and the source wiring, the gate insulating film and the passivation film are made of silicon nitride formed by a plasma CVD method. The inverted stagger type thin film transistor according to 1 or 2. 4. The inverted stagger type thin film transistor according to claim 1, further comprising an ohmic contact layer provided between the semiconductor active layer and the source and drain electrodes. 5. At least a gate electrode and a gate wiring, a gate insulating film, a semiconductor active layer, an ohmic contact layer, a source electrode and a drain electrode, and a passivation film of a channel portion of the semiconductor active layer are sequentially formed on a substrate, When forming the gate insulating film and forming the passivation film, at least the gate wiring at the intersection of the gate wiring and the source wiring connected to the source electrode is simultaneously formed, An insulating film between a source wiring and a gate wiring at an intersection is formed of the gate insulating film and the passivation film, and further, a source wiring and a drain wiring are connected to the source electrode and the drain electrode, respectively. Stagger type thin film transistor manufacturing method. 6. The inverted stagger type thin film transistor according to claim 5, wherein after the formation of the ohmic contact layer, the layers of the source electrode and the drain electrode are continuously formed without being exposed to the atmosphere. Manufacturing method. 7. The etching of the source electrode and drain electrode layers, the ohmic contact layer and the semiconductor active layer for separating each thin film transistor is performed using the same resist mask. The method for manufacturing an inverted stagger type thin film transistor according to claim 5. 8. The same resist mask is used for etching the source electrode and drain electrode layers and the ohmic contact layer for forming the channel portion. 13. The method for manufacturing an inverted stagger type thin film transistor according to any one of 1.