JP3757658B2 - Electro-optical device manufacturing method, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an electro-optical device in which a light-transmitting substrate and a single crystal silicon layer are bonded, an electro-optical device, and an electronic apparatus. In particular, the present invention relates to a method for manufacturing an electro-optical device, an electro-optical device, and an electronic apparatus in which a light shielding layer is embedded in a recess of a light-transmitting substrate.
[0002]
[Prior art]
The SOI technology in which a silicon thin film is formed on an insulating substrate and a semiconductor device is formed on the silicon thin film has advantages such as higher element speed, lower power consumption, and higher integration. Suitable for optical devices.
[0003]
When the SOI technology is applied to such an electro-optical device, a single crystal silicon substrate is bonded to a light transmissive substrate, a thin single crystal silicon layer is formed by polishing or the like, and the single crystal silicon layer is used for, for example, liquid crystal driving It is formed in a transistor element such as a MOSFET.
[0004]
By the way, in a projection display device such as a projector using a liquid crystal device, for example, light is normally irradiated from the surface of a light transmissive substrate, and this is incident on a channel region of a MOSFET formed on the substrate to cause a light leakage current. In general, a light shielding layer is provided on the MOSFET to prevent the occurrence of the above. However, even if a light-shielding layer is provided on the top of the MOSFET, if the support substrate is light transmissive, light incident from the front surface may be reflected at the interface on the back side of the substrate and enter the channel portion of the MOSFET as incident light. . This return light is a small percentage of the amount of light emitted from the surface, but in a device using a very powerful light source such as a projector, a light leakage current can be sufficiently generated. That is, the return light from the back surface of the substrate affects the switching characteristics of the element and degrades the characteristics of the device. Here, the surface on which the single crystal silicon layer is formed is the front surface of the substrate, and the opposite side is the back surface.
[0005]
Japanese Patent Laid-Open No. 10-293320 proposes a technique for forming a light shielding layer on a substrate surface corresponding to a transistor element region. In this technique, the light shielding layer is patterned on the surface of the substrate as described above, and the light shielding layer is covered with an insulating layer, flattened by polishing, and a single crystal silicon substrate is bonded to the flat surface.
[0006]
[Problems to be solved by the invention]
However, in such a liquid crystal device, there are a portion where the transistor element regions are dense and a portion where the transistor element regions are not dense on the substrate. Accordingly, the corresponding light shielding layer is similarly distributed on the substrate, and the insulator layer before polishing is distributed. There are portions where the surface irregularities are also dense and portions where the unevenness is not dense. For this reason, in the polishing process for flattening the surface of the insulator layer, the degree of polishing varies between the portions where the irregularities are dense and the portions where the irregularities are not dense, and the insulator layer becomes thick at the portions where the irregularities are dense. However, there is a problem that the insulating layer becomes thin in a portion where the unevenness is not dense, and the surface of the insulating layer after polishing is wavy.
[0007]
And when such a wave | undulation arises on the insulator layer surface, there exist the following problems. First, voids are generated at the interface between the insulator layer and the single crystal silicon layer, and the characteristics of the MOSFET formed in the region where the voids are present are deteriorated or made completely defective. Secondly, the bonding strength between the insulator layer and the single crystal silicon layer is weakened, causing defects such as film peeling in the MOSFET formation process after the formation of the single crystal silicon layer, thereby reducing the product yield.
[0008]
The present invention has been made to solve such a problem, and provides an electro-optical device manufacturing method, an electro-optical device, and an electronic apparatus that can planarize an insulator layer surface to which a single crystal silicon layer is bonded. The purpose is to do.
[0009]
[Means for Solving the Problems]
  In order to solve this problem, a method for manufacturing an electro-optical device according to the present invention includes:A method of manufacturing an electro-optical device in which a plurality of pixel electrodes and a transistor element region corresponding to each pixel electrode are formed in an image display region on a light-transmitting substrate,A step of forming a recess on one surface of the light-transmitting substrate, a step of forming a light-blocking layer on one surface of the light-transmitting substrate on which the recess is formed, and a light-blocking layer formed in the recess while remaining Removing the light-shielding layer until one surface of the light-transmitting substrate is exposed, and planarizing one surface of the light-transmitting substrate; and an insulator layer on one surface of the flattened light-transmitting substrate Forming a single crystal silicon layer on the surface of the insulator layerAnd forming the transistor element region at a position corresponding to the light shielding layer of the bonded single crystal silicon layer;It is characterized by comprising.
[0010]
  According to the manufacturing method of the present invention, a concave portion is formed on one surface of a light-transmitting substrate, a light-shielding layer is formed thereon, and the light-transmitting property is left while the light-shielding layer formed in the concave portion remains from above. Since the light-shielding layer is removed until one surface of the substrate is exposed to flatten the one surface of the light-transmitting substrate, the surface of the light-transmitting substrate is like a stopper when removing the light-shielding layer by polishing or the like, for example. The light shielding layer on the surface of the light-transmitting substrate is completely removed, and only the light shielding layer in the recess remains cleanly. Accordingly, the light-transmitting substrate and the surface of the light-shielding layer can be removed extremely flat without undulation or the like in the process of removing the light-shielding layer. Therefore, the surface of the insulator layer is also flattened, so that no void is generated at the interface between the insulator layer and the single crystal silicon layer, and the bonding strength between the insulator layer and the single crystal silicon layer is strong. Further, variations and defects in transistor element characteristics are not caused.In addition, even if light incident from the surface of the light transmissive substrate is reflected on the back surface of the substrate and incident as return light on the region where the transistor element is formed, a leakage current does not occur due to the presence of the light shielding layer, An electro-optical device in which the device characteristics are not deteriorated can be manufactured.
[0011]
Therefore, in the method of manufacturing the electro-optical device according to the aspect of the invention, it is preferable that the light shielding layer is removed by a chemical mechanical polishing method in the step of flattening one surface of the light transmissive substrate.
[0013]
  The electro-optical device of the present invention includes:An electro-optical device in which a plurality of pixel electrodes and a transistor element region corresponding to each pixel electrode are formed in an image display region on a light transmissive substrate,RecessedSaidA light-transmitting substrate; a light-blocking layer formed so as to fill a concave portion of the light-transmitting substrate; an insulator layer provided on the light-transmitting substrate on which the light-blocking layer is formed; Formed at a position corresponding to the light shielding layer.SaidAnd a single crystal silicon layer in which a transistor element region is formed.
[0014]
According to this configuration of the present invention, since the surface of the insulator layer is flattened, no void is generated at the boundary surface between the insulator layer and the single crystal silicon layer, and the insulator layer and An electro-optical device can be realized that has high bonding strength with the crystalline silicon layer and does not cause variations or defects in the characteristics of the transistor elements.
[0015]
In the electro-optical device according to the aspect of the invention, the light-transmitting substrate is made of quartz, and the light-shielding layer is made of a refractory metal or a silicon compound of a refractory metal. As a result, when removing the light shielding layer by polishing, for example, the surface of the light transmissive substrate made of quartz surely serves as an etching stopper, and the surfaces of the light transmissive substrate and the light shielding layer are extremely flat without undulation. Can be removed.
[0016]
The electro-optical device according to the present invention is characterized in that the light shielding layer is electrically connected to a peripheral circuit provided around the image display region.
  AlsoThe electro-optical device according to the present invention includes a light transmissive substrate disposed between the two light transmissive substrates and another light transmissive substrate disposed so as to face the surface on which the single crystal silicon layer is formed. And a liquid crystal which is sandwiched and driven by the transistor element formed in the transistor element region.
[0017]
An electronic apparatus according to an aspect of the invention projects a light source, the electro-optical device according to the above, in which light emitted from the light source is incident and performs modulation corresponding to image information, and light modulated by the electro-optical device And a projecting means.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0019]
(Basic structure of electro-optical device)
FIG. 1 is a sectional view showing the basic structure of an electro-optical device according to an embodiment of the invention.
[0020]
As shown in FIG. 1, in the electro-optical device 201, a recess 203 is provided on a light transmitting substrate 202, and a light shielding layer 204 is formed so as to fill the recess 203. An insulating layer 205 and a single crystal silicon layer 206 are sequentially formed on the light transmissive substrate 202. Note that a transistor element region (not shown) is formed in a position corresponding to the light shielding layer 204 in the single crystal silicon layer 206.
[0021]
(Manufacturing process)
A manufacturing process of the electro-optical device will be described with reference to FIGS.
[0022]
First, as shown in FIG. 2A, a photoresist pattern 207 is formed on, for example, a transparent light-transmitting substrate 202. Here, for example, quartz having a thickness of 1.1 mm is used as the light-transmitting substrate 202. The photoresist pattern 207 is formed at a position other than the position corresponding to the transistor element region.
[0023]
Next, as shown in FIG. 2B, etching is performed using the photoresist pattern 207 as a mask to form a recess 203 having a depth of about 400 nm, for example, at a position corresponding to the transistor element region on the light-transmitting substrate 202. To do. Thereafter, the photoresist pattern 207 is peeled off.
[0024]
Next, as shown in FIG. 3C, a light shielding layer 204 is formed on the light transmissive substrate 202. The light shielding layer 204 is obtained, for example, by depositing molybdenum to a thickness of about 400 to 1000 nm by sputtering, more preferably to a thickness of 400 nm which is the same as the depth of the recess formed in the light transmitting substrate. The material of the light shielding layer 204 is not limited to this embodiment, and any material can be used as long as it is stable to the maximum thermal process temperature of the device to be manufactured. For example, refractory metals such as tungsten and tantalum, polycrystalline silicon, and silicides such as tungsten silicide and molybdenum silicide are also used as preferred materials, and the formation method is not only sputtering but also CVD or electron beam heating evaporation. Etc. can be used.
[0025]
Next, as shown in FIG. 3D, the surface of the light shielding layer 204 is globally polished until the surface of the light transmissive substrate 202 is exposed while the light shielding layer 204 formed in the recess 203 remains. Turn into. As a planarization method by polishing, for example, a CMP (chemical mechanical polishing) method can be used.
[0026]
Next, as shown in FIG. 3E, an insulator layer 205 made of, for example, a silicon oxide film is deposited. This silicon oxide film is deposited by, for example, about 1000 nm by sputtering or plasma CVD using TEOS (tetraethylorthosilicate). As the material of the insulator layer 205, in addition to the silicon oxide film, for example, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass). High-insulating glass such as silicon nitride film or the like can be used.
[0027]
Next, as shown in FIG. 3F, the light-transmitting substrate 202 and the single crystal silicon substrate 206a are bonded to each other. The single crystal silicon substrate 206a used for bonding has a thickness of 300 μm, and its surface is previously oxidized by about 0.05 to 0.8 μm to form an oxide film layer 206b. This is because the interface between the single crystal silicon layer 206 and the oxide film layer 206b formed after bonding is formed by thermal oxidation to ensure an interface with good electrical characteristics. For the bonding step, for example, a method of directly bonding two substrates by heat treatment at 300 ° C. for 2 hours can be employed. In order to further increase the bonding strength, it is necessary to further increase the heat treatment temperature to about 450 ° C. However, there is a large difference in the thermal expansion coefficient between the quartz substrate and the single crystal silicon substrate. Defects such as cracks occur in the silicon layer, and the substrate quality deteriorates. In order to suppress the occurrence of defects such as cracks, a single crystal silicon substrate that has been subjected to heat treatment for bonding at 300 ° C. once is thinned to about 100 to 150 μm by wet etching or CMP, It is desirable to perform a high temperature heat treatment. For example, it is preferable to use a KOH aqueous solution at 80 ° C. and perform etching so that the thickness of the single crystal silicon substrate is 150 μm, and then heat-treat the bonded substrates again at 450 ° C. to increase the bonding strength.
[0028]
Further, as shown in FIG. 4G, the bonded substrate is polished so that the thickness of the single crystal silicon layer 206 is 3 to 5 μm.
[0029]
The bonded substrate thus thinned is finally etched by a PACE (Plasma Assisted Chemical Etching) method to a thickness of the silicon layer 206 of about 0.05 to 0.8 μm. By this PACE process, the single crystal silicon layer 206 has a uniformity within 10% with respect to a film thickness of 100 nm, for example.
[0030]
As described above, according to the manufacturing process of the present embodiment, the recess 203 is formed in the light transmissive substrate 202, the light shielding layer 204 is formed thereon, and polishing is performed from above. At this time, the surface of the light transmissive substrate 202 functions as a stopper, so that the light shielding layer 204 on the surface of the light transmissive substrate 202 is completely removed, and only the light shielding layer 202 in the recess 203 remains cleanly. Therefore, in the polishing step shown in FIG. 3D, the surfaces of the light transmissive substrate 202 and the light shielding layer 204 can be polished extremely flat without undulation or the like. Therefore, the surface of the insulator layer 205 is also planarized, so that no void is generated at the boundary surface where the insulator layer 205 and the single crystal silicon layer 206 are bonded to each other. The bonding strength is increased, and further, there is no occurrence of variations or defects in the characteristics of the transistor elements.
[0031]
(Configuration of electro-optical device using the process of this embodiment)
FIG. 5 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image forming region of a liquid crystal device as an electro-optical device. FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed, and FIG. 7 is a plan view of FIG. It is sectional drawing. In FIG. 7, the scales of the respective layers and members are different from each other in order to make each layer and each member large enough to be recognized on the drawing.
[0032]
In FIG. 5, a plurality of pixels formed in a matrix that form an image display area of the liquid crystal device according to the present embodiment are formed from a plurality of pixel electrodes 9 a formed in a matrix and a TFT 30 for controlling the pixel electrodes 9 a. Thus, the data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode (described later) formed on a counter substrate (described later). . The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. In the normally white mode, incident light cannot pass through the liquid crystal part according to the applied voltage. In the normally black mode, incident light passes through the liquid crystal part according to the applied voltage. Through the liquid crystal device as a whole, light having a contrast according to the image signal is emitted. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the voltage is applied to the data line. Thereby, the holding characteristics are further improved, and a liquid crystal device with a high contrast ratio can be realized. In this embodiment, in particular, in order to form such a storage capacitor 70, a capacitor line 3b having a low resistance by using the same layer as the scanning line or a conductive light-shielding film is provided as will be described later. .
[0033]
In FIG. 6, on the TFT array substrate of the liquid crystal device, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix, and the vertical and horizontal boundaries of the pixel electrodes 9a are provided. A data line 6a, a scanning line 3a, and a capacitor line 3b are provided along each line. The data line 6a is electrically connected to a source region to be described later in the semiconductor layer 1a of the single crystal silicon layer through the contact hole 5, and the pixel electrode 9a is to be described later in the semiconductor layer 1a through the contact hole 8. Is electrically connected to the drain region. In addition, the scanning line 3a is disposed so as to face the channel region (the hatched region in the lower right in the drawing) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode.
[0034]
The capacitance line 3b is formed from a main line portion (that is, a first region formed along the scanning line 3a in a plan view) extending substantially linearly along the scanning line 3a and a portion intersecting the data line 6a. And a protruding portion (that is, a second region extending along the data line 6 a when viewed in a plan view) that protrudes forward (upward in the drawing) along the data line 6 a.
[0035]
A plurality of first light-shielding films 11a corresponding to the light-shielding layer 204 shown in FIG. More specifically, the first light shielding film 11a is provided at a position covering the TFT including the channel region of the semiconductor layer 1a in the pixel portion when viewed from the TFT array substrate side, and further, the main line of the capacitor line 3b. A main line portion that extends in a straight line along the scanning line 3a facing the portion, and a protruding portion that protrudes from the portion intersecting the data line 6a to the adjacent step side (that is, downward in the figure) along the data line 6a Have The tip of the downward projecting portion in each stage (pixel row) of the first light shielding film 11a overlaps the tip of the upward projecting portion of the capacitor line 3b in the next stage under the data line 6a. A contact hole 13 for electrically connecting the first light shielding film 11a and the capacitor line 3b to each other is provided at the overlapped portion. In other words, in the present embodiment, the first light-shielding film 11a is electrically connected to the upstream or downstream capacitor line 3b through the contact hole 13.
[0036]
Next, as shown in the cross-sectional view of FIG. 7, the liquid crystal device includes a TFT array substrate 10 that constitutes an example of a light transmissive substrate, and a transparent counter substrate 20 that is disposed to face the TFT array substrate 10. The TFT array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO film (indium tin oxide film). The alignment film 16 is made of an organic thin film such as a polyimide thin film.
[0037]
On the other hand, the counter substrate 20 is provided with a counter electrode (common electrode) 21 over the entire surface thereof, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 20. ing. The counter electrode 21 is made of a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.
[0038]
As shown in FIG. 7, the TFT array substrate 10 is provided with pixel switching TFTs 30 that perform switching control of the pixel electrodes 9a at positions adjacent to the pixel electrodes 9a.
[0039]
As shown in FIG. 7, the counter substrate 20 is further provided with a second light shielding film 23 in an area other than the opening area of each pixel portion. For this reason, incident light does not enter the channel region 1 a ′ or the LDD (Lightly Doped Drain) regions 1 b and 1 c of the semiconductor layer 1 a of the pixel switching TFT 30 from the counter substrate 20 side. Furthermore, the second light-shielding film 23 has functions such as improving contrast and preventing color mixture of color materials.
[0040]
Between the TFT array substrate 10 and the counter substrate 20, which are configured in this way and arranged so that the pixel electrode 9 a and the counter electrode 21 face each other, a liquid crystal is formed in a space surrounded by a sealing material (not shown). Is sealed to form the liquid crystal layer 50. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where the electric field from the pixel electrode 9a is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photocurable resin or a thermosetting resin for bonding the two substrates 10 and 20 around them, and is a glass for setting the distance between the two substrates to a predetermined value. Spacers such as fibers or glass beads are mixed.
[0041]
As shown in FIG. 7, a recess 203 is provided at a position corresponding to each pixel switching TFT 30 on the surface of the TFT array substrate 10 at a position facing each pixel switching TFT 30, and the first light shielding film is formed in each recess 203. 11a is provided. The surface of the TFT array substrate 10 and the first light shielding film 11a provided in each recess 203 constitute a flat surface. Here, the first light-shielding film 11a is preferably made of a simple metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pd, which are preferably opaque high melting point metals. The If comprised from such a material, the 1st light shielding film 11a will not be destroyed or melt | dissolved by the high temperature process in the formation process of the pixel switching TFT30 performed after the formation process of the 1st light shielding film 11a on the TFT array substrate 10 You can Since the first light shielding film 11a is formed, it is possible to prevent the return light from the TFT array substrate 10 from entering the channel region 1a ′ and the LDD regions 1b and 1c of the pixel switching TFT 30 in advance. The characteristics of the pixel switching TFT 30 as a transistor element do not deteriorate due to the generation of the photocurrent.
[0042]
Further, a first interlayer insulating film 12 is provided between the first light shielding film 11 a and the plurality of pixel switching TFTs 30. The first interlayer insulating film 12 is provided to electrically insulate the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light shielding film 11a. Further, the first interlayer insulating film 12 has a function as a base film for the pixel switching TFT 30 by being formed on the entire surface of the TFT array substrate 10. That is, the TFT array substrate 10 has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness during polishing of the surface of the TFT array substrate 10 and dirt remaining after cleaning. The first interlayer insulating film 12 is, for example, a highly insulating glass such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), or a silicon oxide film. It is made of a silicon nitride film or the like. The first interlayer insulating film 12 can also prevent the first light shielding film 11a from contaminating the pixel switching TFT 30 and the like.
[0043]
In the present embodiment, the gate insulating film 2 is extended from a position facing the scanning line 3a and used as a dielectric film, the semiconductor film 1a is extended to form the first storage capacitor electrode 1f, and further opposed thereto. A storage capacitor 70 is configured by using a part of the capacitor line 3b as a second storage capacitor electrode. More specifically, the high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a, and an insulating film is formed on the capacitor line 3b that extends along the data line 6a and the scanning line 3a. The first storage capacitor electrode (semiconductor layer) 1f is disposed so as to be opposed to each other. In particular, since the insulating film 2 as a dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the TFT 30 formed on the single crystal silicon layer by high-temperature oxidation, it can be a thin and high withstand voltage insulating film. The storage capacitor 70 can be configured as a large storage capacitor with a relatively small area.
[0044]
Further, as can be seen from FIGS. 6 and 7, in the storage capacitor 70, the first light shielding film 11a is connected to the first storage capacitor electrode 1f on the opposite side of the capacitor line 3b as the second storage capacitor electrode. By being arranged oppositely as a third storage capacitor electrode through the film 12 (see the storage capacitor 70 on the right side of FIG. 7), a storage capacitor is further provided. That is, in the present embodiment, a double storage capacitor structure in which storage capacitors are provided on both sides across the first storage capacitor electrode 1f is constructed, and the storage capacitor is further increased. Accordingly, the function of the liquid crystal device that prevents flicker and burn-in in the display image is improved.
[0045]
As a result, the space outside the opening area, that is, the area under the data line 6a and the area where the liquid crystal disclination occurs along the scanning line 3a (that is, the area where the capacitor line 3b is formed) is effectively used. Thus, the storage capacity of the pixel electrode 9a can be increased.
[0046]
In the present embodiment, in particular, the first light-shielding film 11a (and the capacitor line 3b electrically connected thereto) is electrically connected to a constant potential source, and the first light-shielding film 11a and the capacitor line 3b are provided with a constant potential. It is said. Therefore, the potential fluctuation of the first light shielding film 11a does not adversely affect the pixel switching TFT 30 disposed opposite to the first light shielding film 11a. Further, the capacitor line 3 b can function well as the second storage capacitor electrode of the storage capacitor 70. In this case, the constant potential source includes a negative power source supplied to a peripheral circuit for driving the liquid crystal device (for example, a scanning line driving circuit, a data line driving circuit, etc.), a constant potential source such as a positive power source, and a ground power source. And a constant potential source supplied to the counter electrode 21. By using a power source such as a peripheral circuit in this way, the light shielding film 11a and the capacitor line 3b can be set to a constant potential without the need for providing a dedicated potential wiring or an external input terminal.
[0047]
Further, as shown in FIGS. 6 and 7, in the present embodiment, the first light shielding film 11a is provided in the recess 203 provided in the TFT array substrate 10, and the surface of the TFT array substrate 10 and each recess 203 are provided. In addition to forming a flat surface with the provided first light-shielding film 11a, the first light-shielding film 11a is configured to be electrically connected to the capacitor line 3b at the preceding stage or the subsequent stage through the contact hole 13. ing. Therefore, compared with the case where each first light shielding film 11a is electrically connected to the capacitor line of its own stage, the capacitor line 3b and the first line are overlapped with the data line 6a along the edge of the opening region of the pixel portion. There are few steps with respect to the other area | region where the light shielding film 11a is formed. Thus, if there are few steps along the edge of the opening area of the pixel portion, the liquid crystal disclination (alignment failure) caused by the step can be reduced, so that the opening area of the pixel portion can be widened. Become.
[0048]
Further, in the first light shielding film 11a, the contact hole 13 is opened at the protruding portion protruding from the main line portion extending linearly as described above. Here, it has been found that, as the opening portion of the contact hole 13 is closer to the edge, cracks are less likely to occur due to the reason that stress is released from the edge. Therefore, in this case, depending on how close to the tip of the protruding portion the contact hole 13 is opened (preferably, depending on whether the contact hole 13 is close to the tip of the margin), the first light shielding film 11a is formed during the manufacturing process. Such stress is relieved, cracks can be prevented more effectively, and the yield can be improved.
[0049]
Further, the first light shielding film 11a is not formed at a position facing the scanning line 3a except for a position covering the channel region 1a '. Accordingly, since the capacitive coupling between the first light-shielding film 11a and each scanning line 3a hardly or practically occurs, the potential fluctuation in the first light-shielding film 11a is caused by the potential fluctuation in the scanning line 3a. As a result, there is no potential fluctuation in the capacitance line 3b.
[0050]
The capacitor line 3b and the scanning line 3a are made of the same polysilicon film, the dielectric film of the storage capacitor 70 and the gate insulating film 2 of the TFT 30 are made of the same high-temperature oxide film, and the first storage capacitor electrode 1f, the channel formation region 1a of the TFT 30, the source region 1d, the drain region 1e, and the like are made of the same semiconductor layer 1a. For this reason, the laminated structure formed on the TFT array substrate 10 can be simplified, and in the manufacturing method of the liquid crystal device described later, the capacitor line 3b and the scanning line 3a can be simultaneously formed in the same thin film forming process, and the storage capacitor 70 dielectric films and the gate insulating film 2 can be formed simultaneously.
[0051]
Further, the first light shielding film 11a extends along the scanning line 3a, and is divided into a plurality of stripes in the direction along the data line 6a. For this reason, for example, the first light shielding film 11a, the scanning line 3a, and the capacitor line 3b are formed as compared with the case where a grid-shaped light shielding film formed integrally around the opening region of each pixel portion is provided. In the laminated structure of the liquid crystal device comprising a polysilicon film, a metal film forming the data line 6a, an interlayer insulating film, etc., the stress generated by heating and cooling during the manufacturing process due to the difference in physical properties of each film is remarkably increased. Alleviated. For this reason, the generation of cracks in the first light-shielding film 11a and the like can be prevented and the yield can be improved.
[0052]
In FIG. 6, the straight main line portion of the first light shielding film 11a is formed so as to substantially overlap the linear main line portion of the capacitor line 3b. If it is provided at a position that covers the region and overlaps with the capacitor line 3b at any point so that the contact hole 13 can be formed, a light shielding function for the TFT and a function for reducing the resistance of the capacitor line can be exhibited. is there. Therefore, for example, the first light-shielding film 11a is provided even in a longitudinal gap region along the scanning line between the adjacent scanning line 3a and the capacitor line 3b or a position slightly overlapping with the scanning line 3a. Also good.
[0053]
The capacitor line 3b and the first light-shielding film 11a are reliably and highly reliable through the contact hole 13 opened in the first interlayer insulating film 12, and both are electrically connected. Such a contact hole 13 may be opened for each pixel, or may be opened for each pixel group including a plurality of pixels.
[0054]
When the contact hole 13 is opened for each pixel, the resistance of the capacitor line 3b can be reduced by the first light-shielding film 11a, and the degree of redundant structure between the two can be increased. On the other hand, when the contact hole 13 is opened for each pixel group composed of a plurality of pixels (for example, every 2 pixels or every 3 pixels), the sheet resistance, the driving frequency of the capacitor line 3b and the first light shielding film 11a, Taking into account the required specifications, etc., the benefits of the low resistance and redundant structure of the capacitor line 3b by the first light-shielding film 11a, the complexity of the manufacturing process by opening a large number of contact holes 13, or the liquid crystal device Since it is possible to properly balance the adverse effects such as the deterioration of the quality, it is very advantageous in practice.
[0055]
Further, the contact hole 13 provided for each pixel or each pixel group is formed under the data line 6a when viewed from the counter substrate 20 side. For this reason, the contact hole 13 is out of the opening region of the pixel portion, and is provided in the portion of the first interlayer insulating film 12 where the TFT 30 and the first storage capacitor electrode 1f are not formed. Defects of the TFT 30 and other wirings due to the formation of the contact hole 13 can be prevented while effectively utilizing.
[0056]
In FIG. 7 again, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and the channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a and the scanning line 3a. The gate insulating film 2 that insulates the scanning line 3a and the semiconductor layer 1a, the data line 6a, the low concentration source region (source side LDD region) 1b and the low concentration drain region (drain side LDD region) 1c of the semiconductor layer 1a, the semiconductor A high concentration source region 1d and a high concentration drain region 1e of the layer 1a are provided. A corresponding one of the plurality of pixel electrodes 9a is connected to the high concentration drain region 1e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e are doped with n-type or p-type dopants with a predetermined concentration depending on whether an n-type or p-type channel is formed in the semiconductor layer 1a. It is formed by doping. An n-type channel TFT has an advantage of high operating speed, and is often used as a pixel switching TFT 30 which is a pixel switching element. The data line 6a is composed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. A second contact hole 5 leading to the high concentration source region 1d and a contact hole 8 leading to the high concentration drain region 1e are formed on the scanning line 3a, the gate insulating film 2 and the first interlayer insulating film 12, respectively. An interlayer insulating film 4 is formed. The data line 6a is electrically connected to the high concentration source region 1d through the contact hole 5 to the source region 1b. Furthermore, on the data line 6a and the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8 to the high concentration drain region 1e is formed is formed. The pixel electrode 9a is electrically connected to the high concentration drain region 1e through the contact hole 8 to the high concentration drain region 1e. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured. The pixel electrode 9a and the high concentration drain region 1e may be electrically connected by relaying the same Al film as the data line 6a or the same polysilicon film as the scanning line 3b.
[0057]
The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c, and the gate electrode 3a is masked. Alternatively, a self-aligned TFT in which impurity ions are implanted at a high concentration to form high concentration source and drain regions in a self-aligning manner may be used.
[0058]
In addition, although a single gate structure in which only one gate electrode (scanning line 3a) of the pixel switching TFT 30 is disposed between the source-drain regions 1b and 1e is used, two or more gate electrodes are disposed therebetween. Also good. At this time, the same signal is applied to each gate electrode. If the TFT is constituted by a double gate or a triple gate or more in this way, a leakage current at the junction between the channel and the source-drain region can be prevented, and the off-state current can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.
[0059]
In general, single-crystal silicon layers such as the channel region 1a ′ and the low concentration source region 1b and the low concentration drain region 1c of the semiconductor layer 1a generate a photocurrent due to a photoelectric conversion effect of silicon when light enters. Although the transistor characteristics of the pixel switching TFT 30 deteriorate, in this embodiment, since the data line 6a is formed of a light-shielding metal thin film such as Al so as to cover the scanning line 3a from above, at least the semiconductor layer Incident light can be effectively prevented from entering the channel region 1a 'and the LDD regions 1b and 1c of 1a. Further, as described above, since the first light shielding film 11a is provided below the pixel switching TFT 30, the return light is incident on at least the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a. Can be effectively prevented.
[0060]
In this embodiment, since the capacitor line 3b provided in the adjacent upstream or downstream pixel is connected to the first light shielding film 11a, the first light shielding film is connected to the uppermost or lowermost pixel. The capacitor line 3b for supplying a constant potential to 11a is required. Therefore, it is preferable to provide one extra capacity line 3b with respect to the number of vertical pixels.
[0061]
(Method for Manufacturing Electro-Optical Device Using Process of Present Embodiment)
Next, a manufacturing process of the liquid crystal device having the above configuration will be described with reference to FIGS.
[0062]
8 to 12 are process diagrams showing the respective layers on the TFT array substrate side in each process corresponding to the AA cast surface of FIG. 6 in the same manner as FIG.
[0063]
As shown in step (1) in FIG. 8, a TFT array substrate 10 such as a quartz substrate or hard glass is prepared. Here, the annealing treatment is preferably performed in an inert gas atmosphere such as N 2 (nitrogen) and at a high temperature of about 850 to 1300 ° C., more preferably 1000 ° C., and distortion generated in the TFT array substrate 10 in a high-temperature process performed later is small. It pre-processes so that it may become. That is, the TFT array substrate 10 is heat-treated in advance at the same temperature or higher in accordance with the temperature at which the high temperature treatment is performed at the maximum temperature in the manufacturing process.
[0064]
A resist mask 207 corresponding to the pattern of the first light shielding film 11a (see FIG. 6) is formed on the TFT array substrate 10 thus processed by photolithography.
[0065]
Next, as shown in step (2), the TFT array substrate 10 is etched through the resist mask to form a recess 203 having a depth of about 100 to 500 nm, more preferably about 200 nm.
[0066]
Next, as shown in step (3), a metal such as Ti, Cr, W, Ta, Mo, and Pd, or a metal alloy such as metal silicide is formed on the entire surface of the TFT array substrate 10 having the recess 203 formed as described above. The light shielding film 11 having a layer thickness of about 100 to 500 nm, preferably about 200 nm is formed by sputtering.
[0067]
Next, as shown in step (4), the surface of the light shielding film 11 is globally polished and planarized until the surface of the substrate 10 is exposed while the light shielding film 11 formed in the recess 203 remains. As a planarization method by polishing, for example, a CMP (chemical mechanical polishing) method can be used.
[0068]
Next, as shown in step (5), a TEOS (tetraethylorthosilicate) gas, TEB, or the like is formed on the first light shielding film 11a as the remaining light shielding film 11 by, for example, atmospheric pressure or reduced pressure CVD. (Tetra-ethyl-boatrate) gas, TMOP (tetra-methyl-oxy-phosphate) gas, etc. are used to form silicate glass films such as NSG, PSG, BSG, BPSG, silicon nitride films, silicon oxide films, etc. A first interlayer insulating film 12 is formed. The layer thickness of the first interlayer insulating film 12 is, for example, about 400 to 1000 nm. More preferably, it is about 800 nm.
[0069]
Next, as shown in step (6), the substrate 10 and the single crystal silicon substrate 206a are bonded to each other. The single crystal silicon substrate 206a used for bonding has a thickness of 600 μm, and its surface is oxidized in advance by about 0.05 to 0.8 μm to form an oxide film layer 206b, and hydrogen ions (H +) are accelerated by, for example, an acceleration voltage of 100 keV. And implanted at a dose of 10e16 / cm 2. For the bonding step, for example, a method of directly bonding two substrates by heat treatment at 300 ° C. for 2 hours can be employed.
[0070]
Next, as shown in step (7), the single crystal silicon substrate 206a is separated from the substrate 10 while leaving the oxide film 206b and the single crystal silicon layer 206 on the bonded surface side of the bonded single crystal silicon substrate 206a. Heat treatment is performed. This substrate peeling phenomenon occurs because the hydrogen ions introduced into the single crystal silicon substrate break silicon bonds in a certain layer near the surface of the single crystal silicon substrate. For example, two bonded substrates can be heated to 600 ° C. at a temperature rising rate of 20 ° C. per minute. By this heat treatment, the bonded single crystal silicon substrate 206a is separated from the substrate 10, and a single crystal silicon layer 206 having a thickness of about 200 nm ± 5 nm is formed on the surface of the substrate 10. Note that the single crystal silicon layer 206 bonded to the substrate 10 is formed to have an arbitrary film thickness from 50 nm to 3000 nm by changing the acceleration voltage of hydrogen ion implantation performed on the single crystal silicon substrate 206a described above. Is possible.
[0071]
Next, as shown in step (8), the semiconductor layer 1a having a predetermined pattern as shown in FIG. 6 is formed by a photolithography process, an etching process, or the like. That is, in particular, in a region where the capacitor line 3b is formed under the data line 6a and a region where the capacitor line 3b is formed along the scanning line 3a, the first layer extending from the semiconductor layer 1a constituting the pixel switching TFT 30 is provided. One storage capacitor electrode 1f is formed.
[0072]
Next, as shown in step (9), the first storage capacitor electrode 1f together with the semiconductor layer 1a constituting the pixel switching TFT 30 is heated at a temperature of about 850 to 1300 ° C., preferably about 1000 ° C. for about 72 minutes. By oxidizing, a relatively thin thermal silicon oxide film having a thickness of about 60 nm is formed, and the gate insulating film 2 for forming a capacitor is formed together with the gate insulating film 2 of the pixel switching TFT 30. As a result, the thickness of the semiconductor layer 1a and the first storage capacitor electrode 1f is about 30 to 170 nm, and the thickness of the gate insulating film 2 is about 60 nm.
[0073]
Next, as shown in step (10) of FIG. 9, a resist film 301 is formed at a position corresponding to the N-channel semiconductor layer 1a, and a dopant 302 of a V group element such as P is applied to the P-channel semiconductor layer 1a. Doping is carried out at a low concentration (for example, P ions at an acceleration voltage of 70 keV and a dose of 2e11 / cm 2).
[0074]
Next, as shown in step (11), a resist film is formed at a position corresponding to the P-channel semiconductor layer 1a (not shown), and a dopant 303 of a group III element such as B is added to the N-channel semiconductor layer 1a. Doping is performed at a low concentration (for example, B ions at an acceleration voltage of 35 keV and a dose of 1e12 / cm 2).
[0075]
Next, as shown in step (12), a resist film 305 is formed on the surface of the substrate 10 excluding the end of the channel region 1a ′ of each semiconductor layer 1a for each P channel and N channel, and P is applied to the end 304. The dopant of a group V element such as P having a dose of about 1 to 10 times that of the step (10) for the channel, and the group III element such as B having a dose of about 1 to 10 times that of the step (11) for the N channel. Dopant 306 is doped.
[0076]
Next, as shown in step (13), in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor film 1a, a portion corresponding to the scanning line 3a (gate electrode) on the surface of the substrate 10 is used. A resist film 307 (wider than the scanning line 3a) is formed on the substrate, and a mask is used as a mask to form a V group element dopant 308 such as P at a low concentration (for example, an acceleration voltage of 70 keV for P ions, 3e14). Dope) (with a dose of / cm 2).
[0077]
Next, as shown in step (14) of FIG. 10, the contact hole 13 reaching the first light shielding film 11a is formed in the first interlayer insulating film 12 by dry etching such as reactive etching, reactive ion beam etching, or wet etching. To form. At this time, opening the contact hole 13 or the like by anisotropic etching such as reactive etching or reactive ion beam etching has an advantage that the opening shape can be made substantially the same as the mask shape. However, if a hole is formed by combining dry etching and wet etching, these contact holes 13 and the like can be tapered, so that an advantage of preventing disconnection at the time of wiring connection can be obtained.
[0078]
Next, as shown in step (15), after the polysilicon layer 3 is deposited with a thickness of about 350 nm by a low pressure CVD method or the like, phosphorus (P) is thermally diffused to make the polysilicon film 3 conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. Thereby, the conductivity of the polysilicon layer 3 can be increased.
[0079]
Next, as shown in the step (16), the capacitance line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. 6 by a photolithography process using a resist mask, an etching process, and the like. After this, the polysilicon remaining on the back surface of the substrate 10 is removed by etching while covering the surface of the substrate 10 with a resist film.
[0080]
Next, as shown in step (17), in order to form a P-channel LDD region in the semiconductor layer 1a, a position corresponding to the N-channel semiconductor layer 1a is covered with a resist film 309 (the figure shows an N-channel semiconductor). The layer 1a is shown.) Using the scanning line 3a (gate electrode) as a diffusion mask, a group 310 element dopant 310 such as B is first applied at a low concentration (for example, BF2 ions are accelerated at 90 keV, 3e13 / cm2). Doping is performed to form a low concentration source region 1b and a low concentration drain region 1c of the P channel.
[0081]
Subsequently, as shown in step (18), in order to form the P-channel high-concentration source region 1d and the high-concentration drain region 1e in the semiconductor layer 1a, the resist film 309 is positioned corresponding to the N-channel semiconductor layer 1a. Although not shown, a resist layer is formed on the scanning line 3a corresponding to the P channel with a mask wider than the scanning line 3a, but also a dopant of a group III element such as B 311 is doped at a high concentration (for example, BF2 ions at an acceleration voltage of 90 keV and a dose of 2e15 / cm <2>).
[0082]
Next, as shown in step (19) of FIG. 11, a position corresponding to the P-channel semiconductor layer 1a is covered with a resist film (not shown) in order to form an N-channel LDD region in the semiconductor layer 1a. Using the scanning line 3a (gate electrode) as a diffusion mask, a dopant 60 of a V group element such as P is doped at a low concentration (for example, P ions are accelerated at 70 keV and a dose of 6e12 / cm 2), and N A low concentration source region 1b and a low concentration drain region 1c of the channel are formed.
[0083]
Subsequently, as shown in step (20), in order to form the N-channel high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a, the resist layer 62 is formed with a mask wider than the scanning line 3a. After forming on the scanning line 3a corresponding to the N channel, similarly, a dopant 61 of a V group element such as P is doped at a high concentration (for example, P ions are accelerated at 70 keV at a dose of 4e15 / cm 2). .
[0084]
Next, as shown in step (21), NSG is used by using, for example, atmospheric pressure or reduced pressure CVD method, TEOS gas, or the like so as to cover the capacitor line 3b and the scan line 3a together with the scan line 3a in the pixel switching TFT 30. Then, a second interlayer insulating film 4 made of a silicate glass film such as PSG, BSG or BPSG, a silicon nitride film or a silicon oxide film is formed. The thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm, and more preferably 800 nm.
[0085]
Thereafter, an annealing process at about 850 ° C. is performed for about 20 minutes in order to activate the high concentration source region 1d and the high concentration drain region 1e.
[0086]
Next, as shown in step (22), the contact hole 5 for the data line 31 is formed by dry etching such as reactive etching or reactive ion beam etching or by wet etching. Further, contact holes for connecting the scanning lines 3 a and the capacitor lines 3 b to wirings (not shown) are also formed in the second interlayer insulating film 4 by the same process as the contact holes 5.
[0087]
Next, as shown in step (23) of FIG. 12, a light-shielding low-resistance metal such as Al, metal silicide, or the like is formed on the second interlayer insulating film 4 as a metal film 6 by sputtering or the like. The film is deposited to a thickness of 100 to 700 nm, preferably about 350 nm. Further, as shown in step (24), the data line 6a is formed by a photolithography process, an etching process, or the like.
[0088]
Next, as shown in step (25), a silicate glass film such as NSG, PSG, BSG, or BPSG is used to cover the data line 6a using, for example, atmospheric pressure or reduced pressure CVD or TEOS gas, A third interlayer insulating film 7 made of a silicon nitride film, a silicon oxide film or the like is formed. The layer thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm, and more preferably 800 nm.
[0089]
Next, as shown in step (26) of FIG. 13, in the pixel switching TFT 30, the contact hole 8 for electrically connecting the pixel electrode 9a and the high concentration drain region 1e is formed by reactive etching or reactive ion. It is formed by dry etching such as beam etching.
[0090]
Next, as shown in step (27), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 to a thickness of about 50 to 200 nm by sputtering or the like. As shown in the step (28), the pixel electrode 9a is formed by a photolithography process, an etching process, or the like. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.
[0091]
Subsequently, after applying a polyimide-based alignment film coating solution on the pixel electrode 9a, the alignment film 16 (see FIG. 7) is obtained by performing a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. Is formed.
[0092]
On the other hand, for the counter substrate 20 shown in FIG. 7, a glass substrate or the like is first prepared, and the second light-shielding film 23 and a second light-shielding film as a peripheral parting described later are sputtered with, for example, metallic chromium, and then a photolithography process. And formed through an etching process. These second light-shielding films may be formed from a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr, Ni, or Al.
[0093]
Then, the counter electrode 21 is formed by depositing a transparent conductive thin film such as ITO to a thickness of about 50 to 200 nm by sputtering or the like on the entire surface of the counter substrate 20. Further, after applying a polyimide-based alignment film coating solution over the entire surface of the counter electrode 21, the alignment film 22 (see FIG. 7) is formed by performing a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. It is formed.
[0094]
Finally, the TFT array substrate 10 on which the respective layers are formed as described above and the counter substrate 20 are bonded together with a sealing material 52 so that the alignment films 16 and 22 face each other, and a space between the two substrates is obtained by vacuum suction or the like. Further, for example, a liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked to form a liquid crystal layer 50 having a predetermined thickness.
[0095]
(Overall configuration of liquid crystal device)
The overall configuration of each embodiment of the liquid crystal device configured as described above will be described with reference to FIGS. 14 is a plan view of the TFT array substrate 10 as viewed from the side of the counter substrate 20 together with the components formed thereon, and FIG. FIG.
[0096]
In FIG. 14, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and in parallel with the inner side thereof, for example, as a peripheral parting made of the same or different material as the second light shielding film 23. The second light shielding film 53 is provided. A data line driving circuit 101 and a mounting terminal 102 are provided along one side of the TFT array substrate 10 in a region outside the sealing material 52, and the scanning line driving circuit 104 extends along two sides adjacent to the one side. Is provided. Needless to say, if the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuit 101 may be arranged on both sides along the side of the screen display area. For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit disposed along one side of the screen display area, and the even-numbered data lines extend along the opposite side of the screen display area. Alternatively, an image signal may be supplied from a data line driving circuit arranged in this manner. If the data lines 6a are driven in a comb-like shape in this way, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be configured. Further, a plurality of wirings 105 are provided on the remaining side of the TFT array substrate 10 to connect between the scanning line driving circuits 104 provided on both sides of the screen display region. A precharge circuit may be provided hidden under 53. Further, at least one corner portion of the counter substrate 20 is provided with a conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20. As shown in FIG. 15, the counter substrate 20 having substantially the same outline as the sealing material 52 shown in FIG. 14 is fixed to the TFT array substrate 10 by the sealing material 52.
[0097]
On the TFT array substrate 10 of the above liquid crystal device, an inspection circuit or the like for inspecting the quality, defects, etc. of the liquid crystal device in the middle of manufacture or at the time of shipment may be further formed. Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (tape automated bonding substrate) is connected to the periphery of the TFT array substrate 10. You may make it connect electrically and mechanically via the anisotropic conductive film provided in the part. Further, for example, a TN (twisted nematic) mode, an STN (super TN) mode, and a D-STN (dual scan) are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the outgoing light of the TFT array substrate 10 exits. -A polarizing film, a retardation film, a polarizing means, etc. are arranged in a predetermined direction according to the operation mode such as the -STN mode or the normally white mode / normally black mode.
[0098]
When the liquid crystal device described above is applied to, for example, a color liquid crystal projector (projection type display device), three liquid crystal devices are used as RGB light valves, and each panel is for RGB color separation. Each color light separated through the dichroic mirror is incident as projection light. Therefore, in this case, as shown in the above embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed. In this way, the liquid crystal device according to each embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflective type color liquid crystal television other than the liquid crystal projector. Furthermore, a microlens may be formed on the counter substrate 20 so as to correspond to one pixel. In this way, a bright liquid crystal device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that produces RGB colors by using interference of light may be formed by depositing several layers of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color liquid crystal device can be realized.
[0099]
In the liquid crystal device according to each of the embodiments described above, incident light is incident from the side of the counter substrate 20 as in the prior art. However, since the first light shielding film 11a is provided, from the side of the TFT array substrate 10. Incident light may be incident and emitted from the counter substrate 20 side. That is, even when the liquid crystal device is attached to the liquid crystal projector in this way, it is possible to prevent light from entering the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a and display a high-quality image. Is possible. Here, conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 10, it is necessary to separately arrange anti-reflection (AR) -coated polarizing means or to paste an AR film. there were. However, in each embodiment, since the first light shielding film 11a is formed between the surface of the TFT array substrate 10 and at least the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a, such an AR There is no need to use a polarizing means or an AR film that is coated, or to use a substrate in which the TFT array substrate 10 itself is subjected to an AR treatment. Therefore, according to each embodiment, it is possible to reduce the material cost, and it is very advantageous that the yield is not lowered due to dust, scratches or the like when the polarizing means is attached. In addition, since the light resistance is excellent, even when a bright light source is used or polarization conversion is performed by a polarization beam splitter to improve light use efficiency, image quality degradation such as crosstalk due to light does not occur.
[0100]
(Electronics)
As an example of an electronic apparatus using the above liquid crystal device, a configuration of a projection display device will be described with reference to FIGS. In FIG. 16, a projection display device 1100 is provided with three liquid crystal devices as described above, and shows a schematic configuration diagram of an optical system of a projection liquid crystal device used as RGB liquid crystal devices 962R, 962G, and 962B. The light source device 920 and the uniform illumination optical system 923 described above are employed in the optical system of the projection display device of this example. The projection display device includes a color separation optical system 924 as color separation means for separating the light beam W emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B); The three light valves 925R, 925G, and 925B as modulation means for modulating the color light beams R, G, and B, and the color synthesis prism 910 as color synthesis means for recombining the modulated color light beams are combined. A projection lens unit 906 is provided as projection means for enlarging and projecting the light beam onto the surface of the projection surface 100. A light guide system 927 that guides the blue light beam B to the corresponding light valve 925B is also provided.
[0101]
The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931, and the two lens plates 921 and 922 are arranged to be orthogonal to each other with the reflection mirror 931 interposed therebetween. The two lens plates 921 and 922 of the uniform illumination optical system 923 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is divided into a plurality of partial light beams by the rectangular lens of the first lens plate 921. These partial light beams are superimposed in the vicinity of the three light valves 925R, 925G, and 925B by the rectangular lens of the second lens plate 922. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has a non-uniform illuminance distribution in the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B can be uniformly illuminated. It can be illuminated.
[0102]
Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B and the green light beam G included in the light beam W are reflected at right angles and travel toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflecting mirror 943, and is emitted from the emission unit 944 of the red light beam R to the prism unit 910 side.
[0103]
Next, in the green reflection dichroic mirror 942, only the green light beam G of the blue and green light beams B and G reflected by the blue-green reflection dichroic mirror 941 is reflected at a right angle, and the color is emitted from the emission portion 945 of the green light beam G. The light is emitted to the side of the combining optical system. The blue light beam B that has passed through the green reflecting dichroic mirror 942 is emitted from the emission part 946 of the blue light beam B to the light guide system 927 side. In this example, the distances from the light beam W emission part of the uniform illumination optical element to the color light emission parts 944, 945, and 946 in the color separation optical system 924 are set to be substantially equal.
[0104]
Condensing lenses 951 and 952 are disposed on the emission side of the emission portions 944 and 945 for the red and green light beams R and G of the color separation optical system 924, respectively. Therefore, the red and green light beams R and G emitted from the respective emission portions are incident on these condenser lenses 951 and 952 and are collimated.
[0105]
The collimated red and green light beams R and G are incident on the light valves 925R and 925G and modulated, and image information corresponding to each color light is added. That is, these liquid crystal devices are subjected to switching control in accordance with image information by a driving unit (not shown), and thereby each color light passing therethrough is modulated. On the other hand, the blue light beam B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to the image information. The light valves 925R, 925G, and 925B in this example further include incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal devices 962R and 962G disposed therebetween. , 962B.
[0106]
The light guide system 927 includes a condensing lens 954 arranged on the emission side of the emission part 946 of the blue light beam B, an incident-side reflection mirror 971, an emission-side reflection mirror 972, and an intermediate lens arranged between these reflection mirrors. 973 and a condenser lens 953 disposed on the front side of the light valve 925B. The blue light beam B emitted from the condenser lens 946 is guided to the liquid crystal device 962B via the light guide system 927 and modulated. The optical path length of each color light beam, that is, the distance from the emission part of the light beam W to each liquid crystal device 962R, 962G, 962B is the longest for the blue light beam B, and therefore, the light amount loss of the blue light beam is the largest. However, the light loss can be suppressed by interposing the light guide system 927.
[0107]
The color light beams R, G, and B modulated through the light valves 925R, 925G, and 925B are incident on the color synthesis prism 910 and synthesized there. Then, the light synthesized by the color synthesis prism 910 is enlarged and projected onto the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.
[0108]
In this example, since the liquid crystal devices 962R, 962G, and 962B are provided with a light shielding layer on the lower side of the TFT, the liquid crystal devices 962R, 962G, and 962B depend on the projection optical system in the liquid crystal projector based on the projection light from the liquid crystal devices 962R, 962G, and 962B. Reflected light, reflected light from the surface of the TFT array substrate when the projected light passes through, a part of the projected light that penetrates the projection optical system after being emitted from another liquid crystal device, etc. as return light of the TFT array substrate Even if the light is incident from the side, the light shielding for the channel of the TFT for switching the pixel electrode can be sufficiently performed.
[0109]
For this reason, even if a prism unit suitable for miniaturization is used in the projection optical system, a film for preventing return light is separately arranged between the liquid crystal devices 962R, 962G, 962B and the prism unit, or the polarizing means is used. Since it is not necessary to perform a return light prevention process, it is very advantageous in reducing the size and simplification of the configuration.
[0110]
Further, in this embodiment mode, the influence of the return light on the channel region of the TFT can be suppressed. Therefore, it is not necessary to attach the polarizing means 961R, 961G, and 961B subjected to the return light prevention process directly to the liquid crystal device. . Therefore, as shown in FIG. 16, the polarizing means is formed apart from the liquid crystal device. More specifically, one polarizing means 961R, 961G, 961B is attached to the prism unit 910, and the other polarizing means 960R, 960G. , 960B can be attached to the condenser lenses 953, 945, and 944. Thus, by attaching the polarizing means to the prism unit or the condensing lens, the heat of the polarizing means is absorbed by the prism unit or the condensing lens, so that the temperature rise of the liquid crystal device can be prevented.
[0111]
Although not shown, an air layer is formed between the liquid crystal device and the polarizing means by forming the liquid crystal device and the polarizing means apart from each other, so a cooling means is provided between the liquid crystal device and the polarizing means. By sending air such as cold air into the liquid crystal, it is possible to further prevent the temperature of the liquid crystal device from rising and to prevent malfunction due to the temperature rise of the liquid crystal device.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a basic structure of an electro-optical device according to the invention.
FIG. 2 is a process diagram (part 1) illustrating a manufacturing process of the electro-optical device illustrated in FIG. 1 in order.
3 is a process diagram (part 2) illustrating the manufacturing process of the electro-optical device illustrated in FIG. 1 in order. FIG.
FIG. 4 is a process diagram (part 3) illustrating the manufacturing process of the electro-optical device illustrated in FIG. 1 in order.
FIG. 5 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix pixels that form an image forming area in an embodiment of a liquid crystal device.
FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light shielding films, and the like are formed in an embodiment of a liquid crystal device.
7 is a cross-sectional view taken along the line A-A ′ of FIG. 6;
FIG. 8 is a process diagram (part 1) illustrating a manufacturing process of an embodiment of the liquid crystal device in order.
FIG. 9 is a process diagram (part 2) illustrating the manufacturing process of the embodiment of the liquid crystal device in order.
FIG. 10 is a process diagram (part 3) illustrating the manufacturing process of the embodiment of the liquid crystal device in order.
FIG. 11 is a process diagram (part 4) illustrating the manufacturing process of the embodiment of the liquid crystal device in order.
FIG. 12 is a process diagram (part 5) illustrating the manufacturing process of the embodiment of the liquid crystal device in order.
FIG. 13 is a process diagram (part 6) illustrating the manufacturing process of the embodiment of the liquid crystal device in order.
FIG. 14 is a plan view of a TFT array substrate in each embodiment of the liquid crystal device as viewed from the counter substrate side together with the components formed thereon.
15 is a cross-sectional view taken along the line H-H ′ of FIG. 13;
FIG. 16 is a configuration diagram of a projection display device which is an example of an electronic apparatus using a liquid crystal device.
[Explanation of symbols]
1a ... Semiconductor layer
1a '... channel region
1b. Low concentration source region (source side LDD region)
1c: Low concentration drain region (drain side LDD region)
1d ... High concentration source region
1e ... High concentration drain region
10 ... TFT array substrate
11a ... 1st light shielding film
12 ... 1st interlayer insulation film
202 ... Light transmissive substrate
203 ... recess
204 ... Light shielding layer
205 ... Insulator layer
205 ... single crystal silicon layer

Claims (7)

A method of manufacturing an electro-optical device in which a plurality of pixel electrodes and a transistor element region corresponding to each pixel electrode are formed in an image display region on a light-transmitting substrate,
Forming a recess on one surface of the light transmitting substrate,
Forming a light-shielding layer on one surface of the light-transmitting substrate in which the recess is formed;
Removing the light shielding layer until the one surface of the light transmissive substrate is exposed while the light shielding layer formed in the recess remains, and planarizing the one surface of the light transmissive substrate;
Forming an insulator layer on one surface of the planarized light-transmitting substrate;
Bonding a single crystal silicon layer to the surface of the insulator layer ;
And a step of forming the transistor element region at a position corresponding to the light shielding layer of the bonded single crystal silicon layer .   2. The method of manufacturing an electro-optical device according to claim 1, wherein in the step of flattening one surface of the light transmissive substrate, the light shielding layer is removed by a chemical mechanical polishing method. An electro-optical device in which a plurality of pixel electrodes and a transistor element region corresponding to each pixel electrode are formed in an image display region on a light transmissive substrate,
And the light-transmitting substrate which recess is provided,
A light-shielding layer formed so as to fill the concave portion of the light-transmitting substrate;
An insulator layer provided on the light-transmitting substrate on which the light shielding layer is formed;
Wherein formed on the insulating layer, an electro-optical device characterized by comprising a single crystal silicon layer in which the transistor element area at a position corresponding are formed in the light shielding layer. 4. The electro-optical device according to claim 3 , wherein the light transmissive substrate is made of quartz, and the light shielding layer is made of a refractory metal or a silicon compound of a refractory metal. The electro-optical device according to claim 3, wherein the light shielding layer is electrically connected to a peripheral circuit provided around the image display area. Another light-transmitting substrate disposed to face the surface of the light-transmitting substrate on which the single crystal silicon layer is formed;
6. The liquid crystal device according to claim 3 , further comprising: a liquid crystal sandwiched between the two light-transmitting substrates and driven by a transistor element formed in the transistor element region. The electro-optical device described. A light source;
The electro-optical device according to claim 6, wherein light emitted from the light source is incident to perform modulation corresponding to image information;
Projection means for projecting light modulated by the electro-optical device.

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