JP2008241978A - ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - Google Patents

Abstract

Contact resistance is reduced.
On a substrate, a conductive layer 402, a transparent electrode 9a, an interlayer insulating film 44 formed between the conductive layer and the transparent electrode, and the conductive layer and the transparent electrode are electrically connected at a contact portion. A contact hole 89 opened in the interlayer insulating film for connection, and a titanium oxide film 17 provided between the conductive layer and the transparent electrode at least in the contact portion. Features.
[Selection] Figure 1

Description

  The present invention relates to an electro-optical device in which a conductive layer has a light shielding function, a manufacturing method thereof, and an electronic apparatus.

  The liquid crystal device is configured by sealing liquid crystal between two substrates such as a glass substrate and a quartz substrate. In a liquid crystal device, active elements such as thin film transistors (hereinafter referred to as TFTs) and pixel electrodes are arranged in a matrix on one substrate, and a counter electrode (transparent electrode (ITO (Indium Tin)) is disposed on the other substrate. Oxide))) is arranged to change the optical characteristics of the liquid crystal layer sealed between the two substrates according to the image signal, thereby enabling image display.

  In an electro-optical device such as an active matrix driving type liquid crystal device using an active element, a pixel corresponding to each intersection of a large number of scanning lines (gate lines) and data lines (source lines) arranged vertically and horizontally, respectively. An electrode and a switching element are provided on a substrate (active matrix substrate).

  A switching element such as a TFT element is turned on by an on signal supplied to the gate line, and an image signal supplied via the source line is written to the pixel electrode (transparent electrode (ITO)). Thereby, a voltage based on the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode to change the arrangement of the liquid crystal molecules. In this way, the transmittance of the pixel is changed, and light passing through the pixel electrode and the liquid crystal layer is changed according to the image signal to perform image display.

  By the way, when each element constituting the element substrate is formed on one plane on the substrate, the area occupied by the element increases, the area of the pixel electrode portion decreases, and the pixel aperture ratio decreases. Therefore, conventionally, a stacked structure is employed in which each element is formed by being divided into a plurality of layers, and an interlayer insulating film is disposed between the layers.

  That is, the element substrate is configured by laminating a semiconductor thin film, an insulating thin film, or a conductive thin film having a predetermined pattern on a glass or quartz substrate. A TFT substrate is formed by repeating various film formation processes and photolithography processes for each layer.

  For example, on the TFT substrate, a semiconductor layer constituting a channel of the TFT element, a wiring layer such as a data line, a pixel electrode layer made of an ITO film, and the like are laminated. The pixel electrode layer is formed on the uppermost layer of the active matrix substrate adjacent to the liquid crystal layer, and the pixel electrode is connected to the semiconductor layer via the wiring layer. Generally, a wiring layer such as a data line is formed of aluminum, for example. However, when aluminum and the ITO film are connected through a contact hole, an electrolytic corrosion that causes the ITO film to darken by an alkaline stripping solution used for patterning occurs.

Therefore, by employing a wiring layer having a multilayer structure in which titanium nitride (TiN) is laminated on aluminum, electrolytic corrosion is prevented. Such a conductive layer having a multilayer structure of aluminum and titanium nitride is disclosed in Patent Document 1 and the like.
JP 2005-242296 A

  By the way, the sheet resistance of the ITO film is several tens of ohms. On the other hand, the contact resistance between ITO and the titanium nitride film connected to ITO is about 1000 to 10,000 Ω. That is, the contact resistance between the titanium nitride film and the ITO in the contact hole portion is dominant between the aluminum wiring layer and the pixel electrode, and there is a problem that the contact resistance is relatively high.

  An object of the present invention is to provide an electro-optical device, a manufacturing method thereof, and an electronic apparatus that can reduce contact resistance by providing a titanium oxide film below an ITO film.

  The electro-optical device according to the present invention includes a conductive layer, a transparent electrode, an interlayer insulating film formed between the conductive layer and the transparent electrode, a contact portion on the substrate, and the conductive layer and the transparent electrode. And a titanium oxide film provided between the conductive layer and the transparent electrode at least in the contact portion. Features.

  According to such a configuration, the conductive layer and the transparent electrode are electrically connected using the contact hole formed by opening the interlayer insulating film. A titanium oxide film is formed at least at the contact portion between the conductive layer and the transparent electrode. The resistance between the conductive layer and the titanium oxide film is sufficiently low, and the contact resistance between the conductive layer and the transparent electrode in the contact portion can be sufficiently reduced.

  The titanium oxide film is formed in the same plane shape as the transparent electrode.

  According to such a configuration, the titanium oxide film and the transparent electrode can be formed on the entire surface and patterned simultaneously, and an increase in the number of manufacturing steps can be suppressed.

  The titanium oxide film is formed only in the contact hole and in the vicinity thereof.

  According to such a configuration, the contact resistance between the conductive layer and the transparent electrode in the contact portion can be sufficiently reduced.

  The method of manufacturing an electro-optical device according to the present invention includes a step of forming a conductive layer on a substrate, a step of forming an interlayer insulating film on the conductive layer, and contacting the conductive layer and the transparent electrode. Forming a contact hole in the interlayer insulating film for electrical connection at a portion, and forming a titanium film in a region including at least a contact portion for electrically connecting the conductive layer and the transparent electrode And a step of forming a transparent electrode electrically connected to the conductive layer via the titanium film in a region including at least the titanium film.

  According to such a configuration, the titanium film is formed in a region including at least a contact portion that electrically connects the conductive layer and the transparent electrode. Thereby, the contact resistance between the conductive layer and the transparent electrode in the contact portion can be sufficiently reduced.

  In the method of manufacturing an electro-optical device according to the invention, the step of forming the titanium film and the step of forming the transparent electrode include a step of forming a titanium film in the entire region including the conductive layer, and the interlayer insulation. The method includes a step of forming a transparent electrode over the entire region including on the film, and a step of patterning the titanium film and the transparent electrode using the same mask.

  According to such a configuration, when the titanium film and the transparent electrode are patterned, after forming the titanium film and the transparent electrode in the entire region, the patterning may be performed simultaneously using the same mask, which increases the number of manufacturing steps. Can be suppressed.

  According to another aspect of the present invention, the titanium film and the transparent electrode are stacked, and the titanium film is changed to a titanium oxide film.

  According to such a configuration, the titanium film is formed in a region including at least a contact portion that electrically connects the conductive layer and the transparent electrode. The titanium film changes to a titanium oxide film, and the conductive layer and the transparent electrode are electrically connected through the titanium oxide film. Thereby, the contact resistance between the conductive layer and the transparent electrode in the contact portion can be sufficiently reduced.

  According to another aspect of the invention, an electronic apparatus includes the electro-optical device.

  According to such a configuration, since the contact resistance between the conductive layer and the pixel electrode can be reduced, it is possible to satisfactorily maintain the voltage application to the pixel electrode or the potential holding characteristic of the pixel electrode a. It becomes possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a cross-sectional structure of the electro-optical device according to the first embodiment of the invention. This embodiment is applied to a liquid crystal device such as a TFT substrate. FIG. 2 is a plan view of the liquid crystal device, which is the electro-optical device according to the present embodiment, viewed from the counter substrate side together with the components formed thereon. FIG. 3 is a cross-sectional view of the liquid crystal device after the assembly process in which the element substrate and the counter substrate are bonded to each other and the liquid crystal is sealed is cut along the line HH ′ in FIG. FIG. 4 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels constituting the pixel region of the liquid crystal device. FIG. 5 is a plan view showing a part of the film formation pattern of each layer for a plurality of adjacent pixels formed on the TFT substrate of this embodiment. FIG. 6 is a flowchart showing a part of the manufacturing method of the liquid crystal device of FIG. FIG. 7 is a process diagram showing a part of the process of the manufacturing method of FIG. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

First, an overall configuration of a liquid crystal device which is an electro-optical device according to the present embodiment will be described with reference to FIGS.
As shown in FIGS. 2 and 3, the liquid crystal device is configured by enclosing a liquid crystal 50 between a TFT substrate 10 which is an element substrate and a counter substrate 20. On the TFT substrate 10, pixel electrodes (ITO) 9a constituting pixels are arranged in a matrix. A counter electrode (ITO) 21 is provided on the entire surface of the counter substrate 20. FIG. 4 shows an equivalent circuit of elements on the TFT substrate 10 constituting the pixel.

  As shown in FIG. 4, in the pixel region, a plurality of scanning lines 11a and a plurality of data lines 6a are wired so as to cross each other, and a pixel electrode is formed in a region partitioned by the scanning lines 11a and the data lines 6a. 9a are arranged in a matrix. A TFT 30 is provided corresponding to each intersection of the scanning line 11 a and the data line 6 a, and the pixel electrode 9 a is connected to the TFT 30.

  The TFT 30 is turned on by the ON signal of the scanning line 11a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50.

  A storage capacitor 70 is provided in parallel with the pixel electrode 9a. The storage capacitor 70 extends the holding time of the voltage applied to the liquid crystal 50. For example, the image signal is held for a period that is three orders of magnitude longer than the time supplied to the pixel electrode 9a. The voltage holding characteristic is improved, and an image display with a high contrast ratio is possible.

  FIG. 1 is a schematic cross-sectional view of a liquid crystal device focusing on one pixel, and FIG. 5 is a plan view showing a film forming pattern of a main part.

  In FIG. 5, a plurality of pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a (broken lines) and scanning lines 11a (shown in FIG. 5) are arranged along the vertical and horizontal boundaries of the pixel electrodes 9a. (Omitted) is provided. As will be described later, the data line 6a has a laminated structure including an aluminum film, and the scanning line 11a is made of, for example, a conductive polysilicon film. Further, the scanning line 11a is electrically connected to the gate electrode 3a (broken line) facing the channel region 1a 'indicated by the hatched region rising to the right in the drawing in the semiconductor layer 1a. That is, the pixel switching TFT 30 is configured by disposing the gate electrode 3a and the channel region 1a 'connected to the scanning line 11a so as to face each other at the intersection of the scanning line 11a and the data line 6a.

  As shown in FIG. 1, which is a cross-sectional view taken along the line AA 'of FIG. And a counter substrate 20 made of a quartz substrate.

  As shown in FIG. 1, a pixel electrode 9a is provided on the TFT substrate 10 side, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO film. On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 that has been subjected to a predetermined alignment process such as a rubbing process is provided on the entire surface. The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, and the alignment films 16 and 22 are made of a transparent organic film such as a polyimide film, for example, similarly to the pixel electrode 9a.

  Between the TFT substrate 10 and the counter substrate 20 arranged so as to face each other, an electro-optical material such as liquid crystal is sealed in a space surrounded by a sealing material 52 (see FIGS. 2 and 3), and a liquid crystal 50 is formed. The The liquid crystal 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal 50 is made of, for example, an electro-optical material in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material 52 is an adhesive made of, for example, a photocurable resin or a thermosetting resin, for bonding the TFT substrate 10 and the counter substrate 20 around them, and the distance between the two substrates is set to a predetermined value. Spacers such as glass fibers or glass beads are mixed.

  On the other hand, on the TFT substrate 10, in addition to the pixel electrode 9a and the alignment film 16, various configurations including these are provided in a laminated structure. As shown in FIG. 1, this stacked structure includes a first layer (film formation layer) including a scanning line 11a, a second layer including a TFT 30 including a gate electrode 3a, and a third layer including a storage capacitor 70 in order from the bottom. A fourth layer including a data line 6a, a fifth layer including a shield layer 400, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and a titanium oxide film 17 described later. . Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. A third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, and a fourth interlayer insulating film 44 is provided between the fifth layer and the sixth layer, so that the above-described elements are short-circuited. Is preventing. Further, these various insulating films 12, 41, 42, 43 and 44 are also provided with, for example, a contact hole for electrically connecting the high concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. It has been. Hereinafter, each of these elements will be described in order from the bottom.

  The first layer includes, for example, a simple metal or alloy containing at least one of high melting point metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). A scanning line 11a made of metal silicide, polysilicide, a laminate of these, or conductive polysilicon is provided. The scanning lines 11a are patterned in stripes along the X direction in FIG. More specifically, the stripe-shaped scanning line 11a includes a main line portion extending along the X direction in FIG. 5 and a protruding portion extending in the Y direction in FIG. 5 where the data line 6a or the shield layer 400 extends. ing. Note that the protruding portions extending from the adjacent scanning lines 11a are not connected to each other, and therefore, the scanning lines 11a are divided one by one.

  Thus, the scanning line 11a has a function of simultaneously controlling ON / OFF of the TFTs 30 existing in the same row. Further, since the scanning line 11a is formed so as to substantially fill a region where the pixel electrode 9a is not formed, the scanning line 11a also has a function of blocking light entering the TFT 30 from below. Thereby, generation of light leakage current in the semiconductor layer 1a of the TFT 30 is suppressed, and high-quality image display without flicker or the like is possible.

  In the second layer, the TFT 30 including the gate electrode 3a is provided. As shown in FIG. 1, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes the gate electrode 3a described above, for example, a polysilicon film, and a channel formed by an electric field from the gate electrode 3a. The channel region 1a ′ of the semiconductor layer 1a to be formed, the insulating film 2 including a gate insulating film that insulates the gate electrode 3a from the semiconductor layer 1a, the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a, and the high concentration. A source region 1d and a high concentration drain region 1e are provided.

  In the second layer, a relay electrode 719 is formed as the same film as the gate electrode 3a described above. The relay electrode 719 is formed in an island shape so as to be positioned approximately at the center of one side of each pixel electrode 9a when seen in a plan view. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of a conductive polysilicon film or the like, the former is also made of a conductive polysilicon film or the like.

  The TFT 30 described above preferably has an LDD structure as shown in FIG. 1, but may have an offset structure in which no impurity is implanted into the low concentration source region 1b and the low concentration drain region 1c. A self-aligned TFT that implants impurities at a high concentration as a mask and forms a high concentration source region and a high concentration drain region in a self-aligning manner may be used. In the present embodiment, only one gate electrode of the pixel switching TFT 30 is arranged between the high concentration source region 1d and the high concentration drain region 1e. However, two or more gates are interposed between them. An electrode may be arranged. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the off-time current can be reduced. Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single crystal layer or a single crystal layer. A known method such as a bonding method can be used for forming the single crystal layer. By making the semiconductor layer 1a a single crystal layer, it is possible to improve the performance of peripheral circuits in particular.

  A base insulating film 12 made of, for example, a silicon oxide film is provided on the scanning line 11a described above and below the TFT 30. In addition to the function of insulating the TFT 30 from the scanning line 11a to the interlayer, the base insulating film 12 is formed on the entire surface of the TFT substrate 10 so that the pixel switching is performed due to roughness during polishing of the surface of the TFT substrate 10 and dirt remaining after cleaning. The TFT 30 has a function of preventing characteristic changes.

  In the base insulating film 12, grooves (contact holes) 12cv having the same width as the channel length of the semiconductor layer 1a extending along the data line 6a described later are dug on both sides of the semiconductor layer 1a in plan view. Corresponding to the groove 12cv, the gate electrode 3a stacked above includes a portion formed in a concave shape on the lower side. Further, since the gate electrode 3a is formed so as to fill the entire groove 12cv, a side wall portion 3b formed integrally with the gate electrode 3a is extended. Yes. As a result, the semiconductor layer 1a of the TFT 30 is covered from the side as viewed in a plan view, and at least light from this portion is prevented from entering.

  The side wall 3b is formed so as to fill the groove 12cv, and its lower end is in contact with the scanning line 11a. Here, since the scanning line 11a is formed in a stripe shape as described above, the gate electrode 3a and the scanning line 11a existing in a certain row are always at the same potential as long as attention is paid to the row.

  A structure in which another scanning line including the gate electrode 3a is formed so as to be parallel to the scanning line 11a may be employed. In this case, the scanning line 11a and the other scanning line have a redundant wiring structure. Thereby, for example, even when a part of the scanning line 11a has some defect and normal energization is impossible, another scanning line in the same row as the scanning line 11a is not present. As long as it is sound, the operation control of the TFT 30 can still be normally performed through the soundness.

  In the third layer, a storage capacitor 70 is provided. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through. According to the storage capacitor 70, it is possible to remarkably improve the potential holding characteristic in the pixel electrode 9a. Further, since the storage capacitor 70 is formed so as not to reach the light transmission region substantially corresponding to the formation region of the pixel electrode 9a (in other words, formed so as to be within the light shielding region), The pixel aperture ratio of the entire electro-optical device is kept relatively large, and thus a brighter image can be displayed.

  More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the lower electrode 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy. In addition to the function as a pixel potential side capacitor electrode, the lower electrode 71 has a function of relay-connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30. This relay connection is performed via the relay electrode 719 as described later.

  The capacitor electrode 300 functions as a fixed potential side capacitor electrode of the storage capacitor 70. In order to set the capacitor electrode 300 to a fixed potential, the capacitor electrode 300 is electrically connected to the shield layer 400 having a fixed potential.

  The capacitor electrode 300 is formed in an island shape on the TFT substrate 10 so as to correspond to each pixel, and the lower electrode 71 is formed to have substantially the same shape as the capacitor electrode 300. . As a result, the storage capacitor 70 does not have a wasteful spread in a plane, that is, without decreasing the pixel aperture ratio, and can achieve the maximum capacitance value under the circumstances. That is, the storage capacitor 70 has a smaller area and a larger capacitance value.

  The dielectric film 75 is made of, for example, a relatively thin HTO (High Temperature Oxide) film having a thickness of about 5 to 200 nm, a silicon oxide film such as an LTO (Low Temperature Oxide) film, or a silicon nitride film. From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 75 is, the better as long as the reliability of the film is sufficiently obtained. As shown in FIG. 1, the dielectric film 75 has a two-layer structure including a silicon oxide film 75a as a lower layer and a silicon nitride film 75b as an upper layer. The presence of the silicon nitride film 75b having a relatively large dielectric constant makes it possible to increase the capacitance value of the storage capacitor 70, and the presence of the silicon oxide film 75a reduces the pressure resistance of the storage capacitor 70. I won't let you down. Thus, by making the dielectric film 75 have a two-layer structure, it is possible to enjoy two conflicting effects.

  In addition, the presence of the silicon nitride film 75b makes it possible to prevent water from entering the TFT 30 in advance. As a result, a situation in which the threshold voltage of the TFT 30 rises is not caused, and a relatively long-term apparatus operation is possible. In the present embodiment, the dielectric film 75 has a two-layer structure. However, the dielectric film 75 has a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, or more. You may comprise so that it may have the laminated structure of these.

  On the TFT 30 to the gate electrode 3a and the relay electrode 719 described above and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass), a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed. In the first interlayer insulating film 41, a contact hole 81 that electrically connects the high-concentration source region 1d of the TFT 30 and a data line 6a described later opens while penetrating the second interlayer insulating film 42 described later. It is holed. The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high-concentration drain region 1 e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70.

  Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 serving as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, a contact hole 882 that electrically connects the relay electrode 719 and a second relay electrode 6a2 described later is opened in the first interlayer insulating film 41 while penetrating the second interlayer insulating film described later. ing.

  As shown in FIG. 1, the contact hole 882 is formed in a region other than the storage capacitor 70, and the lower electrode 71 is once detoured to the lower relay electrode 719 and drawn out to the upper layer through the contact hole 882. Therefore, even when the lower electrode 71 is connected to the upper pixel electrode 9 a, it is not necessary to form the lower electrode 71 wider than the dielectric film 75 and the capacitor electrode 300. Therefore, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be simultaneously patterned in one etching process. As a result, the etching rates of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be easily controlled, and the degree of freedom in designing the film thickness and the like can be increased.

  In addition, since the dielectric film 75 is formed in the same shape as the lower electrode 71 and the capacitor electrode 300 and does not have a spread, in the case of performing a hydrogenation process on the semiconductor layer 1 a of the TFT 30, It is also possible to obtain an effect that it is possible to easily reach the semiconductor layer 1a through the opening around the storage capacitor 70.

  The first interlayer insulating film 41 may be fired at about 1000 ° C. to activate ions implanted into the polysilicon film constituting the semiconductor layer 1a and the gate electrode 3a.

  A data line 6a is provided in the fourth layer. The data line 6a is formed in a stripe shape so as to coincide with the extending direction of the semiconductor layer 1a of the TFT 30, that is, to overlap the Y direction in FIG. As shown in FIG. 1, the data line 6a includes, in order from the lower layer, a layer made of aluminum (reference numeral 41A in FIG. 1), a layer made of titanium nitride (see reference numeral 41TN in FIG. 1), and a layer made of a silicon nitride film (see FIG. It is formed as a film having a three-layer structure denoted by reference numeral 401 in FIG. The silicon nitride film is patterned to a slightly larger size so as to cover the lower aluminum layer and titanium nitride layer. Of these, the data line 6a contains aluminum, which is a relatively low resistance material, so that the supply of image signals to the TFT 30 and the pixel electrode 9a can be realized without delay. On the other hand, the formation of a silicon nitride film that is relatively excellent in preventing moisture from entering on the data line 6a can improve the moisture resistance of the TFT 30, and can achieve a long life. The silicon nitride film is preferably a plasma silicon nitride film.

  In addition, a shield layer relay layer 6a1 and a second relay electrode 6a2 are formed on the fourth layer as the same film as the data line 6a. As shown in FIG. 5, these are not formed so as to have a planar shape continuous with the data line 6 a when viewed in a plan view, but are formed so as to be separated from each other by patterning. Yes. That is, paying attention to the data line 6a located on the leftmost side in FIG. 5, the shield layer relay layer 6a1 having a substantially quadrilateral shape on the right side and further slightly larger than the shield layer relay layer 6a1 on the right side. A second relay electrode 6a2 having a substantially quadrilateral shape with the following area is formed. The shield layer relay layer 6a1 and the second relay electrode 6a2 are in the same process as the data line 6a, and have a three-layer structure of an aluminum layer, a titanium nitride layer, and a plasma nitride film layer in order from the lower layer. It is formed as. The plasma nitride film is patterned to a slightly larger size so as to cover the lower aluminum layer and titanium nitride layer. The titanium nitride layer functions as a barrier metal for preventing etching through of the contact holes 803 and 804 formed for the shield layer relay layer 6a1 and the second relay electrode 6a2. Further, by forming a plasma nitride film that is relatively excellent in the action of blocking moisture ingress on the shield layer relay layer 6a1 and the second relay electrode 6a2, the moisture resistance of the TFT 30 can be improved. Longer service life can be realized. The plasma nitride film is preferably a plasma silicon nitride film.

  Above the storage capacitor 70 and below the data line 6a, for example, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a plasma CVD method using TEOS gas A second interlayer insulating film 42 formed by the above is formed. In the second interlayer insulating film 42, a contact hole 81 for electrically connecting the high concentration source region 1d of the TFT 30 and the data line 6a is opened, and the shield layer relay layer 6a1 and the storage capacitor 70 are formed. A contact hole 801 is formed to electrically connect the capacitor electrode 300, which is the upper electrode. Further, a contact hole 882 for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.

  A shield layer 400 is formed on the fifth layer. When viewed in plan, the shield layer 400 is formed in a lattice shape so as to extend in the X direction and the Y direction in the drawing, as shown in FIG. Of the shield layer 400, the portion extending in the Y direction in the figure is formed to cover the data line 6a and to be wider than the data line 6a. Further, in the portion extending in the X direction in the drawing, a notch is formed near the center of one side of each pixel electrode 9a in order to secure a region for forming a third relay electrode 402 which is a “conductive layer” described later. have.

  The shield layer 400 extends from the image display region 10a in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source so as to have a fixed potential. The constant potential source may be a positive potential source or a negative potential constant source supplied to the data line driving circuit 101 described later, or a constant potential source supplied to the counter electrode 21 of the counter substrate 20.

  Thus, the capacitance formed between the data line 6a and the pixel electrode 9a is formed so as to cover the entire data line 6a (see FIG. 5), and the presence of the shield layer 400 at a fixed potential. It becomes possible to eliminate the influence of coupling. That is, it is possible to avoid a situation in which the potential of the pixel electrode 9a fluctuates in response to the energization of the data line 6a, and the possibility of causing display unevenness along the data line 6a on the image. Can be reduced. Since the shield layer 400 is formed in a lattice shape, it is possible to suppress this so that unnecessary capacitance coupling does not occur in the portion where the scanning line 11a extends. In the present embodiment, the shield layer 400 has a two-layer structure in which the lower layer is a conductive film 400a made of aluminum and the upper layer is a titanium nitride layer 400b.

  In the fifth layer, a third relay electrode 402 as a relay layer is formed as the same layer as the shield layer 400. The third relay electrode 402 also has a two-layer structure of a conductive film 402a made of aluminum in the lower layer and an electrolytic corrosion prevention film 402b made of titanium nitride in the upper layer. The shield layer 400 and the third relay electrode 402 are not continuously formed in a planar shape, but are formed so as to be separated by patterning.

  The shield layer 400 and the third relay electrode 402 include aluminum that is relatively excellent in light reflection performance, and can function as a light shielding layer. That is, according to these, it is possible to block the progress of incident light (see FIG. 1) on the semiconductor layer 1a of the TFT 30 on the upper side thereof. In addition, the capacitor electrode 300 and the data line 6a described above have the same light shielding function. The shield layer 400, the third relay electrode 402, the capacitor electrode 300, and the data line 6 a form an upper light-shielding film that blocks light incident on the TFT 30 from the upper side while forming a part of the laminated structure constructed on the TFT substrate 10. Function.

  Over the data line 6a and under the shield layer 400, a silicate glass film such as NSG, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a plasma CVD method using TEOS gas A third interlayer insulating film 43 is formed. In the third interlayer insulating film 43, a contact hole 803 for electrically connecting the shield layer 400 and the shield layer relay layer 6a1, and a third relay electrode 402 and the second relay electrode 6a2 are electrically connected. Contact holes 804 for connecting to each are opened.

  The second interlayer insulating film 42 may be relieved of stress generated in the vicinity of the interface of the capacitor electrode 300 by not performing the above-described firing with respect to the first interlayer insulating film 41.

In the present embodiment, a titanium oxide film 17 is formed in the sixth layer. The pixel electrodes 9a are formed in a matrix on the titanium oxide film 17 as described above, and the alignment film 16 is formed on the pixel electrodes 9a. In the present embodiment, the titanium oxide film 17 and the pixel electrode 9a have the same planar shape. The titanium oxide film 17 can be formed by stacking the pixel electrode 9a and the titanium film. That is, the titanium oxide film (TiO ₂ ) 17 is formed by the reaction between the titanium film and ITO constituting the pixel electrode 9a.

  Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a fourth interlayer insulating film 44 made of BPSG is formed. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is opened.

  In the third relay electrode 402, the lower conductive film 402a made of aluminum is connected to the second relay electrode 6a2. On the other hand, in the present embodiment, the electrolytic corrosion prevention film 402b made of titanium nitride as the upper layer is connected to the pixel electrode 9a made of ITO or the like through the titanium oxide film 17. The third relay electrode 402 has a function of relaying electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through the contact hole 89.

  When the titanium nitride film, which is the electrolytic corrosion prevention film 402b, and ITO are directly connected, the contact resistance is relatively high and good connectivity cannot be obtained. However, in the present embodiment, the titanium oxide film 17 is formed between the electrolytic corrosion prevention film 402b and the pixel electrode 9a. The interface of the titanium nitride film that is the electrolytic corrosion prevention film 402b contains a large amount of impurities such as an oxide film. For this reason, the contact resistance between the electrolytic corrosion prevention film 402b and the titanium oxide film 17 becomes a sufficiently small value due to the oxidation-reduction action. Further, the contact resistance between the titanium oxide film 17 and the ITO constituting the pixel electrode 9a is sufficiently small.

  Thereby, in this embodiment, the resistance between the electrolytic corrosion preventing film 402b and the pixel electrode 9a is reduced as compared with the case where the titanium nitride film which is the electrolytic corrosion preventing film 402b and ITO are directly connected. Can do. As described above, since the electrical connection between the third relay electrode 402 and the pixel electrode 9a can be satisfactorily realized, the voltage application to the pixel electrode 9a or the potential holding characteristic in the pixel electrode 9a is maintained well. It becomes possible.

  In the present embodiment, the titanium oxide film 17 and the pixel electrode 9a are configured in the same planar shape. This titanium oxide film 17 is transparent. For this reason, even when the titanium oxide film 17 is formed on the entire surface of the pixel electrode 9a, the aperture ratio does not decrease.

  Also regarding the three-dimensional layout of each component, the present invention is not limited to the form as in the above embodiment, and various other forms can be considered.

(Manufacturing process)
Next, a method for manufacturing a liquid crystal device which is an electro-optical device according to the present embodiment will be described with reference to FIGS. FIG. 6 is a flowchart showing a method for manufacturing the fifth layer and the sixth layer, and FIG. 7 is a process diagram showing the method for manufacturing the fifth layer and the sixth layer in the order of steps.

  First, a TFT substrate 10 such as a quartz substrate, glass, or silicon substrate is prepared. Here, annealing is preferably performed at a high temperature of about 900 to 1300 ° C. in an inert gas atmosphere such as N (nitrogen), and pretreatment is performed so that distortion generated in the TFT substrate 10 is reduced in a high-temperature process performed later. Keep it.

  Next, a metal alloy film such as metal or metal silicide such as Ti, Cr, W, Ta, or Mo, or a metal alloy film such as metal silicide is formed on the entire surface of the TFT substrate 10 treated in this manner, and the film thickness is preferably about 100 to 500 nm. Is deposited to a thickness of 200 nm. Then, this metal alloy film is patterned by photolithography and etching to form scanning lines 11a having a planar shape of stripes.

  Next, on the scanning line 11a, for example, TEOS (tetra-ethyl ortho-silicate) gas, TEB (tetra-ethyl boat rate) gas, TMOP (tetra-methyl oxy. A silicate glass film such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride film or silicon oxide film using a phosphite gas or the like A base insulating film 12 made of or the like is formed. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.

  Next, the semiconductor layer 1a is formed. The semiconductor layer 1a is formed on the base insulating film 12 by low pressure CVD (for example, using monosilane gas, disilane gas, etc.) at a flow rate of about 400 to 600 cc / min in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. And an amorphous silicon film formed by CVD at a pressure of about 20 to 40 Pa. Next, heat treatment is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the p-Si (polysilicon) film has a thickness of about 50 to 200 nm. The solid phase growth is preferably performed until the thickness becomes about 100 nm. As a method for solid phase growth, annealing using RTA or laser annealing using an excimer laser or the like may be used. At this time, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like depending on whether the pixel switching TFT 30 is an n-channel type or a p-channel type. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.

  Next, the semiconductor layer 1a constituting the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C., to form a lower gate insulating film. By forming the upper-layer gate green film with the above or the like, the insulating film 2 (including the gate insulating film) made of a single-layer or multilayer high-temperature silicon oxide film (HTO film) or silicon nitride film is formed. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 100 nm. It becomes thickness.

  Next, in order to control the threshold voltage Vth of the TFT 30 for pixel switching, a predetermined amount of a dopant such as boron is ion-implanted into the n-channel region or the p-channel region of the semiconductor layer 1a by ion implantation or the like. Dope.

  Next, a groove 12cv that communicates with the scanning line 11a is formed in the base insulating film 12. The groove 12cv is formed by dry etching such as reactive ion etching or reactive ion beam etching.

  Next, a polysilicon film is deposited by low pressure CVD or the like, and phosphorus (P) is further thermally diffused to make this polysilicon film conductive. Instead of this thermal diffusion, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of this polysilicon film is about 100 to 500 nm, preferably about 350 nm. Then, a gate electrode 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching. When the gate electrode 3a is formed, a side wall 3b extending to the gate electrode 3a is also formed at the same time. The sidewall 3b is formed by depositing the polysilicon film described above also on the inside of the groove 12cv. At this time, since the bottom of the groove 12cv is in contact with the scanning line 11a, the side wall 3b and the scanning line 11a are electrically connected. Further, the relay electrode 719 is also formed simultaneously with the patterning of the gate electrode 3a.

Next, a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e are formed for the semiconductor layer 1a. Here, the case where the TFT 30 is an n-channel TFT having an LDD structure will be described. Specifically, first, in order to form the low concentration source region 1b and the low concentration drain region 1c, the gate electrode 3a is used as a mask. Dope of a group V element such as P is doped at a low concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹³ cm ₂ ). As a result, the semiconductor layer 1a under the gate electrode 3a becomes a channel region 1a ′. At this time, the gate electrode 3a serves as a mask, so that the low concentration source region 1b and the low concentration drain region 1c are formed in a self-aligned manner. Next, in order to form the high concentration source region 1d and the high concentration drain region 1e, a resist layer having a planar pattern wider than the gate electrode 3a is formed on the gate electrode 3a. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions at a dose of 1 to 3 × 10 ¹⁵ / cm ₂ ).

  In addition, it is not necessary to dope by dividing into two steps of low concentration and high concentration. For example, a TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, etc. with the gate electrode 3a (gate electrode) as a mask. Good. By doping the impurities, the gate electrode 3a is further reduced in resistance.

  Next, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or an oxide film is formed on the gate electrode 3a by, for example, atmospheric pressure or low pressure CVD using TEOS gas, TEB gas, TMOP gas, or the like. A first interlayer insulating film 41 made of a silicon film is formed. The film thickness of the first interlayer insulating film 41 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41.

  Next, the contact hole 83 and the contact hole 881 are opened by dry etching such as reactive ion etching and reactive ion beam etching for the first interlayer insulating film 41. At this time, the former is formed so as to communicate with the high-concentration drain region 1e of the semiconductor layer 1a, and the latter is formed so as to communicate with the relay electrode 719.

  Next, a metal film such as Pt or a polysilicon film is formed on the first interlayer insulating film 41 to a thickness of about 100 to 500 nm by low pressure CVD or sputtering, and the lower electrode 71 having a predetermined pattern is formed. Constitute. In this case, the metal film is formed so that both the contact hole 83 and the contact hole 881 are filled, and thereby, the high-concentration drain region 1e and the relay electrode 719 and the lower electrode 71 are electrically connected.

  Next, a dielectric film 75 is formed on the lower electrode 71. The dielectric film 75 can be formed by various known techniques generally used for forming a TFT gate insulating film, as in the case of the insulating film 2. The silicon oxide film 75a is formed by the above-described thermal oxidation, CVD method or the like, and then the silicon nitride film 75b is formed by low pressure CVD method or the like. As the dielectric film 75 is made thinner, the storage capacitor 70 becomes larger. Therefore, it is advantageous to form a very thin insulating film with a film thickness of 50 nm or less on the condition that no defects such as film breakage occur after all. It is. Next, a metal film such as a polysilicon film or AL (aluminum) is formed on the dielectric film 75 to a thickness of about 100 to 500 nm by low-pressure CVD or sputtering to constitute the capacitive electrode 300. .

  Next, the lower electrode 71, the dielectric film 75, and the film constituting the capacitor electrode 300 are patterned at a time to form the lower electrode 71, the dielectric film 75, and the capacitor electrode 300, and the storage capacitor 70 is completed. .

  Next, for example, a normal glass or low pressure CVD method using TEOS gas or the like, preferably a plasma CVD method is used to form a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like. A two-layer insulating film 42 is formed. When aluminum is used for the capacitor electrode 300, it is necessary to form a film at a low temperature by plasma CVD. The film thickness of the second interlayer insulating film 42 is about 500 to 1500 nm, for example. Next, in step S12, contact holes 81, 801, and 882 are opened by dry etching such as reactive ion etching and reactive ion beam etching for the second interlayer insulating film. At this time, the contact hole 81 is formed so as to communicate with the high concentration source region 1d of the semiconductor layer 1a, the contact hole 801 is communicated with the capacitor electrode 300, and the contact hole 882 is formed so as to communicate with the relay electrode 719. The

  Next, on the entire surface of the second interlayer insulating film 42, a thickness of about 100 to 500 nm, preferably about 300 nm, is formed by using a low resistance metal such as light-shielding aluminum or a metal silicide as a metal film by sputtering or the like. accumulate. Then, the data line 6a having a predetermined pattern is formed by photolithography and etching. At this time, during the patterning, the shield layer relay layer 6a1 and the second relay electrode 6a2 are also formed at the same time. The shield layer relay layer 6a1 is formed to cover the contact hole 801, and the second relay electrode 6a2 is formed to cover the contact hole 882.

  Next, after a film made of titanium nitride is formed on the entire surface of these upper layers by plasma CVD or the like, a patterning process is performed so that the film remains only on the data line 6a. However, the titanium nitride layer may be formed so as to remain on the shield layer relay layer 6a1 and the second relay electrode 6a2, or may be formed so as to remain on the entire surface of the TFT substrate 10. Also good. Alternatively, the aluminum film may be formed at the same time as the aluminum film and etched in a lump.

  Next, a silicate such as NSG, PSG, BSG, or BPSG is formed so as to cover the data line 6a or the like, for example, by a normal pressure or low pressure CVD method using TEOS gas or the like, preferably by a plasma CVD method capable of forming a low temperature film A third interlayer insulating film 43 made of a glass film, a silicon nitride film, a silicon oxide film, or the like is formed. The film thickness of the third interlayer insulating film 43 is, eg, about 500-3500 nm. Next, as shown in FIG. 1, the third interlayer insulating film 43 is planarized using, for example, CMP.

  Next, contact holes 803 and 804 are formed by dry etching such as reactive ion etching or reactive ion beam etching for the third interlayer insulating film 43. At this time, the contact hole 803 is formed so as to communicate with the shield layer relay layer 6a1, and the contact hole 804 is formed so as to communicate with the second relay electrode 6a2.

  Next, the shield layer 400 and the third relay electrode 402 are formed on the third interlayer insulating film 43 by sputtering or plasma CVD. That is, the conductive films 400a and 402a are formed from a low resistance material such as aluminum on the third interlayer insulating film 43, and then, on the lower layer films 400a and 402a, other pixel electrodes described later such as titanium nitride are formed. A titanium nitride layer 400b and an electrolytic corrosion prevention film 402b are formed of ITO that constitutes 9a and a material that does not cause electrolytic corrosion (step S1 in FIG. 6). Next, in step S2, the lower layer films 400a and 402a and the upper layer films 400b and 402b are both patterned. Step (1) in FIG. 7 shows this state.

  Next, as shown in step (2) of FIG. 7, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or a silicon oxide film is formed by, for example, atmospheric pressure or low pressure CVD using TEOS gas or the like. A fourth interlayer insulating film 44 made of or the like is formed (step S3). The film thickness of the fourth interlayer insulating film 44 is about 500 to 1500 nm, for example.

  Next, as shown in FIG. 1, the fourth interlayer insulating film 44 is planarized using, for example, CMP. Next, as shown in step (3) of FIG. 7, a contact hole 89 is formed by dry etching such as reactive ion etching or reactive ion beam etching for the fourth interlayer insulating film 44 (step S4). At this time, the contact hole 89 is formed so as to communicate with the electrolytic corrosion prevention film 402 b of the third relay electrode 402.

  Next, as shown in step (4) in FIG. 7, a titanium film 17 'is formed on the fourth interlayer insulating film 44 by sputtering or the like (step S5). Next, as shown in step (5) in FIG. 7, a transparent conductive film 9a 'such as an ITO film is deposited to a thickness of about 50 to 200 nm (step S6). As described above, the titanium film 17 ′ is changed to a titanium oxide film by the reaction between the titanium film 17 ′ and the ITO film that is the transparent conductive film 9 a ′. Then, as shown in step (6) in FIG. 7, the titanium film 17 ′ and the conductive film 9a ′ are simultaneously patterned by photolithography and etching to form the titanium oxide film 17 and the pixel electrode 9a (step S7). ). Finally, as shown in step (7) in FIG. 7, after applying a polyimide alignment film coating liquid onto the pixel electrode 9a and the interlayer insulating film 44, the film has a predetermined pretilt angle and a predetermined value. The alignment film 16 is formed by performing a rubbing process in the direction.

  As described above, in this embodiment, since the electrolytic corrosion prevention film 402b, which is a conductive film, and the ITO that constitutes the pixel electrode are connected with the titanium oxide film 17 interposed therebetween, the contact is made. Resistance can be sufficiently reduced. Further, the titanium oxide film 17 is formed by patterning at the same time as the patterning of the pixel electrode 9a which is an ITO film, so that the process of patterning the titanium oxide film 17 alone is unnecessary, and an increase in the manufacturing process can be suppressed. it can.

  FIG. 8 is a cross-sectional view showing a cross-sectional structure of an electro-optical device according to the second embodiment of the invention. In FIG. 8, the same components as those in FIG.

  This embodiment is different from the first embodiment in that a titanium oxide film 17b is employed instead of the titanium oxide film 17. In the first embodiment, the titanium oxide film 17 having the same planar shape as the pixel electrode 9a is employed. In order to reduce the contact resistance between the third relay electrode 402 and the pixel electrode 9a, a titanium oxide film may be provided between the electrolytic corrosion prevention film 402b and the pixel electrode 9a. Therefore, the titanium oxide film 17b of the present embodiment is provided only in the vicinity of the connection portion between the electrolytic corrosion prevention film 402b and the pixel electrode 9a in plan view.

  Other configurations and operations are the same as those in the first embodiment.

  As described above, also in this embodiment, since the electroerosion prevention film 402b which is a conductive film and the ITO constituting the pixel electrode are connected with the titanium oxide film 17b interposed therebetween, the contact resistance is reduced. Can be sufficiently reduced.

  Further, the electro-optical device of the present invention can be similarly applied to an active matrix liquid crystal panel (for example, a liquid crystal display panel including not only a TFT (thin film transistor) but also a TFD (thin film diode)) as a switching element. It can also be applied to a passive matrix liquid crystal display panel. In addition to liquid crystal display panels, various devices such as electroluminescence devices, organic electroluminescence devices, plasma display devices, electrophoretic display devices, and devices using electron emission (Field Emission Display, Surface-Conduction Electron-Emitter Display, etc.) The present invention can be similarly applied to the electro-optical device.

1 is a cross-sectional view illustrating a cross-sectional structure of an electro-optical device according to a first embodiment of the invention. FIG. 3 is a plan view of the liquid crystal device, which is the electro-optical device according to the present embodiment, viewed from the counter substrate side together with the components formed thereon. FIG. 3 is a cross-sectional view of the liquid crystal device after the assembly process in which the element substrate and the counter substrate are bonded to each other and the liquid crystal is sealed is cut along a line HH ′ in FIG. FIG. 6 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels constituting a pixel region of the liquid crystal device. The top view which shows a part of film-forming pattern of the film-forming pattern of each layer about the several adjacent pixel formed on the TFT substrate of this Embodiment. 2 is a flowchart showing a part of the manufacturing method of the liquid crystal device of FIG. FIG. 7 is a process diagram showing a part of the process of the manufacturing method of FIG. FIG. 6 is a cross-sectional view illustrating a cross-sectional structure of an electro-optical device according to a second embodiment of the invention.

Explanation of symbols

    9a ... pixel electrode, 17 ... titanium oxide film, 44 ... fourth interlayer insulating film, 89 ... contact hole, 400 ... shield layer, 402 ... third relay electrode, 402b ... electrolytic corrosion prevention film.

Claims (7)

On the board
A conductive layer;
A transparent electrode;
An interlayer insulating film formed between the conductive layer and the transparent electrode;
A contact hole opened in the interlayer insulating film to electrically connect the conductive layer and the transparent electrode at a contact portion;
At least in the contact portion, a titanium oxide film provided between the conductive layer and the transparent electrode;
An electro-optical device comprising:   The electro-optical device according to claim 1, wherein the titanium oxide film is formed in the same planar shape as the transparent electrode.   The electro-optical device according to claim 1, wherein the titanium oxide film is formed only in the contact hole and the vicinity thereof. On the board
Forming a conductive layer;
Forming an interlayer insulating film on the conductive layer;
Opening a contact hole in the interlayer insulating film to electrically connect the conductive layer and the transparent electrode at a contact portion;
Forming a titanium film in a region including at least a contact portion for electrically connecting the conductive layer and the transparent electrode;
Forming a transparent electrode electrically connected to the conductive layer through the titanium film in a region including at least the titanium film. The step of forming the titanium film and the step of forming the transparent electrode include:
Forming a titanium film over the entire region including the conductive layer;
Forming a transparent electrode in the entire region including on the interlayer insulating film;
The method of manufacturing an electro-optical device according to claim 4, further comprising: patterning the titanium film and the transparent electrode using the same mask.   6. The method of manufacturing an electro-optical device according to claim 4, wherein the titanium film and the transparent electrode are stacked, and the titanium film is changed to a titanium oxide film.   An electronic apparatus comprising the electro-optical device according to claim 1.

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