JPH11337976A - Array substrate for display device and flat display device equipped with that array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an array substrate for a display device equipped with pixel electrodes which can be directly connected to aluminum wirings without a barrier metal by forming a connecting wiring part essentially comprising aluminum to electrically connect a pixel electrode and a switching element. SOLUTION: A pixel electrode 13 containing at least indium, zinc and oxygen is arranged in the pixel region on a gate insulating film 9. The drain electrode 17 of a thin film transistor 6 consisting of a layered film of aluminum and molybdenum functions as a connecting electrode to be electrically connected to the pixel electrode 13. Namely, the pixel electrode 13 of an IZO film is directly connected to the aluminum wiring which forms the connecting electrode and drain electrode 17. Thus, even when zinc is directly connected to aluminum, zinc is hardly reduced by aluminum. Therefore, large increase in the contact resistance is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a display device and a flat panel display device provided with the array substrate, and more particularly to an array substrate applicable to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using a thin film transistor as a switching element includes an array substrate having pixel electrodes and wiring portions such as signal lines and scanning lines for supplying a voltage to the pixel electrodes; It has a counter substrate provided with a counter electrode disposed at a predetermined distance from the array substrate, and a liquid crystal layer including liquid crystal molecules disposed between the array substrate and the counter substrate. The pixel electrodes provided on the array substrate are made of indium oxide (I
n ₂ O ₃₎ containing about 10% by weight of tin oxide (SnO) in an indium-tin-oxide film (InSnO film)
A signal line of a wiring portion formed of a so-called ITO film and electrically connected to the pixel electrode is formed of pure aluminum (Al) or an aluminum alloy.

[0003]

In the array substrate having the above-described structure, when the ITO film of the pixel electrode and the Al wiring or the Al alloy wiring of the signal line are in direct contact,
Sn contained in the TO film, particularly the ITO film, may be reduced by Al to become an insulator. As described above, when the contact portion between the pixel electrode and the signal line becomes an insulator, there arises a problem that the contact resistance increases and the display quality of the screen decreases.

Conventionally, in order to avoid such a phenomenon, molybdenum (Mo), a barrier metal, and the like are provided between the ITO film and the Al wiring so as not to make direct contact with the ITO film.
It is necessary to interpose a metal such as titanium (Ti).

However, in such an array substrate having a structure in which a barrier metal is interposed, the number of manufacturing steps for forming the barrier metal is increased by one, and the manufacturing cost is increased.
In addition, there is a problem that productivity is deteriorated.

Accordingly, the present invention has been made to solve the above problems, and has been made for a display device having a pixel electrode which can directly contact an aluminum wiring and can omit a barrier metal. An object of the present invention is to provide an array substrate and a flat panel display device provided with the array substrate.

[0007]

SUMMARY OF THE INVENTION The present invention has been made based on the above problems. According to the first aspect of the present invention, indium (In) and zinc (Z) are formed on an insulating substrate.
n) a plurality of pixel electrodes formed of a transparent conductive film containing at least oxygen (O); a switching element for supplying a predetermined level of voltage to the pixel electrodes at a predetermined timing; A connection wiring portion mainly formed of aluminum (Al) for electrically connecting the switching element to the switching element.

According to the second aspect of the present invention, a plurality of pixel electrodes formed of a transparent conductive film containing at least indium (In), zinc (Zn), and oxygen (O) on an insulating substrate. And a wiring portion disposed so as to intersect with each other on the insulating substrate, and disposed near the intersection of the wiring portion, and based on a voltage supplied to the wiring portion, with respect to the pixel electrode. A switching element for supplying a voltage of a predetermined level at a predetermined timing; and a connection wiring portion mainly formed of aluminum (Al) for electrically connecting the pixel electrode and the switching element. Is provided.

According to the present invention, a plurality of pixel electrodes formed of a transparent conductive film containing at least indium (In), zinc (Zn) and oxygen (O) on an insulating substrate. A switching element for supplying a predetermined level of voltage to the pixel electrode at a predetermined timing, and a connection wiring portion formed of aluminum (Al) for electrically connecting the pixel electrode and the switching element; An array substrate provided with, and a counter substrate provided with a counter electrode disposed to face the array substrate, and sandwiched between the array substrate and the counter substrate, between the array substrate and the counter substrate And a light modulation layer for modulating light passing therethrough.

According to the array substrate for a display device of the present invention and the flat display device provided with the array substrate, the pixel electrode is made of a transparent material containing at least indium (In), zinc (Zn), and oxygen (O). Conductive film, ie InZ
nO film (indium-zinc-oxide), so-called I
The switching element is formed of a ZO film, and is directly in contact with the switching element by a connection wiring portion mainly formed of aluminum (Al). Zinc (Zn) contained in the IZO film has the same high ionization potential as Al and has the property of not being easily reduced to aluminum.

For this reason, even if Zn contacts Al directly, it is hard to be reduced to Al and hardly to become an insulator. Therefore, the contact resistance is not significantly increased, and the display quality of the display screen in the flat display device is not adversely affected.

The contact resistance of the IZO film to Al can be as high as that obtained when a conventional barrier metal is used.

Therefore, it is not necessary to interpose a barrier metal between the connection wiring portion and the pixel electrode, thereby preventing an increase in the number of manufacturing steps and suppressing an increase in manufacturing cost.

Therefore, it is possible to provide an array substrate for a display device having a pixel electrode capable of directly contacting an aluminum wiring and eliminating a barrier metal, and a flat display device having the array substrate. .

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an array substrate for a display device and a flat panel display device provided with the array substrate according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is an exploded perspective view schematically showing the structure of a flat display device provided with an array substrate for a display device according to the present invention.

As shown in FIG. 1, the liquid crystal display device as a flat display device has a liquid crystal panel 2. A drive circuit board 41 electrically connected to the liquid crystal panel 2 is disposed on a side portion or a rear surface portion of the liquid crystal panel 2.
On the back side of the liquid crystal panel 2, a backlight unit 42 functioning as a surface light source is arranged.

The liquid crystal panel 2 and the backlight unit 42 are held by frames 43-1 and 43-2 including an opening for defining a display surface, and are screwed to form a liquid crystal display device. I have.

FIG. 2 is a sectional view schematically showing a structure of a liquid crystal panel applied to the liquid crystal display device shown in FIG.

As shown in FIG. 2, the liquid crystal panel 2 includes an array substrate 1 and an opposing substrate 4 disposed opposite to the array substrate.
And a liquid crystal layer 5 disposed between the array substrate 1 and the counter substrate 4 and functioning as light modulation including liquid crystal molecules 5A. The array substrate 1 includes a thin film transistor 6 (19) as a switching element, a pixel electrode 13 (29), and a wiring portion including a scanning line and a signal line, each of which is disposed on an insulating substrate 7 (20). I have. Counter substrate 4
Are thin film transistors 6 (1) on an insulating substrate 36.
9) and a light-shielding film 3 that shields a position facing the wiring portion
7. A color filter 38 colored red, green, and blue for each pixel disposed at a position facing the pixel electrode 13 (29), and a counter electrode 3 formed on the entire surface of the counter substrate 4. ing.

On the outer surfaces of the insulating substrates 7 (20) and 36 constituting the array substrate 1 and the counter substrate 4, a polarizing plate 40 having a polarizing surface in a predetermined direction is disposed, and the inner surfaces facing each other. Is provided with an alignment film 39 for aligning the liquid crystal molecules 5A included in the sandwiched liquid crystal layer 5 in a predetermined direction.

In such a liquid crystal panel 2, the orientation direction of the liquid crystal molecules 5A of the liquid crystal layer 5 is controlled by the electric field formed between the pixel electrode 13 (29) and the counter electrode 3.
Light passing through the liquid crystal layer 5 between the array substrate 1 and the counter substrate 4 is modulated. Thus, the amount of light transmitted through the counter substrate 4 is controlled, and an image is displayed.

FIG. 3 is a sectional view schematically showing a structure of a thin film transistor according to a first embodiment applied to the array substrate of the present invention. FIG. 4 is a plan view schematically showing the structure of the thin film transistor according to the first embodiment applied to the array substrate of the present invention.

As shown in FIGS. 3 and 4, the insulating substrate 7
In the upper row direction, a scanning line 8 formed of a molybdenum-tungsten alloy thin film, that is, a Mo-W alloy thin film extends, and a part of the scanning line 8 has a gate voltage for controlling on / off of the thin film transistor 6. It functions as a supplied gate electrode. In the column direction of the insulating substrate 7, a signal line 16 is formed of a laminated film of aluminum (Al) and molybdenum (Mo) and intersects with the scanning line 8 via the gate insulating film 9. Extended,
Part of the signal line 16 functions as the source electrode 16 of the thin film transistor 6.

The scanning line 8 and the gate electrode are made of AlN
It may be formed of an aluminum alloy such as d, AlY, AlNiNd, and AlNiY, a laminated film of Al and Mo, pure Al, and the like.

In a pixel region on the gate insulating film 9, a transparent conductive film containing at least indium (In), zinc (Zn) and oxygen (O), for example, an InZnO film obtained by adding ZnO to In ₂ O _3. That is, the pixel electrode 13 formed of the IZO film is arranged. The drain electrode 17 of the thin film transistor 6 formed of a stacked film of Al and Mo functions as a connection electrode part electrically connected to the pixel electrode 13. That is, the pixel electrode 13 formed by the IZO film is directly contacted and electrically connected to the drain electrode 17 and the Al wiring forming the connection electrode portion.

That is, the gate electrode 8 is connected via the scanning line 8.
When the thin film transistor 6 is turned on, the drive voltage supplied to the signal line 16 is supplied from the source electrode 16 to the pixel electrode 13 via the drain electrode 17. As a result, a predetermined level of driving voltage is supplied to the pixel electrode 13 to form a potential difference between the pixel electrode 13 and the counter electrode, thereby driving the liquid crystal molecules included in the liquid crystal layer.

Next, a method of manufacturing the array substrate shown in FIG. 3 will be described. The thin film transistor 6 provided on the array substrate according to the first embodiment uses a hydrogenated amorphous silicon film as a semiconductor layer.

FIGS. 5A to 5F are diagrams schematically showing a manufacturing process of the array substrate according to the first embodiment.

First, as shown in FIG. 5A, a molybdenum-tungsten (Mo-W) film having a thickness of 3000 angstroms is formed on the entire surface of a glass substrate 7 as an insulating substrate washed with a surfactant or the like by a sputtering method. ) An alloy thin film is formed. Then, the Mo-W alloy thin film is patterned into a predetermined shape to form a gate electrode 8 integrated with the scanning line. In this patterning, chemical
The Mo-W alloy thin film is etched by dry etching, ie, CDE, into a taper shape having a taper angle of about 30 ° so that the coverage of the gate insulating film 9 coated on the gate electrode 8 in the subsequent manufacturing steps is improved. I do.

Subsequently, as shown in FIG. 5B, plasma CVD is performed on the entire surface of the glass substrate 7 and the gate electrode 8.
A silicon oxide film (SiOx) is formed to a thickness of 3000 angstroms by a method, and a gate insulating film 9 is formed. Further, the same CV as that for forming the gate insulating film 9 is used.
A hydrogenated amorphous silicon (a-Si: H) film 11 and a silicon nitride (S
iNx) film 10 is continuously formed. That is, a hydrogenated amorphous silicon (a-Si: H) film 11 having a thickness of 500 Å is formed on the gate insulating film 9, and a film thickness of 2000 Å is formed on the hydrogenated amorphous silicon film 11. To form a silicon nitride (SiNx) film 10.

Subsequently, as shown in FIG. 5C, the silicon nitride film 10 is patterned by backside exposure using the gate electrode 8 as a mask to form a channel protection film 10.

Subsequently, as shown in FIG. 5D, n + doped with a thickness of 500 Å is formed on the entire surface.
-Type hydrogenated amorphous silicon (n + a-Si: H) film 12 is deposited, and hydrogenated amorphous silicon film 11 and n
The + type hydrogenated amorphous silicon film 12 is patterned into an island shape.

Subsequently, as shown in FIG.
InZn prepared by adding 10% by weight of ZnO to ₂ O ₃
The pixel electrode 13 is formed by depositing and patterning the IZO film 13 with a thickness of 400 angstroms using a sputtering apparatus equipped with an O (indium-zinc-oxide) target. Although the content of ZnO in the target is preferably reduced as the specific resistance decreases,
If the amount is too small, the crystallinity of the obtained film is promoted, and the film cannot be etched with a weak acid-based etchant such as oxalic acid. Therefore, the appropriate addition amount is 5 to 20% by weight.

Subsequently, as shown in FIG. 5F, an Al film 14 is formed on the entire surface to a thickness of 3500 Å, and Mo is continuously formed to a thickness of 500 Å.
By forming the film 15, a laminated film of Al and Mo is formed. Then, by patterning this laminated film, the source electrode 16 integrated with the signal line and the pixel electrode 1 are formed.
3 is formed.

Further, the source electrode 16 and the drain electrode 1
7 is used as a mask to remove the n + -type hydrogenated amorphous silicon film 12 on the channel protective film 10.

Then, a protective film 18 of the thin film transistor 6 is formed by forming a silicon nitride film 18 with a thickness of 3500 Å on the entire surface of the substrate by a plasma CVD apparatus. By patterning the silicon nitride film 18, the silicon nitride film 18 is formed only on the pixel electrode 13.
Is removed, and the array substrate 1 including the thin film transistors 6 as shown in FIGS. 3 and 4 is completed.

According to the array substrate according to the first embodiment formed by the above-described manufacturing process, the pixel electrode 13 is formed of an InZnO film, a so-called IZO film, and a hydrogenated amorphous silicon film as a switching element. Is directly contacted with a thin film transistor 6 having a semiconductor film by a connection wiring portion formed of Al (aluminum). Zn (zinc) contained in the IZO film has the same high ionization potential as Al and has the property of not being easily reduced to Al.

For this reason, even if Zn contacts Al directly, it is hard to be reduced to Al and it is hard to become an insulator. Therefore, a significant increase in contact resistance does not occur. Therefore, it is not necessary to interpose a barrier metal between the connection wiring portion and the pixel electrode, thereby preventing an increase in the number of manufacturing steps and suppressing an increase in manufacturing cost.

Further, according to the liquid crystal display device as a flat display device provided with the array substrate, an increase in contact resistance between the pixel electrode and the connection wiring portion can be suppressed, so that the display quality of the display screen is adversely affected. Can be prevented.

Next, the structure of a thin film transistor according to a second embodiment applied to the array substrate of the present invention will be described.

FIG. 6 is a sectional view schematically showing a structure of a thin film transistor according to a second embodiment applied to the array substrate of the present invention. FIG. 7 is a plan view schematically showing a structure of a thin film transistor according to a second embodiment applied to the array substrate of the present invention. In the second embodiment, a thin film transistor having a top gate structure is applied.

As shown in FIGS. 6 and 7, the insulating substrate 2
A scanning line 25 formed of a Mo—W alloy thin film extends in the row direction above the zero, and a part of the scanning line 25 is a gate electrode to which a gate voltage for controlling on / off of the thin film transistor 19 is supplied. Functions as 25. In the column direction of the insulating substrate 20, a signal line 33 is formed of a laminated film of Al and Mo, and extends so as to intersect the scanning line 25 via an interlayer insulating film 28. 33 is a part of the source electrode 3 of the thin film transistor 19.
Function as 3.

In the pixel region on the interlayer insulating film 28, IZO
A pixel electrode 29 formed of a film is arranged.
The drain electrode 34 of the thin film transistor 19 formed of a laminated film of Al and Mo functions as a connection electrode part electrically connected to the pixel electrode 29. That is, I
The pixel electrode 29 formed of the ZO film is directly contacted with and electrically connected to the drain electrode 34 and the Al wiring forming the connection electrode portion.

That is, when a gate voltage is supplied to the gate electrode 25 via the scanning line 25 and the thin film transistor 19 is turned on, the driving voltage supplied to the signal line 33 changes the voltage from the source electrode 33 to the drain electrode 34. Is supplied to the pixel electrode 29 via As a result, a predetermined level of driving voltage is supplied to the pixel electrode 29 to form a potential difference between the pixel electrode 29 and the counter electrode, thereby driving the liquid crystal molecules included in the liquid crystal layer.

Next, a method of manufacturing the array substrate shown in FIG. 6 will be described. The thin film transistor 6 provided on the array substrate according to the second embodiment has a top gate structure using a polysilicon film as a semiconductor layer.

FIGS. 8A to 8G are diagrams schematically showing a process of manufacturing an array substrate according to the second embodiment.

First, as shown in FIG. 8A, a glass substrate 20 as an insulating substrate washed with a surfactant or the like is used.
A silicon nitride (SiNx) film 21 was formed on the entire surface by plasma CVD at a substrate temperature of 300 ° C. without opening to the atmosphere.
A silicon oxide (SiOx) film 22 and a hydrogenated amorphous silicon (a-Si: H) film 23 are successively formed. That is, after a silicon nitride film 21 having a thickness of 500 Å is formed on the entire surface of the glass substrate 20, a silicon oxide film 22 having a thickness of 1000 Å is formed on the entire surface of the silicon nitride film 21. A hydrogenated amorphous silicon film 23 having a thickness of 500 Å is formed on the entire surface of the silicon oxide film 22.

Then, the hydrogenated amorphous silicon film 2
No. 3 contains a large amount of hydrogen, so
After performing a dehydrogenation process by a high-temperature process for a long time, it is converted into polysilicon by an excimer laser annealing apparatus. That is, the excimer laser has an energy of about 230 mJ / cm.
By emitting a laser beam under the conditions of ² and irradiating the emitted beam to the hydrogenated amorphous silicon film 23, a laser beam of about 0.2 to O.D. Polysilicon film 23 having a particle size of 3 μm
Is obtained. The interface mobility of the polysilicon film 23 is:
It is about 80 cm ² / V.

Subsequently, as shown in FIG. 8B, the polysilicon film 23 is patterned into an island shape by CDE.

Subsequently, as shown in FIG. 8C, a silicon oxide (Si0x) film 24 is formed on the entire surface of the substrate to a thickness of 1 000 angstrom to form a gate insulating film 24. On the insulating film 24, a Mo-W alloy film serving as a gate electrode integrated with a scan line is formed to a thickness of 2500 angstroms by a sputtering method. afterwards,
The Mo-W alloy film is linearly patterned by CDE to form a gate electrode 25 integrated with the scanning line.

[0052] Subsequently, as shown in FIG. 8 (d), a resist R1 patterned, then, by an ion doping apparatus in which the PH ₃ as an ion source, 50K and ^{P +} ions
3 × 10 ¹³ / cm ² doping with energy of eV,
The polysilicon film 23 is made n-type, and an n-type polysilicon film 26 is formed on a part of the polysilicon film 23. And
The resist R1 is removed.

Subsequently, as shown in FIG. 8E, the resist R2 is patterned, and P.sup. ⁺ Ions are applied with the same ion doping apparatus at an energy of 50 KeV to 1 × 10 ^15.
The polysilicon film 23 is converted into n + by doping the same / cm ² , and an n + type polysilicon film 27 is formed on a part of the polysilicon film 23. Then, the resist R2 is removed.

Thereafter, the bonding of the n + polysilicon film 27 broken by the ion doping is recovered by annealing at 500 ° C. for one hour.

Subsequently, as shown in FIG. 8F, silicon oxide (SiO 2)
x) The interlayer insulating film 28 is formed by forming the film 28 to a thickness of 5000 Å. After that, using a sputtering apparatus, a film thickness of 1000 Å
A ZO film is formed and patterned by wet etching to form a pixel electrode 29.

Subsequently, as shown in FIG. 8G, the resist is patterned and the silicon oxide film of the interlayer insulating film 28 and the gate insulating film 24 is wet-etched to form a contact hole 30. Then, the Al film 31 and the Mo film 32 are continuously exposed to 45 Angstrom and 50
By forming a film to a thickness of 0 Å and patterning, a source electrode 33 integrated with the signal line and a drain electrode 34 contacting the pixel electrode 29 are formed.
The source electrode 33 and the drain electrode 34 are in contact with the n + type polysilicon film 27 via the contact holes 30, respectively.

Then, a silicon nitride film 35 is formed to a thickness of 5000 angstroms on the entire surface of the substrate by a plasma CVD apparatus to form a protective film 35 for the thin film transistor 19. Then, the silicon nitride film 35 is patterned to remove the silicon nitride film only above the pixel electrode 29. Thereafter, in order to stabilize the characteristics of the transistor, 3
Anneal for 1 hour in an atmosphere of 50 ° C.

Through the above manufacturing steps, the array substrate 1 having the thin film transistors 19 is completed.

According to the above-described array substrate according to the second embodiment and the liquid crystal display device provided with this array substrate,
The same effect as in the first embodiment can be obtained.

A liquid crystal display device as a flat display device as shown in FIG. 2 is completed using the array substrates according to the first and second embodiments described above.

That is, polyimide is applied to the surface of the array substrate 1, dried, and then subjected to a rubbing treatment to form an alignment film 39.

On the other hand, the opposing substrate 4 is
6, a light shielding film 37 is formed by patterning chromium (Cr) into a matrix shape, for example. And
Red, green and blue color filters 38 made of resin are formed in the gaps between the light shielding films 37.

Then, a transparent conductive film such as ITO is disposed on the light shielding film 37 and the color filter 38 to form the counter electrode 3. Then, after applying and drying polyimide on the uppermost layer of the counter electrode 3, a rubbing process is performed to form an alignment film 39.

Then, the surfaces of the array substrate 1 and the counter substrate 4 on which the alignment films 39 are formed are arranged so as to face each other, and the two substrates are removed by a resin sealing material (not shown) except for the liquid crystal sealing port. Bonding to form empty cells.
At this time, the gap between the two substrates is kept substantially constant by interposing a spacer (not shown) between the two substrates.

Then, the empty cell is placed in a vacuum, and the liquid crystal material containing liquid crystal molecules is injected into the empty cell by gradually returning the pressure to the atmospheric pressure with the sealing port immersed in the liquid crystal. Is formed, and the sealing port is sealed. Further, the polarizing plates 40 are attached to both outer surfaces of the cell to complete the liquid crystal panel 2.

Further, as shown in FIG. 1, a circuit board 41 for controlling the driving of the liquid crystal display device is electrically connected to the liquid crystal panel 2 and arranged on a side portion or a rear surface portion of the liquid crystal panel 2.

Then, the liquid crystal panel 2 is held by the frame 43-1 including the opening for defining the display surface of the liquid crystal panel 2 and the frame 43-2 for holding the backlight 42 as a surface light source, thereby completing the liquid crystal display device. Let it.

Next, the contact resistance between the IZO film as a pixel electrode and the Al wiring as a connection wiring directly contacting the pixel electrode on the array substrate of the present invention was measured. FIG. 9 shows the measurement results.

As shown in FIG. 9, Al distribution is directly provided on the IZO film.
When the wires are contacted, the contact resistance is 6.5.
× 10⁰Ω, and molybdenum (M
o) is interposed between the IZO film and the Al wiring.
Contact resistance, 3.2 × 10 ⁰It is almost equivalent to Ω.

As a comparative example, when an Al wiring is directly contacted with a pixel electrode formed of an ITO film, the contact resistance is 1.3 × 10 ⁵ Ω, which is 10 ⁵ times that of the case where an IZO film is used. became. However, the contact resistance when molybdenum (Mo) is interposed between the ITO film and the Al wiring as a barrier metal is 5.7 × 1.
It became ⁰ 0 Ω.

In this measurement, the contact area between the pixel electrode and the connection wiring portion is 40 × 40 μm.

As described above, in the ITO film, the contact resistance is increased by about 10 ⁵ times by directly contacting the Al wiring. However, when the IZO film is directly contacted with the Al wiring, the contact resistance is reduced by the barrier metal. There was a slight upward trend compared with the case of using, but the digit did not change.

As described above, when a liquid crystal display device was prototyped according to the embodiment of the present invention, the manufacturing yield was reduced.
The display quality was at the same level as the combination of ITO and barrier metal. Therefore, in this liquid crystal display device, it is possible to provide the same performance as that of the conventional liquid crystal display device without disposing the barrier metal.

Therefore, the barrier metal can be omitted, and the manufacturing process can be simplified.

That is, instead of the conventional ITO film, IZ
By using the O film as the pixel electrode, direct contact with the Al wiring becomes possible, so that the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0076]

As described above, according to the present invention, an array substrate for a display device having a pixel electrode capable of directly contacting an aluminum wiring and omitting a barrier metal, and this array substrate It is possible to provide a flat panel display device provided with:

[Brief description of the drawings]

FIG. 1 is an exploded perspective view schematically showing a configuration of a flat display device, that is, a liquid crystal display device, to which an array substrate for a display device of the present invention is applied.

FIG. 2 is a sectional view schematically showing a structure of a liquid crystal panel provided in the liquid crystal display panel shown in FIG.

FIG. 3 is a sectional view schematically showing a structure of a thin film transistor applied to the display device array substrate according to the first embodiment of the present invention.

FIG. 4 is a plan view schematically showing a structure of a thin film transistor applied to the display device array substrate shown in FIG. 3;

FIGS. 5A to 5F are diagrams showing a process of manufacturing an array substrate for a display device according to the first embodiment.

FIG. 6 is a sectional view schematically showing a structure of a thin film transistor applied to a display device array substrate according to a second embodiment of the present invention.

FIG. 7 is a plan view schematically showing a structure of a thin film transistor applied to the display device array substrate shown in FIG. 6;

FIGS. 8A to 8G are diagrams illustrating a process of manufacturing an array substrate for a display device according to a second embodiment.

FIG. 9 shows a measurement result obtained by measuring contact resistance between an IZO film as a pixel electrode and an Al wiring as a connection wiring portion directly contacting the pixel electrode in the display device array substrate of the present invention. FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Array substrate 2 ... Liquid crystal panel 3 ... Counter electrode 4 ... Counter substrate 5 ... Liquid crystal layer 6 (19) ... Thin film transistor 7 (20) ... Glass substrate 8 (25) ... Gate electrode 9 (24) ... Gate insulating film 10 ... Channel protective film 11 (23) hydrogenated amorphous silicon 12 n-type hydrogenated amorphous silicon 13 (29) pixel electrode 14 (31) Al film 15 (32) Mo film 16 (33) source electrode 17 (34) drain electrode 18 (35) thin film transistor protective film 21 silicon nitride film 22 silicon oxide film 26 n-type polysilicon film 27 n-type polysilicon film 28 interlayer insulating film 30 contact hole 36 Glass substrate 37 Light-shielding film 38 Color filter 39 Alignment film 40 Polarizing plate 41 Circuit board 42 Backlight

Claims (6)

[Claims] A plurality of pixel electrodes formed of a transparent conductive film containing at least indium (In), zinc (Zn), and oxygen (O) on an insulating substrate; A switching element for supplying a voltage of a predetermined level at the timing described above, and a connection wiring section mainly formed of aluminum (A) for electrically connecting the pixel electrode and the switching element. Array substrate for display devices. 2. A plurality of pixel electrodes formed of a transparent conductive film containing at least indium (In), zinc (Zn), and oxygen (O) on an insulating substrate, and crossing each other on the insulating substrate. And a wiring portion arranged near the intersection of the wiring portion, and based on a voltage supplied to the wiring portion, applying a voltage of a predetermined level to the pixel electrode at a predetermined timing based on a voltage supplied to the wiring portion. An array substrate for a display device, comprising: a switching element to be supplied; and a connection wiring portion mainly formed of aluminum (Al) for electrically connecting the pixel electrode and the switching element. 3. The array substrate for a display device according to claim 1, wherein the switching element is a thin film transistor using a hydrogenated amorphous silicon film as a semiconductor film. 4. The array substrate according to claim 1, wherein the switching element is a thin film transistor using a polysilicon film as a semiconductor film. 5. The method according to claim 1, wherein the pixel electrode is formed of indium oxide (In ₂
The array substrate for a display device according to any one of claims 1 to 4, wherein the transparent substrate is formed of a transparent conductive film containing 5 to 20% by weight of zinc oxide (ZnO ₎ in O3 ₎ . 6. A plurality of pixel electrodes formed of a transparent conductive film containing at least indium (In), zinc (Zn), and oxygen (O) on an insulating substrate; An array substrate comprising: a switching element for supplying a voltage of a predetermined level at the timing of: and a connection wiring portion mainly formed of aluminum (Al) for electrically connecting the pixel electrode and the switching element; An opposing substrate having an opposing electrode disposed opposite to the array substrate; light interposed between the array substrate and the opposing substrate and modulating light passing between the array substrate and the opposing substrate. A flat panel display, comprising: a modulation layer.