JP2000150962A - Light emitting diode - Google Patents

Light emitting diode

Info

Publication number
JP2000150962A
JP2000150962A JP31936298A JP31936298A JP2000150962A JP 2000150962 A JP2000150962 A JP 2000150962A JP 31936298 A JP31936298 A JP 31936298A JP 31936298 A JP31936298 A JP 31936298A JP 2000150962 A JP2000150962 A JP 2000150962A
Authority
JP
Japan
Prior art keywords
light emitting
emitting diode
voltage
chip
led chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31936298A
Other languages
Japanese (ja)
Inventor
Masafumi Asada
雅文 浅田
Yoshinori Shimizu
義則 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Chemical Industries Ltd
Original Assignee
Nichia Chemical Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichia Chemical Industries Ltd filed Critical Nichia Chemical Industries Ltd
Priority to JP31936298A priority Critical patent/JP2000150962A/en
Publication of JP2000150962A publication Critical patent/JP2000150962A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the luminous efficiency of a light emitting element using a III nitride semiconductor in its light emitting layer without giving any damage to the element by electrically connecting a Zener diode in antiparallel with the element. SOLUTION: An LED(light emitting diode) chip 31 using the III nitride semiconductor in its light emitting layer is bonded to the housing section of an Au-plated stem 33 with Ag paste 36, and an n-substrate Zener diode chip 32 is bonded to the flat section on the peripheral edge of the housing section of the steam 33 with the same Ag paste 36. Then such a light emitting diode that the Zener diode chip 32 is connected in antiparallel with the LED chip 31 is formed by respectively wire-bonding an inner lead 33a and a mount lead 33b to the n and p-side lead-out electrodes of the LED chip 31 by using gold wires 35.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、紫外域から可視光
まで発光可能な窒化物半導体発光素子を用いた発光ダイ
オードに係わり、特に人間がショックを感じる電圧以下
に対し、発光素子を損傷することなく発光効率の優れた
発光ダイオードを提供するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode using a nitride semiconductor light emitting device capable of emitting light from an ultraviolet region to a visible light, and particularly to a light emitting device which is damaged under a voltage below which a human is shocked. It is intended to provide a light emitting diode having excellent luminous efficiency.

【0002】[0002]

【従来技術】発光ダイオードは小型で効率が良く色鮮や
かな発光をする。また、半導体素子であるため球切れな
どの心配がない。さらに、初期駆動特性が優れ、振動や
点滅に強いという特徴を有する。特に、近紫外から赤色
まで高輝度に発光可能な発光素子として窒化物半導体
(InxAlyGa1-x-yN、0≦x≦1、0≦y≦1)
を利用した発光ダイオードが実用化されたことから種々
の分野に急速に利用され始めている。
2. Description of the Related Art Light-emitting diodes emit light of a small size, efficiently and colorfully. In addition, since it is a semiconductor element, there is no fear of breaking the ball. Furthermore, it has a feature that it has excellent initial drive characteristics and is resistant to vibration and blinking. In particular, a nitride semiconductor (In x Al y Ga 1-xy N, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1) is used as a light emitting element capable of emitting light with high luminance from near ultraviolet to red.
Since light-emitting diodes using GaN have been put to practical use, they have begun to be rapidly used in various fields.

【0003】しかし、窒化物半導体は結晶性の優れた半
導体を形成させることが難しく、現在のところサファイ
ア基板やSiC基板上にバッファ層を介して成膜させて
ある。このような窒化物半導体を用いた発光素子は結晶
性が悪いが故に耐電圧が低い。特に、発光層の組成にA
l或いはInを含み紫外域や可視光の長波長側に発光ピ
ークを持った窒化物半導体を形成させるほど結晶性が低
下する傾向にある。
However, it is difficult for a nitride semiconductor to form a semiconductor having excellent crystallinity. At present, a nitride semiconductor is formed on a sapphire substrate or a SiC substrate via a buffer layer. A light-emitting element using such a nitride semiconductor has low withstand voltage because of poor crystallinity. In particular, the composition of the light-emitting layer
The crystallinity tends to decrease as a nitride semiconductor containing l or In and having an emission peak in the ultraviolet region or the long wavelength side of visible light is formed.

【0004】また、発光効率をより向上させるため発光
層が単一量子井戸構造や多重量子井戸構造とされる極め
て薄膜で形成させることが行われている。そのため、小
型、高効率、小電流で高出力を有する優れた特性を持つ
窒化物半導体を用いた発光素子は、少しの静電気電圧で
破壊され易いという問題がある。例えば、通常の発光層
がAlGaInPなどからなる赤色、赤外光が発光可能
な発光ダイオードが約2KVの耐電圧があるのに対し、
発光層がInGaNからなる青色、緑色、黄色などが発
光可能な発光ダイオードの耐電圧は約0.5V以下にし
かすぎない。特に、Alが含有された紫外発光可能な窒
化物半導体発光素子に至っては約0.2KV以下であ
る。(なお、発光素子までの抵抗が理想的な0オーム、
スイッチングにより200pFのコンデンサから発光素
子に電流を流して耐電圧試験をしてある。)
Further, in order to further improve the luminous efficiency, the light emitting layer is formed of an extremely thin film having a single quantum well structure or a multiple quantum well structure. Therefore, there is a problem that a light-emitting element using a nitride semiconductor having excellent characteristics having a small size, high efficiency, high output at a small current and high output is easily broken by a small electrostatic voltage. For example, a light emitting diode whose normal light emitting layer is made of AlGaInP and can emit red and infrared light has a withstand voltage of about 2 KV,
The withstand voltage of a light-emitting diode whose light-emitting layer is made of InGaN and emits blue light, green light, yellow light, or the like is only about 0.5 V or less. In particular, it is about 0.2 KV or less for a nitride semiconductor light emitting device containing Al that can emit ultraviolet light. (The resistance to the light emitting element is ideally 0 ohm,
A withstand voltage test is performed by passing a current from a 200 pF capacitor to the light emitting element by switching. )

【0005】このような3族窒化物半導体からなる発光
ダイオードは、発光素子の構造上、電気的なショックに
より素子の破壊が起こりやすい。特に、乾燥した雰囲
気、帯電し易い環境で発光ダイオード及び発光ダイオー
ド実装部品を取り扱うと、静電気により発光ダイオード
が破壊される場合がある。
A light emitting diode made of such a group III nitride semiconductor is liable to break down due to an electric shock due to the structure of the light emitting element. In particular, when the light emitting diode and the light emitting diode mounted component are handled in a dry atmosphere or an environment where the light emitting diode is easily charged, the light emitting diode may be broken by static electricity.

【0006】また、近年様々な分野に発光ダイオードが
利用され始めているが、発光ダイオードを自動車用部品
に組み込んだ場合も大きな問題となる。具体的には、車
載用の発光ダイオードには始動時にサージ電圧が加わる
場合があり、発光ダイオードを破壊する危険性もある。
In recent years, light-emitting diodes have begun to be used in various fields. However, when the light-emitting diodes are incorporated into automobile parts, a serious problem arises. Specifically, a surge voltage may be applied to a light emitting diode mounted on a vehicle at the time of starting, and there is a risk that the light emitting diode may be destroyed.

【0007】静電気に因る破壊を防ぐために、発光ダイ
オード輸送時は導電性スポンジ、帯電防止剤入りケース
などを使用している。また、発光ダイオードの実装作業
場では湿度管理、人体アース、除電装置の設置などの対
策を取ることができる。しかし、これらの静電気対策は
帯電電圧を下げることは可能であるが、静電気による破
壊を完全に無くすことは難しい。
In order to prevent destruction due to static electricity, a conductive sponge, a case containing an antistatic agent or the like is used when transporting the light emitting diode. Further, measures such as humidity control, human body grounding, and installation of a static eliminator can be taken at the workplace where the light emitting diodes are mounted. However, these countermeasures against static electricity can lower the charging voltage, but it is difficult to completely eliminate destruction due to static electricity.

【0008】また、LED装置側で取られている静電気
及びサージ電圧対策としては、過電流防止用の抵抗を直
列に接続しLED装置単体で定電圧駆動を可能にした抵
抗内蔵型LED装置がある。この抵抗によりサージのエ
ネルギーを吸収、緩和することは可能である。ただし、
LED装置に対して、内蔵した抵抗が消費する電力を投
入する必要があるなどLEDチップが持つ特性を大きく
損なう問題がある。
As a countermeasure against static electricity and surge voltage taken on the LED device side, there is a resistor built-in type LED device in which a resistor for overcurrent prevention is connected in series to enable a constant voltage drive of the LED device alone. . It is possible to absorb and mitigate the energy of surge by this resistance. However,
There is a problem that the characteristics of the LED chip are greatly impaired, for example, it is necessary to supply the power consumed by the built-in resistor to the LED device.

【0009】特に大きな問題となるのは、3族窒化物半
導体からなる発光ダイオードの耐電圧が他の発光ダイオ
ードと比較して極めて低く、また、人体がショックを感
ずる限界が約2KV程度であるため、これ以下の電気が
流れた場合、窒化物半導体素子が破壊されるかどうか
が、分かり難いためである。
A particularly serious problem is that the withstand voltage of a light-emitting diode made of a group III nitride semiconductor is extremely low as compared with other light-emitting diodes, and the limit at which a human body feels a shock is about 2 KV. This is because it is difficult to determine whether the nitride semiconductor device is destroyed when electricity of less than this value flows.

【0010】[0010]

【発明が解決しようとする課題】現在、静電気の発生を
完全に無くすこと、及び電源や測定器のON/OFFに
よるサージ発生を完全に無くすことは困難である。よっ
て、発光ダイオード単体での静電気及びサージ保護対策
が必要であるが、従来の抵抗内蔵型LED装置では、L
EDチップの持つ特性を大きく損なってしまう。従っ
て、本願発明は、LED固有の特性を損なうこと無く、
且つ静電気やサージ電圧に対し、発光素子を損傷するこ
となく発光効率の優れた発光ダイオードを提供すること
を目的とする。
At present, it is difficult to completely eliminate the generation of static electricity and completely eliminate the occurrence of surges due to ON / OFF of a power supply and a measuring instrument. Therefore, it is necessary to protect against static electricity and surge by using the light emitting diode alone.
The characteristics of the ED chip are greatly impaired. Therefore, the present invention does not impair the inherent characteristics of the LED,
It is another object of the present invention to provide a light emitting diode having excellent light emitting efficiency without damaging the light emitting element against static electricity and surge voltage.

【0011】[0011]

【課題を解決するための手段】本発明は、発光層に3族
窒化物半導体を用いた発光素子を有する発光ダイオード
であって、前記発光素子に対してツェナーダイオードが
逆並列に電気接続されている。
The present invention relates to a light emitting diode having a light emitting element using a group III nitride semiconductor for a light emitting layer, wherein a zener diode is electrically connected in antiparallel to the light emitting element. I have.

【0012】本発明の請求項2に記載の発光ダイオード
は、前記発光素子がサファイア基板上に形成されたダブ
ルへテロ構造である。
A light emitting diode according to a second aspect of the present invention has a double hetero structure in which the light emitting element is formed on a sapphire substrate.

【0013】[0013]

【発明の実施の形態】本願発明者は種々の実験の結果、
適切なツェナー電圧Vzを持つツェナーダイオードを窒
化物半導体発光素子に対して逆並列に接続することによ
り、実質的に損失や駆動パルスに影響させることなく、
静電気やサージ電圧に対して保護される発光ダイオード
を見出し本願発明を成すに到った。
BEST MODE FOR CARRYING OUT THE INVENTION The present inventor has conducted various experiments,
By connecting a Zener diode having an appropriate Zener voltage Vz in anti-parallel to the nitride semiconductor light emitting device, the loss and the driving pulse are not substantially affected.
The inventors have found a light emitting diode protected against static electricity and surge voltage, and have accomplished the present invention.

【0014】即ち、本願発明は図1に示す回路を発光ダ
イオードに内蔵することにより、発光ダイオード単体
で、LEDチップ固有の特性を損なうことなく、静電気
やサージ電圧に対してもLEDチップを保護する発光ダ
イオードを得た。
That is, the present invention incorporates the circuit shown in FIG. 1 in a light emitting diode, so that the light emitting diode alone protects the LED chip against static electricity and surge voltage without impairing the characteristics inherent to the LED chip. A light emitting diode was obtained.

【0015】ツェナーダイオードは図2に示すような電
圧電流特性を有する。図2に於いて、横軸に電圧、縦軸
に電流を取ると、逆方向に電圧を印加していくとツェナ
ー電圧Vzを境にして低インピーダンスとなり電流が急
に流れ出す特性がある。順方向についても逆方向ほどの
急激な立ち上がりではないがある電圧Vfで電流が急に
流れる特性がある。
The Zener diode has a voltage-current characteristic as shown in FIG. In FIG. 2, when the voltage is plotted on the horizontal axis and the current is plotted on the vertical axis, the impedance becomes low at the boundary of the Zener voltage Vz and the current suddenly flows when the voltage is applied in the reverse direction. Also in the forward direction, there is a characteristic that the current suddenly flows at a voltage Vf which is not as sharp as the reverse.

【0016】このツェナーダイオードをLEDチップに
対して逆並列に接続した発光ダイオードに於いて、ツェ
ナーダイオードは、順方向では|Vz|以上の電圧に対
する電圧制限器として、逆方向では−Vf以下の電圧に
対する電圧制限器として作用する。ツェナー電圧|Vz
|がLEDチップ駆動電圧より高いツェナーダイオード
を用い、これをLEDチップに対して逆並列に接続する
と、発光ダイオードに対して順方向電圧|Vz|を越え
るサージ電圧が印加された場合、ツェナーダイオードは
電圧制限器として作用するから、バイパスとなる保護作
用をし、逆方向電圧−Vfを越えるサージ電圧に対して
もバイパスとなる保護作用をする。また、ツェナーダイ
オードのツェナー電圧Vzまでの漏れ電流は、LEDチ
ップ特性から考えると充分無視できる程度であるから、
LED装置定常駆動時においてLEDチップ固有の特性
を損なうことは無い。
In the light-emitting diode in which this zener diode is connected in antiparallel to the LED chip, the zener diode acts as a voltage limiter for a voltage of | Vz | or more in the forward direction, and a voltage of -Vf or less in the reverse direction. Acts as a voltage limiter for Zener voltage | Vz
When a Zener diode is used in which | is higher than the LED chip drive voltage and this is connected in anti-parallel to the LED chip, when a surge voltage exceeding the forward voltage | Vz | Since it acts as a voltage limiter, it acts as a bypass, and also acts as a bypass for surge voltages exceeding the reverse voltage -Vf. Also, since the leakage current of the Zener diode up to the Zener voltage Vz is sufficiently negligible in view of the LED chip characteristics,
At the time of steady driving of the LED device, the characteristic peculiar to the LED chip is not spoiled.

【0017】以上のことから、ツェナーダイオードをL
EDチップに対して逆並列に接続することにより、サー
ジ電圧や同様に静電気からも保護され、且つLEDチッ
プ固有の特性を損なうことの無い発光ダイオードを得る
ことができる。
From the above, the Zener diode is set to L
By connecting the LED chip in anti-parallel with the ED chip, it is possible to obtain a light emitting diode that is protected from surge voltage and also from static electricity and does not impair the characteristics inherent to the LED chip.

【0018】[0018]

【実施例】以下に本発明の一実施の形態である実施例を
用いて本発明を更に詳細に説明する。しかし本発明はこ
れに限定されない。 [実施例1]まず、窒化物半導体からなるLEDチップ
をMOCVD法を用いて予め洗浄したサファイア基板上
に成膜させる。MOCVD装置の反応容器内にサファイ
ア基板を配置させて水素ガスを流しながら800℃でベ
ーキングした。次に、原料ガスとしてTMG(トリメチ
ルガリウム)ガス、窒素ガス及びキャリアガスとして水
素ガスを流し、基板温度550℃でサファイア基板上に
バッファ層としてGaNを厚さ150Åで成膜させた。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to embodiments which are embodiments of the present invention. However, the present invention is not limited to this. [Example 1] First, an LED chip made of a nitride semiconductor is formed on a sapphire substrate that has been cleaned in advance by using the MOCVD method. A sapphire substrate was placed in a reaction vessel of an MOCVD apparatus, and baked at 800 ° C. while flowing hydrogen gas. Next, TMG (trimethyl gallium) gas as a source gas, hydrogen gas as a nitrogen gas and a carrier gas were flown, and GaN was formed as a buffer layer to a thickness of 150 ° on a sapphire substrate at a substrate temperature of 550 ° C.

【0019】バッファ層を成膜後、原料ガスの流入を止
め成膜温度を1050℃に上げて、原料ガスとしてTM
G、窒素ガス及びキャリアガスとして水素ガスを流しn
型GaNを厚さ1.5μmで成膜させた。続いて、n型
GaN上にn型電極を形成させるn型GaN層を成膜さ
せる。成膜温度を維持させたまま、原料ガスとしてTM
G、窒素ガス、キャリアガスとして水素ガス及びシラン
ガスを流しn+型GaNを厚さ2.3μmで成膜させ
た。成膜温度を維持させたまま、n+型GaN上に原料
ガスとしてTMG、窒素ガス及びキャリアガスとして水
素ガスを流しアンドープのGaNとSiドープのGaN
を20周期で成膜させてある。なお、GaN層の不純物
濃度が異なる変調ドープとしてある。変調ドープしたG
aN層上には活性層として250ÅのGaNと厚さ30
ÅのInGaNを6周期繰り返した多重量子井戸構造で
あり、両端がGaNである活性層を構成する。
After the formation of the buffer layer, the flow of the raw material gas is stopped, the film forming temperature is raised to 1050 ° C., and TM is used as the raw material gas.
G, nitrogen gas and hydrogen gas as carrier gas
Type GaN was formed into a film with a thickness of 1.5 μm. Subsequently, an n-type GaN layer for forming an n-type electrode is formed on the n-type GaN. While maintaining the film forming temperature, TM
G, a nitrogen gas, and a hydrogen gas and a silane gas as a carrier gas were flowed to form an n + -type GaN film having a thickness of 2.3 μm. While maintaining the film forming temperature, TMG as a source gas, hydrogen gas as a nitrogen gas and a carrier gas are flowed on the n + -type GaN, and undoped GaN and Si-doped GaN are flown.
Is formed in 20 cycles. Note that modulation doping is performed in which the impurity concentration of the GaN layer is different. Modulation-doped G
On the aN layer, GaN of 250 ° and a thickness of 30 are used as an active layer.
多重 has a multiple quantum well structure in which InGaN is repeated six times, and constitutes an active layer having GaN at both ends.

【0020】具体的には、成膜温度を1050℃に維持
したまま、変調ドープしたGaN層上に原料ガスとして
TMG、窒素ガス及びキャリアガスとして水素ガスを流
しアンドープのGaNを30Åで成膜させる。続いて、
キャリアガスだけを流しながら、成膜温度を800℃に
まで下げる。原料ガスとしてTMI(トリメチルインジ
ュウム)ガス、TMGガス、窒素ガス及びキャリアガス
として水素ガスを流し、アンドープのInGaNを25
0Åで成膜させる。これを、6周期繰り返した後、最後
に成膜温度を1050℃にし、原料ガスとしてTMG、
窒素ガス及びキャリアガスとして水素ガスを流しアンド
ープのGaNを30Åで成膜させ活性層を形成させる。
More specifically, while maintaining the film formation temperature at 1050 ° C., TMG as a source gas, hydrogen gas as a nitrogen gas, and a hydrogen gas as a carrier gas flow on the modulation-doped GaN layer to form undoped GaN at 30 °. . continue,
The film forming temperature is lowered to 800 ° C. while flowing only the carrier gas. A TMI (trimethyl indium) gas, a TMG gas, a nitrogen gas, and a hydrogen gas as a carrier gas are flowed as raw material gases, and undoped InGaN is supplied at 25%.
The film is formed at 0 °. After repeating this for 6 cycles, finally, the film forming temperature is set to 1050 ° C., and TMG,
An active layer is formed by flowing undoped GaN at 30 ° by flowing a hydrogen gas as a nitrogen gas and a carrier gas.

【0021】次に、活性層上には、p型クラッド層とし
て厚さ40ÅでMgドープのAlGaNと厚さ25Åで
MgドープのInGaNを5回繰り返した超格子p型ク
ラッド層を形成させる。成膜温度を1050℃に維持し
たまま、原料ガスとしてTMGガス、TMA(トリメチ
ルアルミニウム)ガス、窒素ガス、キャリアガスとして
水素ガス及びp型ドーパントしてCp2Mg(シクロペ
ンタジエニルマグネシウム)ガスを導入してp型AlG
aNを40Åで成膜させる。
Next, on the active layer, a superlattice p-type clad layer is formed as a p-type clad layer in which Mg-doped AlGaN having a thickness of 40 ° and Mg-doped InGaN having a thickness of 25 ° are repeated five times. While maintaining the film formation temperature at 1050 ° C., a TMG gas, a TMA (trimethylaluminum) gas, a nitrogen gas, a hydrogen gas as a carrier gas, and a Cp 2 Mg (cyclopentadienyl magnesium) gas as a p-type dopant are used as source gases. Introduce p-type AlG
aN is deposited at 40 °.

【0022】最後に成膜温度を1050℃に維持したま
ま原料ガスをTMGガス、窒素ガス、キャリアガスとし
て水素ガス及び不純物ガスとしてCp2Mgを流しp型
コンタクト層としてMgドープのGaNを成膜させる。
Finally, while the film formation temperature is maintained at 1050 ° C., the source gas is TMG gas, nitrogen gas, hydrogen gas as a carrier gas and Cp 2 Mg as an impurity gas, and Mg-doped GaN is formed as a p-type contact layer. Let it.

【0023】窒化物半導体ウエハを成膜後、RIEによ
りn型コンタクト層までが一部露出できるように活性層
などを除去する。その後、p型及びn型の各コンタクト
層にスパッタリングを用いて電極を形成させる。窒化物
半導体ウエハをスクライブして各LEDチップを形成さ
せる。こうしてサファイア基板上に多重量子井戸構造の
活性層が形成されダブルへテロ構造となる窒化物半導体
である発光素子が形成される。
After forming the nitride semiconductor wafer, the active layer and the like are removed by RIE so that the n-type contact layer can be partially exposed. Thereafter, an electrode is formed on each of the p-type and n-type contact layers by using sputtering. Each LED chip is formed by scribing the nitride semiconductor wafer. Thus, an active layer having a multiple quantum well structure is formed on the sapphire substrate, and a light emitting device which is a nitride semiconductor having a double hetero structure is formed.

【0024】図3は本発明の一実施例の形態であるキャ
ンタイプパッケージの発光ダイオードを示す模式図であ
る。以下にこの図を元に、窒化物半導体よりなる発光ダ
イオードを作成する。上記で得られたLEDチップ31
を、金メッキを施したステム33の収納部にAgペース
ト36で接合する。次にステムの収納部周縁のフラット
部にn基板ツェナーダイオードチップ32をAgペース
ト36で接合する。
FIG. 3 is a schematic view showing a light emitting diode of a can type package according to an embodiment of the present invention. Hereinafter, a light emitting diode made of a nitride semiconductor will be created based on this drawing. LED chip 31 obtained above
Is bonded to the receiving portion of the gold-plated stem 33 with an Ag paste 36. Next, the n-substrate zener diode chip 32 is bonded to the flat portion of the periphery of the storage portion of the stem with an Ag paste 36.

【0025】インナーリード33aとLEDチップ31
のn側取出電極(−極側)を、またマウントリード33
bとLEDチップ31のp側取出電極(+極側)を金線
35でワイヤーボンディングにより接続する。ステムの
インナーリード33aは、ステム33の収納部及びマウ
ントリード33bとは電気的に絶縁されている。次にツ
ェナーダイオードp側取出電極(+極側)とインナーリ
ード33aを金線35でワイヤーボンディングにより接
続する。
Inner lead 33a and LED chip 31
Of the n-side extraction electrode (negative pole side)
b and the p-side extraction electrode (+ pole side) of the LED chip 31 are connected by wire bonding with a gold wire 35. The inner lead 33a of the stem is electrically insulated from the storage part of the stem 33 and the mount lead 33b. Next, the Zener diode p-side extraction electrode (+ electrode side) and the inner lead 33a are connected by a gold wire 35 by wire bonding.

【0026】最後に、N2雰囲気中でキャップ34とス
テム33のフランジ部を抵抗溶接により溶着封止するこ
とにより、マウントリード33bを+極、インナーリー
ド33aを−極とし、ツェナーダイオードチップ32を
LEDチップ31に対して逆並列に接続した発光ダイオ
ードを形成した。
Finally, the cap 34 and the flange of the stem 33 are welded and sealed by resistance welding in an N 2 atmosphere, so that the mount lead 33b is a positive pole, the inner lead 33a is a negative pole, and the Zener diode chip 32 is A light emitting diode connected in antiparallel to the LED chip 31 was formed.

【0027】こうして得られた発光ダイオードの静電耐
圧を評価した。評価に用いた装置の試験回路を図6に示
す。電源Vの仕様は最大電圧3kV、最大電流3mAの
直流電圧とし、試験条件はコンデンサC容量を200p
F、抵抗Rを0Ωとした。なお、コンデンサCは試験電
圧に充分耐えられるものとし、切替スイッチSは絶縁抵
抗が高く、接触が低く、かつチャタリングのないものと
した。また、試験装置と供試品との配線は極力短くし、
浮遊容量はコンデンサC容量の5%以下とした。試験方
法は、装置の切替スイッチSを電源V側にし、試験電圧
をコンデンサCに充電する。切替スイッチSを供試品側
にして放電させる。次に試験電圧の極性を変えて同じ操
作を繰り返す。試験電圧は100Vステップで、最大
2.5kVまで設定した。
The light-emitting diode thus obtained was evaluated for electrostatic withstand voltage. FIG. 6 shows a test circuit of the device used for the evaluation. The specification of the power supply V is a DC voltage with a maximum voltage of 3 kV and a maximum current of 3 mA.
F and the resistance R were set to 0Ω. The capacitor C was designed to withstand the test voltage sufficiently, and the changeover switch S was designed to have high insulation resistance, low contact, and no chattering. In addition, the wiring between the test equipment and the DUT should be as short as possible,
The stray capacitance was 5% or less of the capacitance of the capacitor C. In the test method, the switch S of the device is set to the power supply V side, and the test voltage is charged in the capacitor C. The changeover switch S is set to the sample side to discharge. Next, the same operation is repeated while changing the polarity of the test voltage. The test voltage was set to a maximum of 2.5 kV in 100 V steps.

【0028】本実施例で得られた発光ダイオードの静電
耐圧評価結果は、順方向、逆方向共に2.5kVに耐え
ることまで確認した。2.5kV以上の電圧については
装置設定外であるため確認できていない。
The evaluation results of the electrostatic withstand voltage of the light emitting diode obtained in this example were confirmed to withstand 2.5 kV in both the forward and reverse directions. Since the voltage of 2.5 kV or more is outside the setting of the device, it cannot be confirmed.

【0029】[実施例2]図4は面実装タイプの発光ダ
イオードである。図4の上図は正面図で、下図は断面図
である。
[Embodiment 2] FIG. 4 shows a light emitting diode of a surface mounting type. 4 is a front view, and the lower figure is a cross-sectional view.

【0030】まず、銀メッキした銅製リードフレーム4
1を打ち抜きにより形成し、そのリードフレーム41に
射出成形法により発光ダイオードの外枠となるプラスチ
ックパッケージ42を形成する。次に、窒化ガリウム系
化合物半導体であるLEDチップ43を、プラスチック
パッケージ42収納部のリードフレーム41露出部にエ
ポキシ樹脂46で接合する。さらに、プラスチックパッ
ケージ42収納部のリードフレーム41露出部にn基板
ツェナーダイオードチップ44をAgペースト47で接
合する。プラスチックパッケージ42収納部のLEDチ
ップ43を接合したリードフレーム41とツェナーダイ
オードチップ44を接合したリードフレーム41はプラ
スチックにより電気的に絶縁されている。LEDチップ
43を接合したリードフレーム41とLEDチップ43
のn側取出電極(−極側)を、またツェナーダイオード
チップ44を接合したリードフレーム41とLEDチッ
プ43のp側取出電極(+極側)を金線45でワイヤー
ボンディングにより接続する。次にツェナーダイオード
チップ44p側取出電極(+極側)とLEDチップ43
を接合したリードフレーム41を金線45でワイヤーボ
ンディングにより接続する。
First, a silver-plated copper lead frame 4
1 is formed by punching, and a plastic package 42 serving as an outer frame of the light emitting diode is formed on the lead frame 41 by an injection molding method. Next, the LED chip 43, which is a gallium nitride-based compound semiconductor, is bonded to the exposed portion of the lead frame 41 in the housing portion of the plastic package 42 with the epoxy resin 46. Further, the n-substrate zener diode chip 44 is bonded to the exposed portion of the lead frame 41 in the storage portion of the plastic package 42 with an Ag paste 47. The lead frame 41 to which the LED chip 43 of the plastic package 42 is bonded and the lead frame 41 to which the zener diode chip 44 is bonded are electrically insulated by plastic. LED chip 43 and lead frame 41 to which LED chip 43 is bonded
And the lead frame 41 to which the Zener diode chip 44 has been joined and the p-side extraction electrode (+ pole side) of the LED chip 43 are connected by wire bonding with a gold wire 45. Next, the Zener diode chip 44p side extraction electrode (+ electrode side) and the LED chip 43
Are connected by wire bonding with a gold wire 45.

【0031】次に、プラスチックパッケージ42収納部
に光透過率の良い透明エポキシ樹脂を充填する。プラス
チックパッケージ42外枠から出たリードフレーム41
を最適形状に切断し、最後にそのリードをプラスチック
パッケージ42外枠に沿うように折り曲げる。以上によ
り、LEDチップ43に対してツェナーダイオードチッ
プ44を逆並列に接続した面実装タイプの発光ダイオー
ドを形成した。
Next, a transparent epoxy resin having a high light transmittance is filled in the housing portion of the plastic package 42. Lead frame 41 protruding from outer frame of plastic package 42
Is cut into an optimum shape, and finally, the leads are bent along the outer frame of the plastic package 42. As described above, a surface-mount type light-emitting diode in which the Zener diode chip 44 is connected in anti-parallel to the LED chip 43 was formed.

【0032】こうして得られた本実施例の発光ダイオー
ドに於いて、実施例1と同様の方法で静電耐圧を評価し
た結果、実施例1同様、順方向、逆方向共に2.5kV
に耐えることまで確認した。2.5kV以上の電圧につ
いては装置設定外であるため確認できていない。
In the thus obtained light emitting diode of the present embodiment, the electrostatic breakdown voltage was evaluated by the same method as in Example 1. As a result, as in Example 1, both the forward and reverse directions were 2.5 kV.
It was confirmed that it could endure. Since the voltage of 2.5 kV or more is outside the setting of the device, it cannot be confirmed.

【0033】[実施例3]図5は、砲弾型樹脂モールド
タイプの発光ダイオード断面図である。まず、銀メッキ
した銅製リードフレーム51を打ち抜きにより形成す
る。形成されたリードフレーム51は、マウントリード
51aの先端にLEDチップ52収納部であるカップ
と、カップ下部にツェナーダイオードチップ53を接合
可能な平坦部を有する。
[Embodiment 3] FIG. 5 is a sectional view of a light emitting diode of a shell type resin mold type. First, a copper lead frame 51 plated with silver is formed by punching. The formed lead frame 51 has a cup as an LED chip 52 accommodating portion at a tip of the mount lead 51a, and a flat portion at a lower portion of the cup to which a zener diode chip 53 can be joined.

【0034】リードフレーム51の収納部に窒化ガリウ
ム系化合物半導体であるLEDチップ52をエポキシ樹
脂56により接合する。続いて、インナーリード51b
とマウントリード51aに、図5に示すようにSMDツ
ェナーダイオードチップ53を溶接により接合する。
An LED chip 52, which is a gallium nitride-based compound semiconductor, is bonded to a housing portion of the lead frame 51 with an epoxy resin 56. Then, the inner lead 51b
The SMD Zener diode chip 53 is joined to the mounting lead 51a by welding as shown in FIG.

【0035】インナーリード51bとLEDチップ52
のn側取出電極(−極側)を、またマウントリード51
aとLEDチップ52のp側取出電極(+極側)を金線
54でワイヤーボンディングにより接続する。インナー
リード51bは、マウントリード51aと電気的に絶縁
されている。
Inner lead 51b and LED chip 52
Of the n-side extraction electrode (− pole side) of the
a and the p-side extraction electrode (+ pole side) of the LED chip 52 are connected by wire bonding with a gold wire 54. The inner lead 51b is electrically insulated from the mount lead 51a.

【0036】LEDチップ52及びツェナーダイオード
チップ54を外部応力、水分及び塵芥などから保護し、
かつ適切な配光特性を得る目的で、光透過性に優れたエ
ポキシ樹脂でモールドする。モールドは、エポキシ樹脂
を入れた砲弾型型枠に先記形成したリードフレームを挿
入し、加熱硬化させることで実施できる。以上により、
ツェナーダイオードチップ53をLEDチップ52に対
して逆並列に接続した砲弾型樹脂モールドタイプの発光
ダイオードを形成した。
The LED chip 52 and the Zener diode chip 54 are protected from external stress, moisture, dust, etc.
In addition, for the purpose of obtaining appropriate light distribution characteristics, it is molded with an epoxy resin having excellent light transmittance. The molding can be performed by inserting the lead frame formed above into a shell-shaped mold frame containing an epoxy resin and curing by heating. From the above,
A bullet-shaped resin mold type light emitting diode in which a Zener diode chip 53 was connected in antiparallel to the LED chip 52 was formed.

【0037】こうして得られた本実施例の発光ダイオー
ドに於いて、実施例1と同様の方法で静電耐圧を評価し
た結果、実施例1同様、順方向、逆方向共に2.5kV
に耐えることまで確認した。2.5kV以上の電圧につ
いては装置設定外であるため確認できていない。
The thus obtained light emitting diode of the present embodiment was evaluated for electrostatic withstand voltage by the same method as in Example 1. As a result, as in Example 1, both the forward and reverse directions were 2.5 kV.
It was confirmed that it could endure. Since the voltage of 2.5 kV or more is outside the setting of the device, it cannot be confirmed.

【0038】[0038]

【発明の効果】以上説明したように、本発明によれば、
ツェナーダイオードをLEDチップに対して逆並列に接
続することにより、静電気やサージ電圧から保護され、
且つLEDチップ固有の特性を損なうことのない発光ダ
イオードを得ることができる。
As described above, according to the present invention,
By connecting the Zener diode in anti-parallel to the LED chip, it is protected from static electricity and surge voltage,
In addition, it is possible to obtain a light emitting diode that does not impair the characteristics unique to the LED chip.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の発光ダイオードの回路図を示す。FIG. 1 shows a circuit diagram of a light emitting diode of the present invention.

【図2】 ツェナーダイオードの電圧電流特性図を示
す。
FIG. 2 shows a voltage-current characteristic diagram of a Zener diode.

【図3】 実施例1のキャンタイプパッケージである発
光ダイオードの斜視図を示す。
FIG. 3 is a perspective view of a light emitting diode which is a can type package according to the first embodiment.

【図4】 実施例2の面実装タイプである発光ダイオー
ドの正面図及び断面図を示す。
FIGS. 4A and 4B are a front view and a cross-sectional view of a surface-mount type light emitting diode according to a second embodiment. FIGS.

【図5】 実施例3の砲弾型樹脂モールドタイプである
発光ダイオードの模式的断面図を示す。
FIG. 5 is a schematic sectional view of a light emitting diode of a shell type resin mold type according to a third embodiment.

【図6】 静電耐圧評価試験装置の回路図を示す。FIG. 6 shows a circuit diagram of an electrostatic withstand voltage evaluation test apparatus.

【符号の説明】[Explanation of symbols]

21、31、43、52・・・LEDチップ 22、32、44、53・・・ツェナーダイオードチッ
プ 35、45、54・・・金線 41、51・・・リードフレーム 33・・・ステム 34・・・キャップ 42・・・プラスチックパッケージ 58・・・モールド樹脂 36、47・・・Agペースト 46、56・・・エポキシ樹脂 57・・・溶接による金属片
21, 31, 43, 52: LED chip 22, 32, 44, 53: Zener diode chip 35, 45, 54: Gold wire 41, 51: Lead frame 33: Stem 34 ..Cap 42 ... Plastic package 58 ... Mold resin 36,47 ... Ag paste 46,56 ... Epoxy resin 57 ... Metal piece by welding

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 発光層に3族窒化物半導体を用いた発光
素子を有する発光ダイオードであって、前記発光素子に
対してツェナーダイオードが逆並列に電気接続されてい
ることを特徴とする発光ダイオード。
1. A light emitting diode having a light emitting element using a group III nitride semiconductor for a light emitting layer, wherein a zener diode is electrically connected in anti-parallel to the light emitting element. .
【請求項2】 前記発光素子がサファイア基板上に形成
されたダブルへテロ構造である請求項1記載の発光ダイ
オード。
2. The light emitting diode according to claim 1, wherein said light emitting element has a double hetero structure formed on a sapphire substrate.
JP31936298A 1998-11-10 1998-11-10 Light emitting diode Pending JP2000150962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31936298A JP2000150962A (en) 1998-11-10 1998-11-10 Light emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31936298A JP2000150962A (en) 1998-11-10 1998-11-10 Light emitting diode

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2004303593A Division JP4626258B2 (en) 2004-10-18 2004-10-18 Light emitting diode

Publications (1)

Publication Number Publication Date
JP2000150962A true JP2000150962A (en) 2000-05-30

Family

ID=18109313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31936298A Pending JP2000150962A (en) 1998-11-10 1998-11-10 Light emitting diode

Country Status (1)

Country Link
JP (1) JP2000150962A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005013381A1 (en) * 2003-07-30 2005-02-10 Epivalley Co., Ltd. Light emitting diode and light emitting device with the same
KR100643471B1 (en) 2005-11-24 2006-11-10 엘지전자 주식회사 Light emitting diode pakage and fabricating method thereof
JP2008211132A (en) * 2007-02-28 2008-09-11 Koa Corp Light-emitting component
JP2009081460A (en) * 2008-12-08 2009-04-16 Nichia Corp Semiconductor light-emitting device equipped with metallic package
JP2011139109A (en) * 2007-04-23 2011-07-14 Samsung Led Co Ltd Light emitting device
CN102456683A (en) * 2010-10-22 2012-05-16 展晶科技(深圳)有限公司 Light-emitting diode packaging structure
WO2013009081A2 (en) * 2011-07-14 2013-01-17 주식회사 포인트엔지니어링 Substrate for an optical device having a zener diode
US8735935B2 (en) 2007-04-23 2014-05-27 Samsung Electronics Co., Ltd Small size light emitting device and manufacturing method of the same
CN106876550A (en) * 2016-12-29 2017-06-20 广东长盈精密技术有限公司 LED encapsulation structure and preparation method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005013381A1 (en) * 2003-07-30 2005-02-10 Epivalley Co., Ltd. Light emitting diode and light emitting device with the same
KR100643471B1 (en) 2005-11-24 2006-11-10 엘지전자 주식회사 Light emitting diode pakage and fabricating method thereof
JP2008211132A (en) * 2007-02-28 2008-09-11 Koa Corp Light-emitting component
JP2011139109A (en) * 2007-04-23 2011-07-14 Samsung Led Co Ltd Light emitting device
US8735935B2 (en) 2007-04-23 2014-05-27 Samsung Electronics Co., Ltd Small size light emitting device and manufacturing method of the same
JP2009081460A (en) * 2008-12-08 2009-04-16 Nichia Corp Semiconductor light-emitting device equipped with metallic package
CN102456683A (en) * 2010-10-22 2012-05-16 展晶科技(深圳)有限公司 Light-emitting diode packaging structure
WO2013009081A2 (en) * 2011-07-14 2013-01-17 주식회사 포인트엔지니어링 Substrate for an optical device having a zener diode
WO2013009081A3 (en) * 2011-07-14 2013-03-14 주식회사 포인트엔지니어링 Substrate for an optical device having a zener diode
CN106876550A (en) * 2016-12-29 2017-06-20 广东长盈精密技术有限公司 LED encapsulation structure and preparation method thereof

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