JP3348843B2 - Light emitting diode and dot matrix display using the same - Google Patents

Light emitting diode and dot matrix display using the same

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Publication number
JP3348843B2
JP3348843B2 JP2000046647A JP2000046647A JP3348843B2 JP 3348843 B2 JP3348843 B2 JP 3348843B2 JP 2000046647 A JP2000046647 A JP 2000046647A JP 2000046647 A JP2000046647 A JP 2000046647A JP 3348843 B2 JP3348843 B2 JP 3348843B2
Authority
JP
Japan
Prior art keywords
light emitting
light
emitting diode
voltage
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000046647A
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Japanese (ja)
Other versions
JP2000312033A (en
Inventor
義則 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Corp
Original Assignee
Nichia Corp
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Publication of JP2000312033A publication Critical patent/JP2000312033A/en
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Publication of JP3348843B2 publication Critical patent/JP3348843B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、紫外域から可視光
まで発光可能な窒化物半導体発光素子を用いた発光ダイ
オード等に係わり、特に、マトリックス状に接続させた
LEDディスプレイを構成させた場合などにおいても誤
作動することなく、発光素子が電気的に損傷されること
がない発光ダイオード及びそれを用いたドットマトリッ
クスディスプレイに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode using a nitride semiconductor light emitting device capable of emitting light from the ultraviolet region to visible light, and particularly to a case where an LED display connected in a matrix is constructed. The present invention relates to a light emitting diode in which a light emitting element is not electrically damaged without malfunction and a dot matrix display using the same.

【0002】[0002]

【従来技術】近紫外から黄色まで高輝度に発光可能な発
光素子として窒化物半導体(InxAlyGa1-x-yN、
0≦x≦1、0≦y≦1)を利用した発光ダイオードが
実用化された。これにより、液晶バックライトの光源や
プリンターの書き込み光源など種々の分野に急速に利用
され始めている。窒化物半導体は結晶性の優れた半導体
を量産性よく形成させることが難しく、現在のところサ
ファイア基板やSiC基板上にバッファ層を介して成膜
させてある。そのため、窒化物半導体を用いた発光素子
は通常の発光素子に比べて結晶欠陥などが多く結晶性が
悪いが故に耐電圧が低いと考えられている。特に、発光
層の組成にAl及び/又はInの元素を含み紫外域など
の短波長側や可視光の長波長側に発光ピークを持った窒
化物半導体を利用した発光素子を形成させるほど良好な
膜を形成させることが難しい傾向にある。また、サファ
イア基板など絶縁性基板上に窒化物半導体を成膜させた
発光素子は、導通する半導体層領域が総膜厚でも約10
μmにも満たない薄さのため電圧がかかると破壊されや
すい傾向にある。
2. Description of the Related Art A nitride semiconductor (InxAlyGa1-x-yN,
Light emitting diodes utilizing 0 ≦ x ≦ 1, 0 ≦ y ≦ 1) have been put to practical use. Accordingly, it has begun to be rapidly used in various fields such as a light source of a liquid crystal backlight and a writing light source of a printer. It is difficult to form a semiconductor having excellent crystallinity with good mass productivity, and a nitride semiconductor is currently formed on a sapphire substrate or a SiC substrate via a buffer layer. Therefore, a light-emitting element using a nitride semiconductor is considered to have a lower withstand voltage because of more crystal defects and poor crystallinity than a normal light-emitting element. In particular, the composition of the light-emitting layer contains Al and / or In elements, and is preferable as a light-emitting element using a nitride semiconductor having a light emission peak on a short wavelength side such as an ultraviolet region or a long wavelength side of visible light is formed. It tends to be difficult to form a film. Further, in a light-emitting element in which a nitride semiconductor is formed on an insulating substrate such as a sapphire substrate, the conductive semiconductor layer region has a total thickness of about 10%.
Since the thickness is less than μm, it tends to be broken when a voltage is applied.

【0003】さらに、発光効率をより向上させるため、
発光層が単一量子井戸構造や多重量子井戸構造とされる
極めて薄膜で形成させることが行われている。そのた
め、小型、高効率、小電流で高出力を有する優れた特性
を持つ窒化物半導体を用いた発光素子は、少しの静電気
電圧で破壊され易いという問題がある。
Further, in order to further improve the luminous efficiency,
2. Description of the Related Art A light emitting layer is formed of an extremely thin film having a single quantum well structure or a multiple quantum well structure. Therefore, there is a problem that a light-emitting element using a nitride semiconductor having excellent characteristics having a small size, high efficiency, high output at a small current and high output is easily broken by a small electrostatic voltage.

【0004】例えば、通常の発光層がAlGaInPな
どからなる赤色や赤外光が発光可能な発光ダイオード
は、約2KVの耐電圧があるのに対し、発光層がInG
aNからなる青色、緑色、黄色などが発光可能な発光素
子の耐電圧は約0.5KV以下にしかすぎない。特に、
Alが含有された紫外発光可能な窒化物半導体発光素子
に至っては約0.2KV以下である(なお、発光素子ま
での抵抗がほぼ0オーム、スイッチングにより200p
Fのコンデンサから発光素子に電流を流して耐電圧試験
をしてある。)。上述の如く、3族窒化物半導体からな
る発光ダイオードは、他の半導体発光素子と異なり、構
造上、電気的なショックにより比較的低い逆方向電圧だ
けでなく順方向電圧であっても発光素子に破壊が起こり
やすい。
For example, a light emitting diode whose normal light emitting layer is made of AlGaInP or the like and is capable of emitting red or infrared light has a withstand voltage of about 2 KV, while the light emitting layer is made of InG
The withstand voltage of a light-emitting element made of aN, which can emit blue, green, yellow, etc., is only about 0.5 KV or less. In particular,
In the case of a nitride semiconductor light emitting device capable of emitting ultraviolet light containing Al, the voltage is about 0.2 KV or less (the resistance to the light emitting device is almost 0 ohm, and 200p by switching.
A withstand voltage test was performed by passing a current from the capacitor of F to the light emitting element. ). As described above, unlike other semiconductor light emitting devices, a light emitting diode made of a group III nitride semiconductor is not only relatively low in reverse voltage but also forward voltage due to an electric shock due to an electric shock. Destruction is easy to occur.

【0005】静電気及びサージ電圧対策としては、発光
素子を破壊させる過大な電流が流れ込まないよう制限す
る半導体保護素子を設けることが考えられる。例えば、
ツェナーダイオードを半導体保護素子として発光素子と
逆並列に接続させる。これにより、静電気やサージに対
し、見かけ上発光素子の耐電性を強くすることができ
る。具体的一例を図7に示す。図7(A)には、マウント
リード51aのカップ内にLEDチップ52をダイボン
ド樹脂56を用いて配置固定させると共に、LEDチッ
プ52をマウントリード51a及びインナーリード51
bとワイヤ54を用いて電気的に接続させる。また、マ
ウントリード51a上には半導体保護素子としてツェナ
ーダイオード57が配置される。ツェナーダイオード5
7はマウントリード51aと銀ペーストで固定されると
共にツェナーダイオードの他方の電極とインナーリード
51bとをワイヤで電気的に接続させる。図7(B)に
は、図7(A)の等価回路図を示す。
[0005] As a countermeasure against static electricity and surge voltage, it is conceivable to provide a semiconductor protection element for restricting an excessive current for destroying the light emitting element from flowing. For example,
The Zener diode is connected in antiparallel with the light emitting element as a semiconductor protection element. This makes it possible to apparently increase the light resistance of the light emitting element against static electricity and surge. FIG. 7 shows a specific example. 7A, the LED chip 52 is arranged and fixed in the cup of the mount lead 51a using the die bond resin 56, and the LED chip 52 is connected to the mount lead 51a and the inner lead 51. FIG.
b and the wires 54 are used to make electrical connection. Further, a Zener diode 57 is arranged on the mount lead 51a as a semiconductor protection element. Zener diode 5
Reference numeral 7 fixes the mount lead 51a to the silver paste and electrically connects the other electrode of the Zener diode to the inner lead 51b with a wire. FIG. 7B shows an equivalent circuit diagram of FIG.

【0006】これにより、LEDチップにツェナーダイ
オードが逆並列に電気的に接続されることとなる。LE
Dチップが配置され、電気的に接続されたマウントリー
ド及びインナーリードの先端をエポキシ樹脂58などに
より封止し、発光ダイオードを形成させることができ
る。なお、図8に半導体発光素子(波線)とツェナーダ
イオード(実線)の電流電圧特性をそれぞれ示す。この
発光素子を点灯させるために順方向電流を流す場合、半
導体保護素子であるツェナーダイオードは逆並列に接続
されているため電流が実質的に流れない。そのため、発
光ダイオードの駆動電圧により、効率よく発光素子であ
るLEDチップを発光させることができる。他方、発光
素子が破壊されるサージ電圧が順方向に印加されると、
ツェナーダイオードが発光素子が破壊されるサージ電圧
よりも低い電圧VZに制限する。即ち、LEDチップが
破壊される電圧よりも小さい電圧に選択した立ち上がり
電圧でツェナーダイオードに電流が流れ定電圧化し、L
EDチップに大きな電圧が掛かることがない。
As a result, the Zener diode is electrically connected to the LED chip in anti-parallel. LE
The tips of the mount leads and the inner leads on which the D chips are arranged and electrically connected are sealed with an epoxy resin 58 or the like, so that a light emitting diode can be formed. FIG. 8 shows the current-voltage characteristics of the semiconductor light emitting element (broken line) and the Zener diode (solid line), respectively. When a forward current is applied to turn on the light emitting element, substantially no current flows because the Zener diode, which is a semiconductor protection element, is connected in anti-parallel. Therefore, the LED chip, which is a light emitting element, can emit light efficiently with the driving voltage of the light emitting diode. On the other hand, when a surge voltage that destroys the light emitting element is applied in the forward direction,
The Zener diode limits the voltage to a voltage VZ lower than the surge voltage at which the light emitting element is destroyed. That is, a current flows through the Zener diode at a rising voltage selected to a voltage lower than the voltage at which the LED chip is destroyed, and a constant voltage is generated.
No large voltage is applied to the ED chip.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、このよ
うなツェナーダイオードで発光素子が保護された発光ダ
イオードをマトリックス状に配置させたLEDディスプ
レイに利用した場合、新たな問題が生ずることが分かっ
た。この発光ダイオードを用いダイナミック駆動させる
ためにマトリックス状に配置させたLEDディスプレイ
の模式的回路構成を図9に示す。図9にはLEDチップ
と、ツェナーダイオードが逆方向に接続された発光ダイ
オードをL1からL12の如くマトリックス状に配置さ
せてある。発光ダイオードは各列及び行ごとに接続さ
れ、各列及び行が選択された発光ダイオードのみが発光
可能となる。この回路に上記したツェナーダイオードを
保護素子として組み込まれた発光ダイオードを配置させ
た場合、半導体保護素子を介して電流が他の回路に流れ
込み、意図しない発光ダイオードが発光されることとな
る。
However, it has been found that a new problem arises when an LED display in which light-emitting diodes whose light-emitting elements are protected by such zener diodes are arranged in a matrix is used. FIG. 9 shows a schematic circuit configuration of an LED display arranged in a matrix for dynamic driving using the light emitting diodes. In FIG. 9, LED chips and light-emitting diodes in which zener diodes are connected in opposite directions are arranged in a matrix like L1 to L12. The light emitting diode is connected for each column and row, and only the light emitting diode of which column and row is selected can emit light. When a light emitting diode in which the above-mentioned zener diode is incorporated as a protection element is arranged in this circuit, a current flows into another circuit via the semiconductor protection element, and an unintended light emitting diode emits light.

【0008】このような発光ダイオードの意図しない点
灯は、所望の発光ダイオードL1及びL7の点灯輝度が
下がるばかりでなく、LEDディスプレイ全体のコント
ラストの低下や誤作動を引き起こす要因となる。従って
ツェナーダイオードや通常のシリコンダイオードは、マ
トリックス状の回路構成のディスプレイには不向きであ
り、実質的に使えない。また、発光素子の不良チェック
は逆方向漏れ電流の有無で行う場合が、単なるツェナー
ダイオードなどの保護素子を並列に接続させただけで
は、保護素子の特性上発光ダイオードの逆方向が保護素
子を介して通電するため不良チェックができないという
不都合が生じる。したがって、本願発明は、静電気やサ
ージ電圧に対し発光素子を保護すると共に誤作動のない
発光ダイオードを提供することを目的とする。また、発
光素子の不良チェックが簡単に行える発光ダイオードを
提供することを目的とする。
[0008] Such unintended lighting of the light emitting diodes not only lowers the lighting brightness of the desired light emitting diodes L1 and L7, but also causes a reduction in the contrast and malfunction of the entire LED display. Therefore, a Zener diode or a normal silicon diode is not suitable for a display having a circuit configuration in a matrix form, and is substantially unusable. In addition, when a defect check of a light emitting element is performed based on the presence or absence of a reverse leakage current, simply connecting a protection element such as a zener diode in parallel causes the reverse direction of the light emitting diode to pass through the protection element due to the characteristics of the protection element. Inconveniently, it is not possible to perform a defect check because the current is supplied. Therefore, an object of the present invention is to provide a light emitting diode that protects a light emitting element against static electricity and surge voltage and does not malfunction. It is another object of the present invention to provide a light emitting diode that can easily check for a defect in a light emitting element.

【0009】[0009]

【課題を解決するための手段】本発明は、少なくとも発
光層がGaを含む窒化物半導体である発光素子と、該発
光素子を電気的に保護するための半導体保護素子とを有
する発光ダイオードである。特に、発光素子と並列接続
された半導体保護素子は、双方向とも発光素子の順方向
電圧以上の電圧において導通することを特徴とする。よ
り具体的には、発光素子と並列接続された半導体保護素
は負性抵抗特性を有することとさせる。これにより、
発光素子の破壊や誤動作を抑制することができる。ま
た、電圧の低い領域では実質的にほとんど保護素子を介
さず、電流が流れるため発光素子の不良チェックを簡単
に行うことができる。
According to the present invention, there is provided a light emitting diode having a light emitting element in which at least a light emitting layer is a nitride semiconductor containing Ga, and a semiconductor protection element for electrically protecting the light emitting element. . In particular, the semiconductor protection element connected in parallel with the light emitting element conducts at a voltage higher than the forward voltage of the light emitting element in both directions. More specifically, the semiconductor protection element connected in parallel with the light emitting element has a negative resistance characteristic. This allows
Destruction and malfunction of the light emitting element can be suppressed. Further, in a region where the voltage is low, a current flows substantially without passing through the protection element, so that the defect check of the light emitting element can be easily performed.

【0010】本発明の請求項2に記載の発光ダイオード
は、少なくとも発光層にInとGaとを有する窒化物半
導体を用いた発光素子と、発光素子と並列接続され発光
素子を電気的に保護するための半導体保護素子とを有す
る。特に、半導体保護素子は、トリガダイオード、ベー
スをオープンにさせたトランジスタから選択される少な
くとも1種を有する。
According to a second aspect of the present invention, there is provided a light emitting diode using a nitride semiconductor having at least a light emitting layer containing In and Ga, and a light emitting element connected in parallel with the light emitting element to electrically protect the light emitting element. And a semiconductor protection element. In particular, the semiconductor protection element has at least one trigger diodes are transistors data or we selected that is open to the base.

【0011】本発明の請求項3に記載の発光ダイオード
は、発光素子がサファイア基板上に少なくとも発光層が
Gaを含む窒化物半導体を介してp型及びn型の窒化物
半導体を有する。
In a light emitting diode according to a third aspect of the present invention, the light emitting device has p-type and n-type nitride semiconductors on a sapphire substrate with at least a light emitting layer interposed through a nitride semiconductor containing Ga.

【0012】本発明の請求項4に記載のドットマトリッ
クスディスプレイは、特定の保護素子を持った発光ダイ
オードをダイナミック駆動させる構成のドットマトリッ
クスディスプレイとすることで、誤作動等のないドット
マトリックスディスプレイとすることができる。
The dot matrix display according to a fourth aspect of the present invention is a dot matrix display having a configuration in which a light emitting diode having a specific protection element is dynamically driven to thereby prevent a malfunction or the like. be able to.

【0013】[0013]

【発明の実施の形態】本願発明者は種々の実験の結果、
窒化物半導体発光素子を用いた発光ダイオードの順方向
或いは逆方向の両方に対して、実質的に損失や駆動回路
に影響されることなく、静電気やサージ電圧に対して保
護される発光ダイオードを見出し本願発明を成すに到っ
た。
BEST MODE FOR CARRYING OUT THE INVENTION The present inventor has conducted various experiments,
A light-emitting diode that is protected against static electricity and surge voltage in both the forward and reverse directions of a light-emitting diode using a nitride semiconductor light-emitting element without being substantially affected by loss or a drive circuit. The present invention has been accomplished.

【0014】即ち、本願発明は図1に示す回路を発光ダ
イオードに内蔵することにより、発光ダイオード単体
で、LEDチップ固有の特性を損なうことなく、静電気
やサージ電圧に対してもLEDチップを保護する発光ダ
イオードを得た。
That is, the present invention incorporates the circuit shown in FIG. 1 in a light emitting diode, so that the light emitting diode alone protects the LED chip against static electricity and surge voltage without impairing the characteristics inherent to the LED chip. A light emitting diode was obtained.

【0015】本発明に用いられる半導体保護素子として
のトリガダイオードは、図2に示すような電圧電流特性
を有する。図2に於いて、横軸に電圧、縦軸に電流を取
り、それぞれの方向に電圧を印加していくと降伏電圧V
BOを境にして低インピーダンスとなり電流が急に流れ出
す特性がある。なお、図2において、窒化物半導体発光
素子を点線で示し、トリガーダイオードを実線で示す。
トリガーダイオードには極性がないため、それぞれの方
向にほぼ対称な特性を示す。
A trigger diode as a semiconductor protection element used in the present invention has a voltage-current characteristic as shown in FIG. In FIG. 2, the voltage is plotted on the horizontal axis and the current is plotted on the vertical axis, and when the voltage is applied in each direction, the breakdown voltage V
There is a characteristic that the impedance becomes low at the border of BO and the current suddenly flows. In FIG. 2, the nitride semiconductor light emitting device is indicated by a dotted line, and the trigger diode is indicated by a solid line.
Since the trigger diode has no polarity, it exhibits substantially symmetric characteristics in each direction.

【0016】このトリガダイオードをLEDチップに対
して並列に接続した発光ダイオードに於いて、トリガダ
イオードは、発光素子の順方向及び逆方方向において、
|VBO|以上の電圧に対する電圧制限器として作用す
る。降伏電圧|VBO|がLEDチップの駆動電圧より高
いトリガダイオードを選択して使用することにより、発
光ダイオードに対して静電気やサージ電圧が印加された
場合、トリガダイオードは電圧制限器として作用するか
ら、バイパスとなる保護作用をする。したがって、降伏
電圧|VBO|を越える電圧は発光素子に印加されず、発
光素子が破壊されることはない。
In the light emitting diode in which the trigger diode is connected in parallel to the LED chip, the trigger diode is arranged in the forward and reverse directions of the light emitting element.
Acts as a voltage limiter for voltages greater than | VBO |. By selecting and using a trigger diode whose breakdown voltage | VBO | is higher than the driving voltage of the LED chip, the trigger diode acts as a voltage limiter when static electricity or surge voltage is applied to the light emitting diode. It acts as a bypass protection. Therefore, a voltage exceeding the breakdown voltage | VBO | is not applied to the light emitting element, and the light emitting element is not destroyed.

【0017】また、逆方向においても降伏電圧までは導
通せず電流阻止能力があるため、マトリック状に接続さ
せた各発光ダイオードに、電流回り込みによる誤作動が
生ずることを防止する作用をする。さらに、トリガダイ
オードの降伏電圧VBOまでの漏れ電流は、LEDチップ
特性から考えると充分小さく、無視できる程度である。
したがって、LED装置定常駆動時においても発光素子
固有の特性を損なうことはない。
In addition, since it does not conduct to the breakdown voltage even in the reverse direction and has a current blocking capability, it functions to prevent malfunctions due to current sneak in each of the light emitting diodes connected in a matrix. Furthermore, the leakage current of the trigger diode up to the breakdown voltage VBO is sufficiently small and negligible in view of the LED chip characteristics.
Therefore, even during the steady driving of the LED device, the characteristics unique to the light emitting element are not impaired.

【0018】また、トランジスターを用いた場合、例え
ばベースをオープンとしたnpn型のトランジスターで
は、電圧電流特性は図10のようになる(なお、ここ
で、本発明のトランジスターとは広義に解釈するものと
し、必ずしも3端子が露出しているものだけでなく、n
pn接合やpnp接合された半導体に二端子だけが露出
させた半導体保護素子も含む)。図10(A)中の波線
は発光素子を示し、実線はトランジスターを示す。この
特性は、発光素子であるLED1001のアノードをト
ランジスター1002のエミッタと、LEDのカソード
をトランジスターのコレクターと接続した場合、LED
に対して順方向ではツェナーダイオードと同じ特性に、
逆方向ではトリガーダイオードと同じ特性の保護回路と
して働く。一般にGaN系LEDは逆方向の過電圧によ
り弱く、保護回路としての整合性は良好である。図10
(B)は、図10(A)の等価回路図を示す。
When a transistor is used, for example, in an npn-type transistor having an open base, the voltage-current characteristics are as shown in FIG. 10 (here, the transistor of the present invention is to be interpreted in a broad sense). And not only those having three exposed terminals, but also n
(Including a semiconductor protection element in which only two terminals are exposed to a pn junction or a pnp junction semiconductor.) A wavy line in FIG. 10A indicates a light-emitting element, and a solid line indicates a transistor. This characteristic is obtained by connecting the anode of the LED 1001, which is a light emitting element, to the emitter of the transistor 1002 and the cathode of the LED to the collector of the transistor.
In the forward direction, it has the same characteristics as the Zener diode,
In the reverse direction, it functions as a protection circuit having the same characteristics as the trigger diode. Generally, a GaN-based LED is weak due to an overvoltage in the reverse direction, and has good matching as a protection circuit. FIG.
FIG. 10B shows an equivalent circuit diagram of FIG.

【0019】また、トランジスターを使用する場合、他
の保護素子と比べてより大きな長所があるすなわち、実
際の発光素子であるLEDチップや、量産されているツ
ェナーダイオードや、トリガダイオード及びトランジス
ターを実装した場合、半導体素子の構造や極性、実装方
法によって厄介な問題を生じる場合がある。シリコンを
利用したツェナーダイオードやトランジスターなどはn
型基板が得やすく、n型基板使用の方が特性、コスト面
で有利である。このため、ほとんどのダイオードは基板
がn型半導体でボンディング電極がp型半導体となって
いる。
When a transistor is used, it has a greater advantage than other protection elements. That is, an LED chip which is an actual light emitting element, a Zener diode, a trigger diode, and a transistor which are mass-produced are mounted. In this case, a troublesome problem may occur depending on the structure, polarity, and mounting method of the semiconductor element. Zener diodes and transistors using silicon are n
A mold substrate is easily obtained, and the use of an n-type substrate is advantageous in terms of characteristics and cost. For this reason, most diodes have an n-type semiconductor substrate and a p-type semiconductor bonding electrode.

【0020】一方、窒化物半導体であるGaN系LED
はサファイア基板上に形成される場合があり、サファイ
アなどの絶縁基板を利用する場合には基本的に極性はな
い。しかし、例えばツェナーダイオードを共通の導電性
基体に乗せる場合、自ずから極性は決まってしまうこと
になる。すなわち、この場合発光素子が搭載されるフレ
ーム(導電性基体)がアノード(正極)と決まる。とこ
ろが、この接続が信頼性面で重要な問題を提起する場合
がある。発光素子であるLEDのフレームには反射効率
を向上させる等のため、銀メッキが施すことがある。こ
れに正の電圧が印加された場合、外部から浸入等した水
分と反応し、銀のマイグレーション作用により短絡する
危険性がある。しかも、GaN系LEDはn型半導体層
がサファイア側であり、フレームと露出したn型半導体
層間に順方向電圧がかかり、マイグレーションを起こす
方向と一致してしまう。極性は逆の方が好ましいのであ
るがツェナーダイオードがこの極性を決めてしまうので
ある。
On the other hand, a GaN-based LED which is a nitride semiconductor
May be formed on a sapphire substrate, and there is basically no polarity when an insulating substrate such as sapphire is used. However, for example, when a Zener diode is mounted on a common conductive substrate, the polarity is naturally determined. That is, in this case, the frame (conductive base) on which the light emitting element is mounted is determined as the anode (positive electrode). However, this connection can raise significant reliability issues. Silver plating may be applied to the frame of the LED, which is a light emitting element, in order to improve the reflection efficiency. When a positive voltage is applied to this, there is a risk of reacting with moisture that has entered from the outside and short-circuiting due to the migration action of silver. In addition, in the GaN-based LED, the n-type semiconductor layer is on the sapphire side, and a forward voltage is applied between the frame and the exposed n-type semiconductor layer, which matches the direction in which migration occurs. It is preferable that the polarity is reversed, but the zener diode determines this polarity.

【0021】ここで、同じn型半導体基板を使ったnp
nトランジスターを見てみると、フレームを負極に実装
可能なことが判る。すなわち、トランジスターによる保
護回路は、保護能力、誤動作防止の他に信頼性面でも大
きな長所を有することになるのである。
Here, np using the same n-type semiconductor substrate
A look at the n-transistor shows that the frame can be mounted on the negative electrode. In other words, a protection circuit using transistors has great advantages in terms of reliability in addition to protection ability and prevention of malfunction.

【0022】以上のことから、双方向形の保護機能を有
する半導体保護素子をLEDと並列接続させ、半導体保
護素子の電圧内でLEDを駆動させる。これより、LE
Dチップ固有の特性を損なうことのなく静電気やサージ
電圧から発光素子を保護し、且つ発光ダイオードの誤作
動を防止することができる。なお、半導体保護素子は、
上述の双方向形の保護機能を有する限り、トリガダイオ
ード、ベースをオープンにさせたトランジスタ、バリス
タ及び逆方向に直列接続されたツェナーダイオードやこ
れらの特性を含むIC、LSIなどを利用することもで
きる。以下に本発明の一実施の形態である実施例を用い
て本発明を更に詳細に説明する。しかし本発明はこれの
みに限定されないことはいうまでもない。
From the above, a semiconductor protection element having a bidirectional protection function is connected in parallel with an LED, and the LED is driven within the voltage of the semiconductor protection element. From this, LE
The light emitting element can be protected from static electricity and surge voltage without impairing the characteristics inherent to the D chip, and malfunction of the light emitting diode can be prevented. The semiconductor protection element is
As long as it has the above-described bidirectional protection function, a trigger diode, a transistor having an open base, a varistor, a zener diode connected in series in the reverse direction, and an IC or LSI including these characteristics can also be used. . Hereinafter, the present invention will be described in more detail with reference to Examples, which are embodiments of the present invention. However, it goes without saying that the present invention is not limited to this.

【0023】[0023]

【実施例】[実施例1]窒化物半導体をMOCVD法を
用いて予め洗浄したサファイア基板上に成膜させ発光素
子であるLEDを形成させる。MOCVD装置の反応容
器内にサファイア基板を配置させて、水素ガスを流しな
がら800℃でベーキングする。次に、原料ガスとして
TMG(トリメチルガリウム)ガス、窒素ガス及びキャ
リアガスとして水素ガスを流し、基板温度550℃でサ
ファイア基板上にバッファ層としてGaNを厚さ150
Åで成膜させる。
[Example 1] A nitride semiconductor is deposited on a sapphire substrate which has been washed in advance by MOCVD to form an LED as a light emitting element. A sapphire substrate is placed in a reaction vessel of an MOCVD apparatus, and baked at 800 ° C. while flowing hydrogen gas. Next, a TMG (trimethyl gallium) gas as a source gas, a hydrogen gas as a nitrogen gas and a carrier gas are flown, and GaN as a buffer layer having a thickness of 150 is formed on a sapphire substrate at a substrate temperature of 550 ° C.
The film is formed by Å.

【0024】バッファ層を成膜後、原料ガスの流入を止
め成膜温度を1050℃に上げて、原料ガスとしてTM
Gガス、窒素ガス及びキャリアガスとして水素ガスを流
しノンドープのn型GaNを厚さ1.5μmで成膜させ
る。n型GaN上にn型電極を形成させるn型GaN層
を成膜させる。成膜温度を維持させたまま、原料ガスと
してTMGガス、窒素ガス、キャリアガスとして水素ガ
ス及びシランガスを流しn+型GaNを厚さ2.3μm
で成膜させる。成膜温度を維持させたまま、n+型Ga
N上に原料ガスとしてTMGガス、窒素ガス及びキャリ
アガスとして水素ガスを流し、ノンドープのGaNとS
iドープのGaNを20周期で成膜させたn型多層膜を
形成させる。なお、GaN層の不純物濃度が異なる変調
ドープとしてある。
After the formation of the buffer layer, the flow of the raw material gas is stopped, the film forming temperature is raised to 1050 ° C., and TM is used as the raw material gas.
A non-doped n-type GaN is formed to a thickness of 1.5 μm by flowing a hydrogen gas as a G gas, a nitrogen gas and a carrier gas. An n-type GaN layer for forming an n-type electrode is formed on the n-type GaN. While maintaining the film forming temperature, a TMG gas and a nitrogen gas as source gases, and a hydrogen gas and a silane gas as a carrier gas are caused to flow, and n + -type GaN is 2.3 μm in thickness
To form a film. While maintaining the film forming temperature, n + Ga
A TMG gas as a source gas, a nitrogen gas and a hydrogen gas as a carrier gas are flowed over N, and undoped GaN and S
An n-type multilayer film in which i-doped GaN is formed in 20 cycles is formed. Note that modulation doping is performed in which the impurity concentration of the GaN layer is different.

【0025】続いて、変調ドープしたGaN層上には活
性層としてAlInGaNを形成する。具体的には、成
膜温度を800℃にまで下げる。原料ガスとしてTMA
(トリメチルアルミニウム)ガス、TMI(トリメチル
インジウム)ガス、TMGガス、窒素ガス及びキャリア
ガスとして水素ガスを流し、活性層を形成させる。
Subsequently, AlInGaN is formed on the modulation-doped GaN layer as an active layer. Specifically, the film forming temperature is lowered to 800 ° C. TMA as raw material gas
An active layer is formed by flowing (trimethylaluminum) gas, TMI (trimethylindium) gas, TMG gas, nitrogen gas and hydrogen gas as carrier gas.

【0026】次に、活性層上には、p型クラッド層とし
て厚さが40ÅであるMgドープのAlGaNと厚さが
25ÅであるMgドープのInGaNを5回繰り返した
超格子p型クラッド層を形成させる。より具体的には、
成膜温度を1050℃に維持したまま、原料ガスとして
TMGガス、TMA(トリメチルアルミニウム)ガス、
窒素ガス、キャリアガスとして水素ガス及びp型ドーパ
ントしてCp2Mg(シクロペンタジエニルマグネシウ
ム)ガスを導入してp型クラッド層を成膜させる。
Next, on the active layer, a superlattice p-type clad layer in which Mg-doped AlGaN having a thickness of 40 ° and Mg-doped InGaN having a thickness of 25 ° are repeated five times is formed as a p-type clad layer. Let it form. More specifically,
While maintaining the film formation temperature at 1050 ° C., TMG gas, TMA (trimethylaluminum) gas,
A p-type clad layer is formed by introducing a nitrogen gas, a hydrogen gas as a carrier gas and a Cp 2 Mg (cyclopentadienyl magnesium) gas as a p-type dopant.

【0027】最後に成膜温度を1050℃に維持したま
ま原料ガスをTMGガス、窒素ガス、キャリアガスとし
て水素ガス及び不純物ガスとしてCp2Mgを流しp型
コンタクト層としてMgドープのGaNを成膜させる。
窒化物半導体ウエハを成膜後、RIEによりn型コンタ
クト層までが一部露出できるように活性層などを除去す
る。その後、p型及びn型の各コンタクト層にスパッタ
リングを用いて電極を形成させる。窒化物半導体ウエハ
をスクライブして発光素子として複数のLEDチップを
形成させる。こうしてサファイア基板上に量子井戸構造
の活性層が形成されダブルへテロ構造となる窒化物半導
体である発光素子が形成される。発光層となる活性層は
Gaを含む窒化物半導体の紫外線が発光可能な発光素子
である。この発光素子を利用して図3の如き、発光ダイ
オードを形成させる。
Finally, while maintaining the film formation temperature at 1050 ° C., the source gas is TMG gas, nitrogen gas, hydrogen gas as the carrier gas and Cp 2 Mg as the impurity gas, and Mg-doped GaN is formed as the p-type contact layer. Let it.
After forming the nitride semiconductor wafer, the active layer and the like are removed by RIE so that the n-type contact layer can be partially exposed. Thereafter, an electrode is formed on each of the p-type and n-type contact layers by using sputtering. A plurality of LED chips are formed as light emitting elements by scribing the nitride semiconductor wafer. Thus, an active layer having a quantum well structure is formed on the sapphire substrate, and a light emitting element which is a nitride semiconductor having a double hetero structure is formed. The active layer serving as a light emitting layer is a light emitting element capable of emitting ultraviolet light of a nitride semiconductor containing Ga. A light emitting diode is formed using this light emitting element as shown in FIG.

【0028】図3は本発明の一実施例の形態であるキャ
ンタイプパッケージの発光ダイオードを示す模式図であ
る。上記で得られたLEDチップ31を、銀メッキを施
したステム33の収納部に銀ペースト36で接合する。
次にステムの収納部周縁のフラット部にnpn接合を有
しn型基板であるトリガダイオードチップ32を銀ペー
スト36で接合する。この場合、ステムをカソード側と
すると共にインナーリードをアノード側としている。よ
り具体的には、インナーリード33aとLEDチップ3
1のp側取出電極(アノード側)を、またマウントリー
ド33bとLEDチップ31のn側取出電極(カソード
側)を金線35でワイヤーボンディングにより接続す
る。ステムのインナーリード33aは、ステム33の収
納部及びマウントリード33bとは電気的に絶縁されて
いる。次にトリガダイオードの上面となるn側取出電極
とインナーリード33aを金線35でワイヤーボンディ
ングにより接続する。
FIG. 3 is a schematic view showing a light emitting diode of a can type package according to an embodiment of the present invention. The LED chip 31 obtained as described above is joined to the accommodation portion of the silver-plated stem 33 with a silver paste 36.
Next, the trigger diode chip 32 which has an npn junction and is an n-type substrate at the flat portion of the periphery of the storage portion of the stem is joined with a silver paste 36. In this case, the stem is on the cathode side and the inner lead is on the anode side. More specifically, the inner lead 33a and the LED chip 3
No. 1 p-side extraction electrode (anode side), and the mount lead 33b and the n-side extraction electrode (cathode side) of the LED chip 31 are connected by a gold wire 35 by wire bonding. The inner lead 33a of the stem is electrically insulated from the storage part of the stem 33 and the mount lead 33b. Next, the n-side extraction electrode serving as the upper surface of the trigger diode and the inner lead 33a are connected by wire bonding with a gold wire 35.

【0029】最後に、N2雰囲気中でキャップ34とス
テム33のフランジ部を抵抗溶接により溶着封止するこ
とにより、マウントリード33bをカソード、インナー
リード33aをアノードとし、トリガダイオードチップ
32をLEDチップ31に対して並列に接続した発光ダ
イオードが形成できる。
Finally, the cap 34 and the flange of the stem 33 are welded and sealed by resistance welding in an N 2 atmosphere, so that the mount lead 33b is used as a cathode, the inner lead 33a is used as an anode, and the trigger diode chip 32 is used as an LED chip. A light-emitting diode connected in parallel to 31 can be formed.

【0030】こうして得られた発光ダイオードの耐電圧
を評価する。評価に用いた装置の試験回路を図6に示
す。電源Vの仕様は最大電圧3kV、最大電流3mAの
直流電圧とし、試験条件はコンデンサC容量を200p
F、抵抗Rを0Ωとした。なお、コンデンサCは試験電
圧に充分耐えられるものとし、切替スイッチSは絶縁抵
抗が高く、接触抵抗が低く、かつチャタリングのないも
のとした。また、試験装置と供試品との配線は極力短く
し、浮遊容量はコンデンサC容量の5%以下とした。試
験方法は、装置の切替スイッチSを電源V側にし、試験
電圧をコンデンサCに充電する。切替スイッチSを供試
品側にして放電させる。
The withstand voltage of the light emitting diode thus obtained is evaluated. FIG. 6 shows a test circuit of the device used for the evaluation. The specification of the power supply V is a DC voltage with a maximum voltage of 3 kV and a maximum current of 3 mA.
F and the resistance R were set to 0Ω. The capacitor C was designed to withstand the test voltage sufficiently, and the changeover switch S was designed to have high insulation resistance, low contact resistance and no chattering. The wiring between the test apparatus and the test sample was made as short as possible, and the stray capacitance was set to 5% or less of the capacitance of the capacitor C. In the test method, the switch S of the device is set to the power supply V side, and the test voltage is charged in the capacitor C. The changeover switch S is set to the sample side to discharge.

【0031】次に試験電圧の極性を変えて同じ操作を繰
り返す。試験電圧は100Vステップで、最大2.5k
Vまで設定した。本実施例で得られた発光ダイオードの
耐電圧試験評価結果は、順方向、逆方向共に2.5kV
に耐えることができる。即ち、LEDチップは半導体保
護素子を加えないときと同様に駆動させることができる
と共に、定格電圧以上においてはトリガダイオードの降
伏電圧で一定となる。 [実施例2]図4は本発明の一例である表面実装タイプ
の発光ダイオードの模式図である。図4の上図は正面図
で、下図は断面図である。この発光ダイオードは、窒化
物半導体からなるLEDチップを用いている。窒化物半
導体は、MOCVD法を用いて予め洗浄したサファイア
基板上に成膜させる。MOCVD装置の反応容器内にサ
ファイア基板を配置させて水素ガスを流しながら800
℃でベーキングした。次に、原料ガスとしてTMG(ト
リメチルガリウム)ガス、窒素ガス及びキャリアガスと
して水素ガスを流し、基板温度550℃でサファイア基
板上にバッファ層としてGaNを厚さ150Åで成膜さ
せた。
Next, the same operation is repeated while changing the polarity of the test voltage. Test voltage is 100V step, maximum 2.5k
V was set. The evaluation result of the withstand voltage test of the light emitting diode obtained in this example is 2.5 kV in both the forward and reverse directions.
Can withstand. That is, the LED chip can be driven in the same manner as when no semiconductor protection element is added, and becomes constant at the breakdown voltage of the trigger diode above the rated voltage. [Embodiment 2] FIG. 4 is a schematic view of a surface mount type light emitting diode as an example of the present invention. 4 is a front view, and the lower figure is a cross-sectional view. This light emitting diode uses an LED chip made of a nitride semiconductor. The nitride semiconductor is formed on a sapphire substrate that has been cleaned in advance by using the MOCVD method. The sapphire substrate is placed in the reaction vessel of the MOCVD apparatus, and the hydrogen gas is flowed for 800.
Baking at ℃. Next, TMG (trimethyl gallium) gas as a source gas, hydrogen gas as a nitrogen gas and a carrier gas were flown, and GaN was formed as a buffer layer to a thickness of 150 ° on a sapphire substrate at a substrate temperature of 550 ° C.

【0032】バッファ層を成膜後、原料ガスの流入を止
め成膜温度を1050℃に上げて、原料ガスとしてTM
Gガス、窒素ガス及びキャリアガスとして水素ガスを流
しノンドープのn型GaNを厚さ1.5μmで成膜させ
た。続いて、n型GaN上にn型電極を形成させるn型
コンタクト層としてn型GaN層を成膜させる。具体的
には、成膜温度を維持させたまま、原料ガスとしてTM
Gガス、窒素ガス、キャリアガスとして水素ガス及びシ
ランガスを流しn+型GaNを厚さ2.3μmで成膜さ
せる。次に成膜温度を維持させたまま、n+型GaN上
に原料ガスとしてTMGガス、窒素ガス及びキャリアガ
スとして水素ガスを流しノンドープのGaNとSiドー
プのGaNを20周期で成膜させる多層膜を形成する。
なお、GaN層の不純物濃度が異なる変調ドープとして
ある。
After the formation of the buffer layer, the flow of the raw material gas is stopped, the film forming temperature is raised to 1050 ° C., and TM is used as the raw material gas.
A non-doped n-type GaN having a thickness of 1.5 μm was formed by flowing a hydrogen gas as a G gas, a nitrogen gas and a carrier gas. Subsequently, an n-type GaN layer is formed as an n-type contact layer for forming an n-type electrode on the n-type GaN. Specifically, TM is used as a source gas while maintaining the film forming temperature.
G + gas, nitrogen gas, and hydrogen gas and silane gas as a carrier gas are flowed to form an n + -type GaN film having a thickness of 2.3 μm. Next, while maintaining the film formation temperature, a multi-layered film is formed by flowing TMG gas as a source gas, nitrogen gas and hydrogen gas as a carrier gas on n + -type GaN to form non-doped GaN and Si-doped GaN in 20 cycles. To form
Note that modulation doping is performed in which the impurity concentration of the GaN layer is different.

【0033】続いて、変調ドープしたGaN層上には活
性層として250ÅのGaNと厚さ30ÅのInGaN
を6周期繰り返した多重量子井戸構造であり、両端がG
aNである活性層を構成する。具体的には、成膜温度を
1050℃に維持したまま、変調ドープしたGaN層上
に原料ガスとしてTMG、窒素ガス及びキャリアガスと
して水素ガスを流しノンドープのGaNを30Åで成膜
させる。続いて、一旦キャリアガスだけを流しながら、
成膜温度を800℃にまで下げる。温度が一定した後
に、再び原料ガスとしてTMI(トリメチルインジウ
ム)ガス、TMGガス、窒素ガス及びキャリアガスとし
て水素ガスを流し、ノンドープのInGaNを250Å
で成膜させる。これを、6周期繰り返した後、最後に成
膜温度を1050℃にし、原料ガスとしてTMG、窒素
ガス及びキャリアガスとして水素ガスを流しノンドープ
のGaNを30Åで成膜させ活性層を形成させる。
Subsequently, on the modulation-doped GaN layer, 250 ° GaN and 30 ° thick InGaN were formed as active layers.
Are repeated six times, and the both ends are G
An active layer of aN is formed. Specifically, while maintaining the film formation temperature at 1050 ° C., TMG as a source gas, hydrogen gas as a nitrogen gas and a carrier gas are flowed on the modulation-doped GaN layer to form a non-doped GaN film at 30 °. Next, while flowing only the carrier gas,
The film forming temperature is lowered to 800 ° C. After the temperature is stabilized, a TMI (trimethyl indium) gas, a TMG gas, a nitrogen gas, and a hydrogen gas as a carrier gas are flowed again as source gases, and non-doped InGaN is deposited at 250 ° C.
To form a film. After repeating this for 6 cycles, finally, the film formation temperature is set to 1050 ° C., TMG as a source gas, hydrogen gas as a nitrogen gas and a carrier gas are flown, and non-doped GaN is formed at 30 ° to form an active layer.

【0034】次に、活性層上には、p型クラッド層とし
て厚さが40ÅであるMgドープのAlGaNと厚さが
25ÅであるMgドープのInGaNを5回繰り返した
超格子p型クラッド層を形成させる。成膜温度を105
0℃に維持したまま、原料ガスとしてTMGガス、TM
A(トリメチルアルミニウム)ガス、窒素ガス、キャリ
アガスとして水素ガス及びp型ドーパントしてCp2
g(シクロペンタジエニルマグネシウム)ガスを導入し
てp型AlGaNを40Åで成膜させる。
Next, a superlattice p-type cladding layer in which Mg-doped AlGaN having a thickness of 40 ° and Mg-doped InGaN having a thickness of 25 ° are repeated five times is formed on the active layer as a p-type cladding layer. Let it form. Film forming temperature 105
While maintaining at 0 ° C., TMG gas, TM
A (trimethylaluminum) gas, nitrogen gas, hydrogen gas as carrier gas and Cp 2 M as p-type dopant
g (cyclopentadienyl magnesium) gas is introduced to form a p-type AlGaN film at 40 °.

【0035】最後に成膜温度を1050℃に維持したま
ま原料ガスをTMGガス、窒素ガス、キャリアガスとし
て水素ガス及び不純物ガスとしてCp2Mgを流しp型
コンタクト層としてMgドープのGaNを成膜させる。
窒化物半導体ウエハを成膜後、RIEによりn型コンタ
クト層までが一部露出できるように活性層などを除去す
る。その後、p型及びn型の各コンタクト層にスパッタ
リングを用いて電極を形成させる。窒化物半導体ウエハ
をスクライブして各LEDチップを形成させる。こうし
てサファイア基板上に多重量子井戸構造の活性層が形成
されダブルへテロ構造となる窒化物半導体である発光素
子が形成される。発光層となる活性層はGaを含む窒化
物半導体の青色が発光可能な発光素子である。この発光
素子を利用して図4の如き、白色系が発光可能な発光ダ
イオードを形成させる。
Finally, while maintaining the film formation temperature at 1050 ° C., TMG gas, nitrogen gas, hydrogen gas as a carrier gas, and Cp 2 Mg as an impurity gas are flowed, and Mg-doped GaN is formed as a p-type contact layer. Let it.
After forming the nitride semiconductor wafer, the active layer and the like are removed by RIE so that the n-type contact layer can be partially exposed. Thereafter, an electrode is formed on each of the p-type and n-type contact layers by using sputtering. Each LED chip is formed by scribing the nitride semiconductor wafer. Thus, an active layer having a multiple quantum well structure is formed on the sapphire substrate, and a light emitting device which is a nitride semiconductor having a double hetero structure is formed. The active layer serving as a light emitting layer is a nitride semiconductor containing Ga which is capable of emitting blue light. By using this light emitting element, a light emitting diode capable of emitting white light is formed as shown in FIG.

【0036】まず、銀メッキした銅製リードフレーム4
1を打ち抜きにより形成し、そのリードフレーム41に
射出成形法により発光ダイオードの外枠となるパッケー
ジ42を形成する。次に、窒化ガリウム系化合物半導体
であるLEDチップ43を、プラスチックパッケージ4
2収納部のリードフレーム41露出部にエポキシ樹脂4
6で接合する。さらに、パッケージ42のリード電極4
1上にnpn接合を持ったn基板のトランジスターチッ
プ44を銀ペースト47で接合する。パッケージ42の
LEDチップ43を接合したリードフレーム41とトラ
ンジスターチップ44を接合したリード電極41はパッ
ケージ材料により電気的に絶縁されている。LEDチッ
プ43を接合したリード電極41とLEDチップ43の
n側取出電極(カソード側)を、またトランジスターチ
ップ44の表面電極と他方のリード電極41とを金線に
よりワイヤボンディングさせる。同様に、LEDチップ
43のp側取出電極(アノード側)を金線45でワイヤ
ーボンディングにより接続する。
First, a silver-plated copper lead frame 4
1 is formed by punching, and a package 42 serving as an outer frame of the light emitting diode is formed on the lead frame 41 by an injection molding method. Next, the LED chip 43, which is a gallium nitride-based compound semiconductor, is placed in a plastic package 4
2 epoxy resin 4 on the exposed part of the lead frame 41
Join at 6. Further, the lead electrode 4 of the package 42
An n-substrate transistor chip 44 having an npn junction on 1 is joined with a silver paste 47. The lead frame 41 joined to the LED chip 43 of the package 42 and the lead electrode 41 joined to the transistor chip 44 are electrically insulated by the package material. The lead electrode 41 to which the LED chip 43 is bonded and the n-side extraction electrode (cathode side) of the LED chip 43, and the surface electrode of the transistor chip 44 and the other lead electrode 41 are wire-bonded with a gold wire. Similarly, the p-side extraction electrode (anode side) of the LED chip 43 is connected to the gold wire 45 by wire bonding.

【0037】次に、パッケージ42上に射出成形により
青色光を吸収して補色となる光を発光可能な蛍光体とし
てYAG:Ceが含有された透光性エポキシ樹脂をLE
Dチップ及びトランジスタダイオード上に形成させる。
パッケージ42外枠から出たリードフレーム41を最適
形状に切断し、最後にそのリードをプラスチックパッケ
ージ42外枠に沿うように折り曲げる。以上により、L
EDチップ43に対してトランジスターチップ44を並
列に接続した面実装タイプの白色発光ダイオードを形成
した。
Next, a transparent epoxy resin containing YAG: Ce as a phosphor capable of absorbing blue light and emitting light of a complementary color by injection molding on the package 42 is LE.
It is formed on a D chip and a transistor diode.
The lead frame 41 protruding from the outer frame of the package 42 is cut into an optimum shape, and finally the lead is bent along the outer frame of the plastic package 42. From the above, L
A surface-mount type white light-emitting diode in which a transistor chip 44 was connected in parallel with the ED chip 43 was formed.

【0038】こうして得られた本実施例の発光ダイオー
ドにおいて、実施例1と同様の方法で耐電圧を評価した
結果、実施例1同様、順方向、逆方向共に2.5kVに
耐えることまで確認した。即ち、LEDチップは半導体
保護素子を加えないときと同様に駆動させることができ
ると共に定格電圧以上においてはトランジスターの降伏
電圧で一定となる。なお、ツェナーダイオードをAgペ
ーストでダイボンドすると、Agはアノード側からカソ
ード側に向かってマイグレーションする傾向が高いた
め、並列接続させたLEDチップ或いはツェナーダイオ
ードに駆動に伴いAgがマイグレーションして短絡する
場合がある。しかしながら、本発明の半導体保護素子を
利用した場合、LEDチップとトランジスタダイオード
とをリード電極上で同極性で接続させることができるた
め上述のような問題を回避することができる。さらに、
この発光ダイオードを用いてダイナミック駆動させるマ
トリックス状のLEDディスプレイに利用した場合、実
質的に点灯する発光ダイオードをなくすことができる。 [実施例3]図5は、砲弾型タイプの発光ダイオード断
面図である。まず、銀メッキした銅製リードフレーム5
1を打ち抜き及び押圧により形成する。形成されたリー
ドフレーム51は、マウントリード51aの先端にLE
Dチップ52収納部であるカップと、カップ下部にトリ
ガダイオードチップ53を接合可能な平坦部を有する。
With respect to the thus obtained light emitting diode of this example, the withstand voltage was evaluated by the same method as in Example 1. As a result, as in Example 1, it was confirmed that the light emitting diode withstands 2.5 kV in both the forward and reverse directions. . That is, the LED chip can be driven in the same manner as when no semiconductor protection element is added, and becomes constant at the breakdown voltage of the transistor above the rated voltage. When a Zener diode is die-bonded with an Ag paste, Ag tends to migrate from the anode side to the cathode side. Therefore, there is a case where Ag migrates to the LED chip or the Zener diode connected in parallel with driving and short-circuits. is there. However, when the semiconductor protection element of the present invention is used, the above-mentioned problem can be avoided because the LED chip and the transistor diode can be connected with the same polarity on the lead electrode. further,
When the LED is used in a matrix LED display that is dynamically driven by using the light emitting diode, the light emitting diode that is substantially turned on can be eliminated. [Embodiment 3] Fig. 5 is a sectional view of a light emitting diode of a shell type. First, a silver-plated copper lead frame 5
1 is formed by punching and pressing. The formed lead frame 51 is provided with LE at the tip of the mount lead 51a.
It has a cup which is a storage portion for the D chip 52, and a flat portion below the cup where the trigger diode chip 53 can be joined.

【0039】リードフレーム51の収納部に窒化ガリウ
ム系化合物半導体であるLEDチップ52をエポキシ樹
脂56によりダイボンドする。続いて、LEDチップか
らの放射光がトリガダイオードによって吸収されること
を防止するためにカップ底面のリードフレーム間に配置
させる。即ち、図5に示すようにSMDトリガダイオー
ドチップ53をインナーリード51bとマウントリード
51a間に溶接により接合する。SMDトリガダイオー
ドはカップによって実質上保護されるLEDチップと異
なり、後に形成させる封止樹脂の収縮などによる影響を
受けやすいため、強固に接合させることができる溶接に
よって接合させてある。
An LED chip 52, which is a gallium nitride-based compound semiconductor, is die-bonded to a storage portion of the lead frame 51 with an epoxy resin 56. Subsequently, in order to prevent the emitted light from the LED chip from being absorbed by the trigger diode, it is arranged between the lead frames on the bottom surface of the cup. That is, as shown in FIG. 5, the SMD trigger diode chip 53 is joined between the inner lead 51b and the mount lead 51a by welding. Unlike an LED chip that is substantially protected by a cup, the SMD trigger diode is easily affected by shrinkage of a sealing resin to be formed later, and is thus joined by welding that can be firmly joined.

【0040】インナーリード51bとLEDチップ52
のn側取出電極(カソード側)を、またマウントリード
51aとLEDチップ52のp側取出電極(アノード
側)を金線54でそれぞれワイヤーボンディングさせ
る。インナーリード51bは、マウントリード51aと
電気的に絶縁されている。
Inner lead 51b and LED chip 52
And the mount lead 51a and the p-side extraction electrode (anode side) of the LED chip 52 are wire-bonded with a gold wire 54, respectively. The inner lead 51b is electrically insulated from the mount lead 51a.

【0041】LEDチップ52及びSMDトリガダイオ
ードチップ54を外部応力、水分及び塵芥などから保護
し、かつ適切な配光特性を得る目的で、光透過性に優れ
たエポキシ樹脂でモールドする。モールド部材である封
止樹脂は、エポキシ樹脂を入れた砲弾型型枠となるキャ
ビティ内にLEDチップ及びSMDトリガダイオードチ
ップまで樹脂封止できるようにリードフレームを挿入
し、加熱硬化させることで形成できる。以上により、ト
リガダイオードチップ53をLEDチップ52に対して
逆並列に接続した砲弾型タイプの発光ダイオードを形成
した。
For the purpose of protecting the LED chip 52 and the SMD trigger diode chip 54 from external stress, moisture, dust and the like, and obtaining appropriate light distribution characteristics, they are molded with an epoxy resin having excellent light transmittance. The sealing resin, which is a molding member, can be formed by inserting a lead frame into a cavity serving as a shell-shaped mold frame containing epoxy resin so that the LED chip and the SMD trigger diode chip can be resin-sealed, and then heat-cured. . As described above, a bullet-type light emitting diode in which the trigger diode chip 53 is connected in antiparallel to the LED chip 52 is formed.

【0042】こうして得られた本実施例の発光ダイオー
ドにおいて、実施例1と同様の方法で耐電圧を評価した
結果、実施例1同様、順方向、逆方向共に2.5kVに
耐えることまで確認した。即ち、LEDチップは半導体
保護素子を加えないときと同様に駆動させることができ
ると共に定格電圧以上においてはトリガダイオードの降
伏電圧で一定となる。
With respect to the thus obtained light emitting diode of this example, the withstand voltage was evaluated by the same method as in Example 1. As a result, as in Example 1, it was confirmed that the light emitting diode could withstand 2.5 kV in both the forward and reverse directions. . That is, the LED chip can be driven in the same manner as when no semiconductor protection element is added, and becomes constant at the breakdown voltage of the trigger diode above the rated voltage.

【0043】[0043]

【発明の効果】以上説明したように、本発明によればL
EDチップと特定の関係を満たした半導体保護素子をL
EDチップに対して並列に接続することにより、静電気
やサージ電圧から保護され、且つLEDチップ固有の特
性を損なうことのない発光ダイオードを得ることができ
る。
As described above, according to the present invention, L
A semiconductor protection element that satisfies a specific relationship with the ED chip is L
By connecting in parallel to the ED chip, it is possible to obtain a light emitting diode that is protected from static electricity and surge voltage and does not impair the characteristics inherent to the LED chip.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の発光ダイオードの回路図を示す。FIG. 1 shows a circuit diagram of a light emitting diode of the present invention.

【図2】 トリガダイオード及びLEDチップの電圧電
流特性図を示す。
FIG. 2 shows a voltage-current characteristic diagram of a trigger diode and an LED chip.

【図3】 実施例1のキャンタイプパッケージである発
光ダイオードの斜視図を示す。
FIG. 3 is a perspective view of a light emitting diode which is a can type package according to the first embodiment.

【図4】 実施例2の面実装タイプである発光ダイオー
ドの正面図及び断面図を示す。
FIGS. 4A and 4B are a front view and a cross-sectional view of a surface-mount type light emitting diode according to a second embodiment. FIGS.

【図5】 実施例3の砲弾型樹脂モールドタイプである
発光ダイオードの模式的断面図を示す。
FIG. 5 is a schematic sectional view of a light emitting diode of a shell type resin mold type according to a third embodiment.

【図6】 耐電評価試験装置の回路図を示す。FIG. 6 shows a circuit diagram of a withstand voltage evaluation test apparatus.

【図7】 図7(A)は本発明と比較のために示す砲弾
型樹脂モールドタイプである発光ダイオードの模式的断
面図を示し、図7(B)はその等価回路を示す。
FIG. 7A is a schematic sectional view of a light emitting diode of a shell type resin mold type shown for comparison with the present invention, and FIG. 7B shows an equivalent circuit thereof.

【図8】 ツエナーダイオード及びLEDチップの電圧
電流特性図を示す。
FIG. 8 shows a voltage-current characteristic diagram of a Zener diode and an LED chip.

【図9】 発光ダイオードを用いたドットマトリックデ
ィスプレイの模式的部分回路図を示す。
FIG. 9 is a schematic partial circuit diagram of a dot matrix display using light emitting diodes.

【図10】 図10(A)はベースをオープンにしたn
pn型のトランジスタ及びLEDチップの電圧電流特性
図を示し、図10(B)はその等価回路を示す。
FIG. 10 (A) shows n with the base open.
FIG. 10B shows a voltage-current characteristic diagram of a pn-type transistor and an LED chip, and FIG. 10B shows an equivalent circuit thereof.

【符号の説明】[Explanation of symbols]

21、31、43、52・・・LEDチップ 22、32、44、53・・・トリガダイオードチップ 35、45、54・・・金線 41、51・・・リードフレーム 33・・・ステム 34・・・キャップ 42・・・プラスチックパッケージ 58・・・モールド樹脂 36、47・・・Agペースト 46、56・・・エポキシ樹脂 57・・・溶接による金属片 21, 31, 43, 52 ... LED chip 22, 32, 44, 53 ... trigger diode chip 35, 45, 54 ... gold wire 41, 51 ... lead frame 33 ... stem 34 ..Cap 42 ... Plastic package 58 ... Mold resin 36,47 ... Ag paste 46,56 ... Epoxy resin 57 ... Metal piece by welding

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 33/00 JICSTファイル(JOIS)────────────────────────────────────────────────── ─── Continued on front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 33/00 JICST file (JOIS)

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 少なくとも発光層がGaを含む窒化物半
導体である発光素子と、該発光素子を電気的に保護する
ための半導体保護素子とを有する発光ダイオードであっ
て、前記発光素子と並列接続された半導体保護素子は、
双方向とも発光素子の順方向電圧以上の電圧において導
通し、且つ負性抵抗特性を有することを特徴とする発光
ダイオード。
1. A light-emitting diode having a light-emitting element in which at least a light-emitting layer is a nitride semiconductor containing Ga and a semiconductor protection element for electrically protecting the light-emitting element, wherein the light-emitting diode is connected in parallel with the light-emitting element. Semiconductor protection element
In both directions, the voltage is higher than the light emitting element's forward voltage.
Through, and light-emitting diodes, characterized in Rukoto which have a negative resistance characteristic.
【請求項2】 少なくとも発光層にInとGaとを有す
る窒化物半導体を用いた発光素子と、該発光素子と並列
接続され発光素子を電気的に保護するための半導体保護
素子とを有する発光ダイオードであって、前記半導体保
護素子は、トリガダイオード、ベースをオープンにさせ
たトランジスタから選択される少なくとも1種を有する
ことを特徴とする発光ダイオード。
2. A light emitting diode comprising a light emitting element using a nitride semiconductor having at least a light emitting layer containing In and Ga, and a semiconductor protection element connected in parallel with the light emitting element for electrically protecting the light emitting element. a is, the semiconductor protection element, the trigger diode, light emitting diode, characterized in that it comprises at least one selected or transistor was opened base data al.
【請求項3】 前記発光素子がサファイア基板上に少な
くとも発光層がGaを含む窒化物半導体を介してp型及
びn型の窒化物半導体を有する請求項1或いは2に記載
の発光ダイオード。
3. The light-emitting diode according to claim 1, wherein the light-emitting element has p-type and n-type nitride semiconductors on a sapphire substrate with at least a light-emitting layer interposed through a nitride semiconductor containing Ga.
【請求項4】 請求項1或いは請求項2に記載の発光ダ
イオードをダイナミック駆動させるドットマトリックス
ディスプレイ。
4. A dot matrix display for dynamically driving the light emitting diode according to claim 1.
JP2000046647A 1999-02-25 2000-02-23 Light emitting diode and dot matrix display using the same Expired - Lifetime JP3348843B2 (en)

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JP11-47728 1999-02-25
JP2000046647A JP3348843B2 (en) 1999-02-25 2000-02-23 Light emitting diode and dot matrix display using the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004040661A2 (en) 2002-10-30 2004-05-13 Osram Opto Semiconductors Gmbh Method for producing a light source provided with electroluminescent diodes and comprising a luminescence conversion element
DE102004005269B4 (en) 2003-11-28 2005-09-29 Osram Opto Semiconductors Gmbh Light emitting semiconductor element has multilayers on a substrate with the pn junction insulatively separated into light emitting and protective diode sections
EP1687879B1 (en) * 2003-11-28 2008-12-10 OSRAM Opto Semiconductors GmbH Light-emitting semiconductor component comprising a protective diode
KR101139181B1 (en) 2004-01-30 2012-04-26 미쓰비시 가가꾸 가부시키가이샤 Led and led mounting structure
JP3994094B2 (en) * 2004-05-27 2007-10-17 ローム株式会社 Light emitting diode lamp
JP4789433B2 (en) * 2004-06-30 2011-10-12 三洋電機株式会社 LED display housing and LED display
DE102004036157B4 (en) 2004-07-26 2023-03-16 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Electromagnetic radiation emitting optoelectronic component and light module
JP4640794B2 (en) * 2005-05-19 2011-03-02 東洋電機製造株式会社 Matrix converter protection device
JP2007027357A (en) * 2005-07-15 2007-02-01 Showa Denko Kk Semiconductor light emitting device and substrate
JP2007329502A (en) * 2007-08-16 2007-12-20 Toshiba Corp Light-emitting device
JP4403199B2 (en) * 2008-11-17 2010-01-20 株式会社東芝 Light emitting device
JP2010135362A (en) * 2008-12-02 2010-06-17 Seiwa Electric Mfg Co Ltd Electric apparatus
JP2010182803A (en) * 2009-02-04 2010-08-19 Seiwa Electric Mfg Co Ltd Light-emitting apparatus
KR101920211B1 (en) 2011-12-19 2018-11-21 엘지이노텍 주식회사 Light emitting device array
JP2013179271A (en) * 2012-01-31 2013-09-09 Rohm Co Ltd Light emitting device and manufacturing method of the same
CN113748501A (en) * 2019-04-26 2021-12-03 罗姆股份有限公司 Semiconductor light emitting device

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