JP2000124391A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked multichip semiconductor device in which the loop height of a wire is suppressed and which is made thin by a method wherein the electrode pad of a semiconductor chip stacked in the upper part is connected to an internal electrode via an electrode pad in the lower part. SOLUTION: A first semiconductor chip 10 is fixed and bonded. A second semiconductor chip 11 is fixed and bonded onto the first semiconductor chip 10. A ball bump 17 is formed on a first bonding pad 12a. A second bonding pad 12b and the ball bump 17 are connected by a bonding wire 18 in such a way that a stitch bonding operation can be performed to the ball bump. In addition, the ball bump 17 and an internal electrode 14 are connected continuously by the bonding wire 18. The second bonding pad 12b and the internal electrode 14 are connected electrically via the first bonding pad 12a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of reducing the thickness of a package while superposing and molding a plurality of semiconductor chips.

[0002]

2. Description of the Related Art A transfer molding method for sealing a semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. Technology. A lead frame is used as a support material for the semiconductor chip 1. The semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pads of the semiconductor chip 1 and the leads 4 are connected to the wires 5.
It is manufactured by setting a lead frame in a mold having a desired outer shape, injecting an epoxy resin into the mold, and curing the lead frame.

On the other hand, the wave of miniaturization and weight reduction of various electronic devices is unavoidable, and semiconductor devices incorporated therein are required to have higher capacity, higher function, and higher integration.

In view of this, a technique of sealing a plurality of semiconductor chips in one package, which has existed as an idea (for example, Japanese Patent Application Laid-Open No. 55-1111517), has been attracting attention, and there has been a movement to realize it. Have been. That is, FIG.
As shown in FIG. 1, the first semiconductor chip 1
a, and the second semiconductor chip 1b is fixed on the first semiconductor chip 1a, and the corresponding bonding pads and the leads 4 are connected to the first and second bonding wires 5a, 5a.
b, and sealed with resin 2.

[0005]

[0007] Despite the increase in cost, there is no other choice but to integrate a plurality of chips, that is, there is an extremely strong demand for reduction in size and size. Therefore, there is a strong desire to store the package in a surface-mounted and thin package rather than a DIP-type package having a sufficient external dimension, and this has a greater merit as a whole.

However, the semiconductor chip 1 cannot be made thinner than a certain thickness due to the necessity of imparting mechanical strength. Therefore, there is a disadvantage that the package outer shape is increased by the number of stacked chips.

The second bonding wire 5b is
Avoiding contact with the first semiconductor chip 1a;
In order to avoid contact when crossing the bonding wire 5a, it is necessary to take a considerably large wire loop. Therefore, the height 6 of the wire loop tends to be large, and this has the disadvantage that the thickness of the entire package is increased and the reduction in thickness is hindered.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has a first semiconductor chip having a first bonding pad and a first semiconductor chip having a second bonding pad. A second semiconductor chip fixed on the first semiconductor chip, an internal electrode to be electrically connected to the first and second bonding pads, and a ball bump formed on the surface of the first bonding pad. A bonding wire that connects the ball bump from the second bonding pad and further connects the internal electrode continuously, and an insulating resin that covers the periphery of the first and second semiconductor chips. It is characterized by doing.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

First, FIG. 1A is a sectional view showing a semiconductor device of the present invention, and FIG. 1B is an enlarged sectional view of a main part.

In the figure, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. First and second semiconductor chips 1
Various active and passive circuit elements are formed on the silicon surfaces 0 and 11 in the previous process. On the surface of the first semiconductor chip 10, a first bonding pad 12a for external connection is formed. Similarly, a second bonding pad 12b is formed on the surface of the second semiconductor chip 11. Each bonding pad 1 on each chip surface
A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide-based insulating film is formed so as to cover 2a and 12b, and upper portions of bonding pads 12a and 12b are opened for electrical connection.

The insulating film substrate 13 is provided with the first
And a substrate that supports the second semiconductor chips 10 and 11. A conductive pattern is drawn on the surface of the film substrate 13 by a gold plating layer. The conductive pattern forms an internal electrode 14 for connecting each of the bonding pads 12a and 12b and the bump electrode 20 respectively.

The first semiconductor chip 10 is fixed on the island portion with an epoxy insulating adhesive 15. The second semiconductor chip 11 is the first semiconductor chip 1
No. 0 is fixed on the passivation film by an insulating epoxy adhesive 15. However, the second semiconductor chip 11 has a chip size that does not cover the first bonding pads 12a.

A ball bump 17 is formed above the first bonding pad 12a. The ball bump 17 is a bump electrode formed by using a gold wire ball bonding method and leaving only the gold ball portion. Then, the second bonding pad 12 b and the internal electrode 14 are connected to each other by a continuous bonding wire 18 via the ball bump 17. The bonding wire 18 is board-bonded (first-bonded) to the surface of the second electrode pad 12b, and the ball bump 1
7 is stitch-bonded at one end and the inner electrode 1
The four surfaces are again stitch-bonded and connected. The ball bump 17 is connected to the bonding wire 18 in the first direction.
When the second bond (stitch bond) is performed on the electrode pad 12a, the tip of the bonding tool serves as a buffer for preventing direct contact with the surface of the first semiconductor chip 10.

A plurality of bump electrodes 20 are formed on the film substrate 1.
3 is formed on the back surface side. The film substrate 13 is provided with a through hole (not shown), and the internal electrode 14 and the bump electrode 20 are connected through the through hole.

An epoxy thermosetting resin 21 covers the periphery of the first and second semiconductor chips 10 and 11. The thermosetting resin 21 covers the upper side of the film substrate 13 to form a package outer shape.

FIG. 2 shows steps in forming the bonding wire 18. Figure 2 (A) in advance
As shown in (1), the ball bump 17 is formed on the first electrode pad 12a, and the gold ball 33 is first bonded on the second electrode pad 12b using the capillary 30, and then the capillary 30 is mounted. The gold wire 32 is moved and stitch-bonded onto the ball bump 17. At this time, the gold wire 32 is continuously extended without cutting, and a second bond is performed on the surface of the internal electrode 14.

The first and second semiconductor chips 10, 11 are:
It is convenient to combine them with a memory device. For example,
EEPRO as the first and second semiconductor chips 10 and 11
When a semiconductor storage device such as M (flash memory) is used (first combination example), the storage capacity can be doubled, tripled, and so on in one package. Further, a case where a semiconductor memory device such as an EEPROM (flash memory) is formed on the first semiconductor chip 10 and a semiconductor memory device such as an SRAM is formed on the second semiconductor chip 11 is considered (second combination example). Can be

In either case, each chip has an I / O terminal for inputting / outputting data, an address terminal for specifying an address of data, and a chip enable terminal for permitting input / output of data. The pin arrangement of both chips is very similar. Therefore, the internal electrodes 14 for I / O terminals and address terminals of the first and second semiconductor chips 10 and 11 can be shared, and by applying an exclusive chip enable signal to each chip, It is possible to exclusively select the memory cells of one of the semiconductor chips. Further, with such a configuration, the first and second bonding pads 12a and 12b can be electrically connected.

The first and second bonding pads 12
In the case of a circuit configuration in which the first and second bonding pads 12a and 12b cannot be electrically connected to each other, the first bonding pads 12a are electrically independent to be dummy pads having no circuit function, and the ball bumps 17 are formed on the dummy pads. It is formed and connected by bonding wires 18 as shown in FIG.

FIG. 3 is a cross-sectional view for briefly explaining a method of manufacturing the ball bump 17.

Referring to FIG. 3A, a gold wire 32 having a diameter of about 20 to 30 .mu. Is inserted into a central hole 31 of a capillary 30, and a gold wire having a diameter of 60 to 80 .mu. The ball 33 is formed. This is moved above the first bonding pad 12a, and the capillary 30 is lowered, thereby bringing the gold ball 33 into contact with the surface of the electrode pad 12a and applying a constant pressure. At the same time, ultrasonic vibration is applied through the capillary 12 and heated to fix the gold ball 33 and the first bonding pad 12a.

Referring to FIG. 3B, the capillary 30 is raised vertically and then lowered vertically again. The distance 34 between the tip of the capillary 30 and the upper end (flat portion) of the gold ball 33 is 10
The capillary 30 is stopped at a position such that the distance becomes about 30 μm. The vicinity of the base of the gold ball 33 is not stored inside the capillary 30 and is exposed.

Referring to FIG. 3C, while maintaining the distance 34, the capillary 30 is horizontally moved by a distance exceeding two-thirds of the diameter of the gold wire 32. For example, when the diameter of the hole at the tip of the capillary 12 is 40 μm, 25 μm to 3 μm
Move by 5μ. The gold wire 32 is sheared halfway at the tip of the capillary 30, and a thin portion 35 is drawn to draw a thread.
It is barely continuous.

The distance 34 is important to provide shear in this step. If the distance 34 is too large, the gold wire 32 is only plastically deformed and a thin portion 35 cannot be formed. If the distance 34 is too small, the bonded gold balls 17 cannot be formed.
Will be peeled off. The tip of the capillary 30 is shown in FIG.
As shown in (D), near the base of the gold ball 33,
The gold wire 32 has the original diameter Φ without being affected by plastic deformation.
Control so that it is located immediately above the part where 1 was maintained.

FIG. 3E shows a state in which the capillary 12 is vertically moved up again. The state where the gold wire 32 and the gold ball 33 are continuous only in the thin portion 35 is shown.

Referring to FIG. 3F, the clamper (not shown), which has been released, is closed, the gold wire 32 is clamped, and the thin portion 35 is completely cut by pulling it upward. By such a process, the ball bump 17 is formed on the first bonding pad 12a.

In the semiconductor device of the present invention described above, the second bonding pad 12b is connected to the first bonding pad 12a, so that the distance between them is short, so that the loop length of the bonding wire 18 is reduced. It is possible. Therefore, the loop height 22 (FIG. 1) can be kept low. This is particularly effective when the difference in chip size between the first semiconductor chip 10 and the second semiconductor chip 11 is large. Further, a contact accident between the bonding wire 18 and the first semiconductor chip 10 can be avoided. Furthermore, since the crossing arrangement of the bonding wires is eliminated, an electrical short circuit between the two can be avoided.

[0029]

As described above, according to the present invention,
By stacking a plurality of semiconductor chips 10 and 11 in one package, there is an advantage that a product of high-density mounting can be provided according to a demand for reduction in size and size of electronic equipment.

Further, since the bonding wire 18 and the internal electrode 14 are connected via the first bonding pad 12a, there is an advantage that the length of the bonding wire 18 from the pad 12b to the pad 12a can be reduced.
As a result, the loop height 22 can be kept low, and there is an advantage that the thickness of the package can be reduced.

Then, the second bonding pad 12b
Since the wire is not directly wire-bonded to the internal electrode 14, the intersection of the bonding wires 18 is eliminated, so that an accident such as an electrical short circuit can be prevented, and the contact between the bonding wires 18 and the first semiconductor chip 10 can also be prevented.

Further, the number of stitch bonds to the internal electrode 14 is 1
Since only a book is required, the bonding area can be reduced, and the size of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining a conventional example.

Claims (4)

[Claims] A first bonding pad having a first bonding pad;
Semiconductor chip having a second bonding pad, a second semiconductor chip fixed on the first semiconductor chip, and an internal electrode to be electrically connected to the first and second bonding pads A ball bump formed on the surface of the first bonding pad; a bonding wire connecting the ball bump from the second bonding pad and further connecting the internal electrode continuously; An insulating resin covering the periphery of the second semiconductor chip. 2. The semiconductor device according to claim 1, wherein said first bonding pad is electrically dummy, and said second bonding pad is connected to said internal electrode via said first bonding pad. 2. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, wherein said first bonding pad and said second bonding pad have a common function. 4. The semiconductor device according to claim 1, wherein said first and second bonding wires are formed by ball bonding.