JP2013191738A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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JP2013191738A
JP2013191738A JP2012057215A JP2012057215A JP2013191738A JP 2013191738 A JP2013191738 A JP 2013191738A JP 2012057215 A JP2012057215 A JP 2012057215A JP 2012057215 A JP2012057215 A JP 2012057215A JP 2013191738 A JP2013191738 A JP 2013191738A
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metal wire
electrode pad
substrate
semiconductor chip
receiving surface
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Shogo Watanabe
昭吾 渡邉
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Toshiba Corp
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Toshiba Corp
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Priority to JP2012057215A priority Critical patent/JP2013191738A/en
Priority to TW101148519A priority patent/TW201338110A/en
Priority to CN2013100136613A priority patent/CN103311203A/en
Publication of JP2013191738A publication Critical patent/JP2013191738A/en
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing thickness of the device by suppressing loop height of a metal wire and capable of suppressing cost by suppressing the number of bonding steps.SOLUTION: A semiconductor device 1 includes a substrate 2, a semiconductor chip 3, electrode pads 5 and 6, and a metal wire 4. The semiconductor chip is stacked on the substrate by at least two stages. The electrode pad is formed at the substrate and the semiconductor chip. The metal wire electrically connects the electrode pads together. At one end of a metal wire 4a jointed to one electrode pad 6a among the electrode pads, a base part 8 in which a receiving surface 9 is formed is provided. The metal wire extends from a position shying the receiving surface toward other electrode pad 6b provided at a stage upper than the one electrode pad. The other end of other metal wire 4b whose one end is jointed to another electrode pad 5 provided at a stage lower than the one electrode pad is jointed to the receiving surface of the base part by stitch bonding.

Description

本発明の実施形態は、半導体装置およびその製造方法に関する。   Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

従来、配線層が形成された基板上にコントローラチップやメモリチップ等の半導体チップを載置した半導体装置が知られている。このような半導体装置では、基板上に設けられた電極パッドとチップ上に設けられた電極パッドとを、金属ワイヤで接続することで（以下、ボンディングともいう）、基板とチップとが互いに電気的に接続される。このような半導体装置では、装置自体の薄型化のために金属ワイヤのループ高さをより低く抑えることが望まれている。   Conventionally, a semiconductor device in which a semiconductor chip such as a controller chip or a memory chip is mounted on a substrate on which a wiring layer is formed is known. In such a semiconductor device, the electrode pad provided on the substrate and the electrode pad provided on the chip are connected by a metal wire (hereinafter also referred to as bonding), whereby the substrate and the chip are electrically connected to each other. Connected to. In such a semiconductor device, it is desired to keep the loop height of the metal wire lower in order to reduce the thickness of the device itself.

特開２００３−２４３４４１号公報JP 2003-243441 A

一つの実施形態は、金属ワイヤのループ高さを抑えて装置の薄型化を図るとともに、ボンディングの工程数を抑えてコストの抑制を図ることのできる半導体装置およびその製造方法を提供することを目的とする。   One embodiment aims to provide a semiconductor device capable of reducing the thickness of the device by suppressing the loop height of the metal wire and reducing the number of bonding steps, and a method for manufacturing the same. And

一つの実施形態によれば、基板と、半導体チップと、電極パッドと、金属ワイヤとを備える半導体装置が提供される。半導体チップは、基板上に少なくとも２段以上積層される。ここで基板上とは、基板の半導体チップ積層面側を上とした場合の上を指す。電極パッドは、基板および半導体チップに形成される。金属ワイヤは、電極パッド間を電気的に接続させる。電極パッドのうち一の電極パッドに接合された金属ワイヤの一端には、ステッチボンディングが可能な受け面が形成された基部が設けられる。基部の受け面をよけた位置から一の電極パッドよりも上段に設けられた他の電極パッドに向けて金属ワイヤが延びる。一の電極パッドよりも下段に設けられたさらに他の電極パッドに一端が接合された他の金属ワイヤの他端が、基部の受け面にステッチボンディングにより接合されている。電極パッドのうち最上段の電極パッドに接合された金属ワイヤの最上段の電極パッド側の一端は、最上段の電極パッド上に設けられたバンプに接続されている。   According to one embodiment, a semiconductor device including a substrate, a semiconductor chip, an electrode pad, and a metal wire is provided. The semiconductor chips are stacked on at least two stages on the substrate. Here, the term “on the substrate” refers to the case where the semiconductor chip lamination surface side of the substrate is the top. The electrode pad is formed on the substrate and the semiconductor chip. The metal wire electrically connects the electrode pads. One end of the metal wire bonded to one of the electrode pads is provided with a base portion on which a receiving surface capable of stitch bonding is formed. A metal wire extends from a position away from the receiving surface of the base toward another electrode pad provided on the upper stage than the one electrode pad. The other end of another metal wire having one end bonded to another electrode pad provided at a lower stage than the one electrode pad is bonded to the receiving surface of the base by stitch bonding. One end of the metal wire joined to the uppermost electrode pad among the electrode pads is connected to a bump provided on the uppermost electrode pad.

図１は、第１の実施の形態にかかる半導体装置の断面図である。FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. 図２は、図１に示すＡ部分を拡大した部分拡大断面図であって、ボンディングの手順を説明するための図である。FIG. 2 is a partial enlarged cross-sectional view in which the portion A shown in FIG. 1 is enlarged, and is a view for explaining a bonding procedure. 図３は、図１に示すＡ部分を拡大した部分拡大断面図であって、ボンディングの手順を説明するための図である。FIG. 3 is a partial enlarged cross-sectional view in which the portion A shown in FIG. 1 is enlarged, and is a view for explaining a bonding procedure. 図４は、図１に示すＡ部分を拡大した部分拡大断面図であって、ボンディングの手順を説明するための図である。FIG. 4 is a partially enlarged cross-sectional view in which the portion A shown in FIG. 1 is enlarged, and is a view for explaining a bonding procedure. 図５は、図４に示すＢ−Ｂ線に沿った矢視断面図である。5 is a cross-sectional view taken along the line BB shown in FIG. 図６は、図１に示すＡ部分を拡大した部分拡大断面図であって、ボンディングの手順を説明するための図である。FIG. 6 is a partially enlarged cross-sectional view in which the portion A shown in FIG. 1 is enlarged, and is a view for explaining a bonding procedure. 図７は、図６に示すＣ−Ｃ線に沿った矢視断面図である。FIG. 7 is a cross-sectional view taken along the line CC shown in FIG. 図８は、半導体装置の製造手順を説明するためのフローチャートである。FIG. 8 is a flowchart for explaining a manufacturing procedure of the semiconductor device. 図９は、比較例としての半導体装置の断面図である。FIG. 9 is a cross-sectional view of a semiconductor device as a comparative example.

以下に添付図面を参照して、実施の形態にかかる半導体装置およびその製造方法を詳細に説明する。なお、この実施の形態により本発明が限定されるものではない。   Exemplary embodiments of a semiconductor device and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

（第１の実施の形態）
図１は、第１の実施の形態にかかる半導体装置の断面図である。半導体装置１は、基板２、半導体チップ３、金属ワイヤ４を備える。基板２は、例えば絶縁性樹脂基板の内部や表面に配線層を設けたものであり、素子搭載基板と端子形成基板とを兼ねる。このような基板２として、ガラス−エポキシ樹脂やガラス−ＢＴ樹脂（ビスマレイミド・トリアジン樹脂）などを用いたプリント配線板が使用される。基板２の表面には、複数の電極パッド（基板側電極パッド（さらに他の電極パッド）５）が形成されている。 (First embodiment)
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. The semiconductor device 1 includes a substrate 2, a semiconductor chip 3, and a metal wire 4. The substrate 2 is, for example, provided with a wiring layer inside or on the surface of an insulating resin substrate, and serves as both an element mounting substrate and a terminal forming substrate. As such a substrate 2, a printed wiring board using glass-epoxy resin, glass-BT resin (bismaleimide / triazine resin) or the like is used. On the surface of the substrate 2, a plurality of electrode pads (substrate-side electrode pads (further other electrode pads) 5) are formed.

半導体チップ３は、基板２上に実装される半導体素子であり、例えばＤＲＡＭやＮＡＮＤフラッシュメモリなどをコントロールするためのコントローラチップや、ＤＲＡＭやＮＡＮＤフラッシュメモリなどの半導体メモリチップである。半導体チップ３の上面には、複数の電極パッド（チップ側電極パッド６）が形成されている。   The semiconductor chip 3 is a semiconductor element mounted on the substrate 2 and is, for example, a controller chip for controlling a DRAM or a NAND flash memory or a semiconductor memory chip such as a DRAM or a NAND flash memory. On the upper surface of the semiconductor chip 3, a plurality of electrode pads (chip-side electrode pads 6) are formed.

複数枚の半導体チップ３が基板２上に積層されている。本実施の形態では、２枚の半導体チップ３が積層された例を挙げて説明する。なお、以下の説明において、基板２に直接実装される半導体チップ３を下段側半導体チップ（一の半導体チップ）３ａともいい、下段側半導体チップ３ａの上段に積層された半導体チップ３を上段側半導体チップ（他の半導体チップ）３ｂともいう。   A plurality of semiconductor chips 3 are stacked on the substrate 2. In the present embodiment, an example in which two semiconductor chips 3 are stacked will be described. In the following description, the semiconductor chip 3 directly mounted on the substrate 2 is also referred to as a lower semiconductor chip (one semiconductor chip) 3a, and the semiconductor chip 3 stacked on the upper stage of the lower semiconductor chip 3a is the upper semiconductor chip. Also referred to as a chip (another semiconductor chip) 3b.

半導体チップ３は、熱硬化性樹脂等を用いた接着剤７によって基板２や下段側半導体チップ３ａに接着される。複数枚の半導体チップ３は、平面視において互いにずらして配置されて、階段状に積層されている。これにより、下段側半導体チップ３ａの上面の一部が、上段側半導体チップ３ｂに覆われずに露出する。この露出部分となる位置にチップ側電極パッド６が形成される。なお、以下の説明において、下段側半導体チップ３ａに形成されたチップ側電極パッド６を下段チップ側電極パッド（一の電極パッド）６ａともいい、上段側半導体チップ３ｂに形成されたチップ側電極パッド６を上段チップ側電極パッド（他の電極パッド）６ｂともいう。   The semiconductor chip 3 is bonded to the substrate 2 and the lower semiconductor chip 3a with an adhesive 7 using a thermosetting resin or the like. The plurality of semiconductor chips 3 are arranged so as to be shifted from each other in plan view, and are stacked in a staircase pattern. Thereby, a part of the upper surface of the lower semiconductor chip 3a is exposed without being covered by the upper semiconductor chip 3b. A chip-side electrode pad 6 is formed at a position to be the exposed portion. In the following description, the chip-side electrode pad 6 formed on the lower semiconductor chip 3a is also referred to as a lower chip-side electrode pad (one electrode pad) 6a, and the chip-side electrode pad formed on the upper semiconductor chip 3b. 6 is also referred to as an upper chip side electrode pad (another electrode pad) 6b.

金属ワイヤ４は、その両端部が電極パッド５，６に接合されて、電極パッド５，６同士を電気的に接続させる。金属ワイヤ４には、金等の金属が用いられている。なお、以下の説明において、下段チップ側電極パッド６ａと上段チップ側電極パッド６ｂとを電気的に接続させる金属ワイヤを上段金属ワイヤ４ａともいい、基板側電極パッド５と下段チップ側電極パッド６ａとを電気的に接続させる金属ワイヤを下段金属ワイヤ（他の金属ワイヤ）４ｂともいう。また、金属ワイヤ４を電極パッド５，６に接合させることをボンディングともいう。   Both ends of the metal wire 4 are bonded to the electrode pads 5 and 6 to electrically connect the electrode pads 5 and 6 to each other. A metal such as gold is used for the metal wire 4. In the following description, a metal wire that electrically connects the lower chip side electrode pad 6a and the upper chip side electrode pad 6b is also referred to as an upper metal wire 4a, and the substrate side electrode pad 5 and the lower chip side electrode pad 6a A metal wire for electrically connecting the two is also referred to as a lower metal wire (other metal wire) 4b. Bonding the metal wire 4 to the electrode pads 5 and 6 is also called bonding.

次に、図面を用いて半導体装置１の製造手順を詳細に説明する。図２、３、４、６は、図１に示すＡ部分を拡大した部分拡大断面図であって、ボンディングの手順を説明するための図である。図５は、図４に示すＢ−Ｂ線に沿った矢視断面図である。図７は、図６に示すＣ−Ｃ線に沿った矢視断面図である。図８は、半導体装置の製造手順を説明するためのフローチャートである。なお、図５、７では、キャピラリ１１の図示を省略している。   Next, the manufacturing procedure of the semiconductor device 1 will be described in detail with reference to the drawings. 2, 3, 4, and 6 are partial enlarged cross-sectional views in which the portion A shown in FIG. 1 is enlarged, and are diagrams for explaining a bonding procedure. 5 is a cross-sectional view taken along the line BB shown in FIG. FIG. 7 is a cross-sectional view taken along the line CC shown in FIG. FIG. 8 is a flowchart for explaining a manufacturing procedure of the semiconductor device. 5 and 7, illustration of the capillary 11 is omitted.

まず、基板２に半導体チップ３を実装する（ステップＳ１）。次に、上段側半導体チップ３ｂの上段チップ側電極パッド６ｂ上にバンプ１０を形成する（ステップＳ２）。バンプ１０は、最上段となる電極パッド（本実施の形態では上段チップ側電極パッド６ｂ）上に設けられて、金属ワイヤ４の下端と上段側半導体チップ３ｂの上面との間に所定の間隔Ｘ（図１も参照）を形成させる。この間隔Ｘが不足すると、金属ワイヤ４と上段側半導体チップ３ｂの上面とが接触してしまう場合がある。なお、バンプ１０の形成は、キャピラリ１１によって行われるが、その詳細な説明については省略する。   First, the semiconductor chip 3 is mounted on the substrate 2 (step S1). Next, the bump 10 is formed on the upper chip side electrode pad 6b of the upper semiconductor chip 3b (step S2). The bump 10 is provided on the uppermost electrode pad (in this embodiment, the upper chip side electrode pad 6b), and a predetermined distance X is provided between the lower end of the metal wire 4 and the upper surface of the upper semiconductor chip 3b. (See also FIG. 1). If the distance X is insufficient, the metal wire 4 may come into contact with the upper surface of the upper semiconductor chip 3b. The bumps 10 are formed by the capillaries 11, but detailed description thereof is omitted.

次に、下段側半導体チップ３ａの下段チップ側電極パッド６ａに、上段金属ワイヤ４ａの一端をファーストボンディングによって接合させる。図２に示すように、金属ワイヤ４は、キャピラリ１１に形成された貫通孔１１ｂを通して供給される。チップ側電極パッド６に接合する前の金属ワイヤ４の先端には、略球体状のボール部１２が形成されている。ボール部１２は、トーチ（図示せず）と金属ワイヤ４との間に電圧が印加されて生じるスパークによって、キャピラリ１１の先端から突出した金属ワイヤ４が溶融して形成される。また、金属ワイヤ４のボンディングは、キャピラリ１１によって金属ワイヤ４に荷重と超音波を加えることによって行われる。   Next, one end of the upper metal wire 4a is bonded to the lower chip side electrode pad 6a of the lower semiconductor chip 3a by first bonding. As shown in FIG. 2, the metal wire 4 is supplied through a through hole 11 b formed in the capillary 11. A substantially spherical ball portion 12 is formed at the tip of the metal wire 4 before being bonded to the chip-side electrode pad 6. The ball portion 12 is formed by melting the metal wire 4 protruding from the tip of the capillary 11 by a spark generated when a voltage is applied between the torch (not shown) and the metal wire 4. The bonding of the metal wire 4 is performed by applying a load and an ultrasonic wave to the metal wire 4 by the capillary 11.

まず、図３に示すように、キャピラリ１１によってボール部１２が下段チップ側電極パッド６ａに押しつけてつぶされることで（ステップＳ３）、下段チップ側電極パッド６ａへの上段金属ワイヤ４ａのボンディングが行われる。   First, as shown in FIG. 3, the ball portion 12 is pressed against the lower chip-side electrode pad 6a by the capillary 11 and crushed (step S3), thereby bonding the upper metal wire 4a to the lower chip-side electrode pad 6a. Is called.

次に、図４、５に示すように、上段金属ワイヤ４ａの一端に基部８と受け面９を形成する（ステップＳ４）。より具体的には、ステップＳ３においてボール部１２がつぶされて形成された基部８に、キャピラリ１１のフェイス部１１ａを押し当てて受け面９を形成する。   Next, as shown in FIGS. 4 and 5, a base 8 and a receiving surface 9 are formed at one end of the upper metal wire 4a (step S4). More specifically, the receiving part 9 is formed by pressing the face part 11a of the capillary 11 against the base part 8 formed by crushing the ball part 12 in step S3.

フェイス部１１ａを押し当てる際には、キャピラリ１１をセカンドボンディング地点方向、すなわち上段チップ側電極パッド６ｂ方向に移動させておく。これにより、フェイス部１１ａのうち上段チップ側電極パッド６ｂから離れた側となる部分が基部８に押し当てられる。   When pressing the face portion 11a, the capillary 11 is moved in the direction of the second bonding point, that is, in the direction of the upper chip side electrode pad 6b. As a result, a portion of the face portion 11 a that is away from the upper chip side electrode pad 6 b is pressed against the base portion 8.

フェイス部１１ａのうち上段チップ側電極パッド６ｂから離れた側となる部分を基部８に押し当てることで、図４、５に示すように、受け面９をよけた位置であって、セカンドボンディング地点方向（上段チップ側電極パッド６ｂ方向）となる位置から金属ワイヤ４が延びた状態とすることができる。   By pressing a portion of the face portion 11a on the side away from the upper chip-side electrode pad 6b against the base portion 8, as shown in FIGS. The metal wire 4 can be extended from a position in the direction (upper chip-side electrode pad 6b direction).

次に、上段金属ワイヤ４ａの他端を、上段チップ側電極パッド６ｂ上のバンプ１０に対してセカンドボンディングによって接合する（ステップＳ５）。バンプ１０へのボンディングは、一般的にステッチボンディングと呼ばれる手法を用いればよい。これにより、上段金属ワイヤ４ａによって、下段チップ側電極パッド６ａと上段チップ側電極パッド６ｂとが電気的に接続される。   Next, the other end of the upper metal wire 4a is joined to the bump 10 on the upper chip side electrode pad 6b by second bonding (step S5). The bonding to the bumps 10 may be performed using a technique generally called stitch bonding. Thereby, the lower chip side electrode pad 6a and the upper chip side electrode pad 6b are electrically connected by the upper metal wire 4a.

次に、下段金属ワイヤ４ｂの一端を基板側電極パッド５にファーストボンディングによって接合する（ステップＳ６）。基板側電極パッド５へのボンディングは、一般的にボールボンディングと呼ばれる手法を用いればよい。   Next, one end of the lower metal wire 4b is bonded to the substrate-side electrode pad 5 by first bonding (step S6). Bonding to the substrate-side electrode pad 5 may be performed using a technique generally called ball bonding.

次に、図６、７に示すように、下段金属ワイヤ４ｂの他端を、基部８に形成された受け面９にセカンドボンディングによって接合する（ステップＳ７）。受け面９へのボンディングは、一般的にステッチボンディングと呼ばれる手法を用いればよい。   Next, as shown in FIGS. 6 and 7, the other end of the lower metal wire 4b is joined to the receiving surface 9 formed on the base 8 by second bonding (step S7). The bonding to the receiving surface 9 may be performed using a technique generally called stitch bonding.

以上の工程により、半導体装置１が製造される。なお、ステップＳ７の後に、基板２の表面を樹脂で封止したり、ケースで覆ったりすることで、半導体装置１の外郭を構成してもよい。   The semiconductor device 1 is manufactured through the above steps. Note that after step S7, the outer surface of the semiconductor device 1 may be configured by sealing the surface of the substrate 2 with a resin or covering it with a case.

図９は、比較例としての半導体装置の断面図である。なお、上記半導体装置１と同様の構成については、同様の符号を付している。比較例として示す半導体装置５１では、上段金属ワイヤ５４ａおよび下段金属ワイヤ５４ｂの両方で、上記半導体装置１の下段金属ワイヤ４ｂと同様に、ボールボンディングによってファーストボンディングが行われ、ステッチボンディングによってセカンドボンディングが行われる。   FIG. 9 is a cross-sectional view of a semiconductor device as a comparative example. The same reference numerals are given to the same configurations as those of the semiconductor device 1. In the semiconductor device 51 shown as the comparative example, first bonding is performed by ball bonding and second bonding is performed by stitch bonding in the same manner as the lower metal wire 4b of the semiconductor device 1 in both the upper metal wire 54a and the lower metal wire 54b. Done.

また、下段金属ワイヤ５４ｂを先にボンディングしてから上段金属ワイヤ５４ａをボンディングしている。下段金属ワイヤ５４ｂのセカンドボンディングにおいて、ステッチボンディングを行うためには、下段金属ワイヤ５４ｂの下端と、下段側半導体チップ３ａの上面との間に所定の間隔Ｚが必要となる。この間隔Ｚが不足すると、下段金属ワイヤ５４ｂと下段側半導体チップ３ａの上面とが接触してしまう場合がある。   Further, the upper metal wire 54a is bonded after the lower metal wire 54b is bonded first. In the second bonding of the lower metal wire 54b, in order to perform stitch bonding, a predetermined interval Z is required between the lower end of the lower metal wire 54b and the upper surface of the lower semiconductor chip 3a. If the interval Z is insufficient, the lower metal wire 54b may come into contact with the upper surface of the lower semiconductor chip 3a.

十分な間隔Ｚを設けるために、半導体装置５１では、上段チップ側電極パッド６ｂ上だけでなく、下段チップ側電極パッド６ａ上にもバンプ６０が形成されている。そして、下段金属ワイヤ５４ｂがステッチボンディングされた下段チップ側電極パッド６ａに対して、上段金属ワイヤ５４ａがボールボンディングによって接合される。   In order to provide a sufficient distance Z, in the semiconductor device 51, the bumps 60 are formed not only on the upper chip side electrode pads 6b but also on the lower chip side electrode pads 6a. Then, the upper metal wire 54a is bonded to the lower chip side electrode pad 6a to which the lower metal wire 54b is stitch bonded by ball bonding.

そのため、バンプ６０の高さ分だけ、上段金属ワイヤ５４ａのループ高さが高くなってしまう。また、バンプ６０を形成するための工程が必要となるため、工数の増加によるコスト増加を招いてしまう。   Therefore, the loop height of the upper metal wire 54a is increased by the height of the bump 60. Further, since a process for forming the bump 60 is required, the cost is increased due to an increase in the number of steps.

一方、本実施の形態にかかる半導体装置１では、先に上段金属ワイヤ４ａを下段チップ側電極パッド６ａにボンディングし、基部８と受け面９を形成することで、バンプ６０を設けることなく、ステッチボンディングに必要な間隔Ｙ（図６も参照）を確保し、ステッチボンディングの対象となる面（受け面９）を設けることができる。   On the other hand, in the semiconductor device 1 according to the present embodiment, the upper metal wire 4a is first bonded to the lower chip side electrode pad 6a, and the base 8 and the receiving surface 9 are formed. A space Y (see also FIG. 6) necessary for bonding can be secured, and a surface (receiving surface 9) to be stitch bonded can be provided.

また、上段金属ワイヤ４ａは、平面視において受け面９をよけるとともに、セカンドボンディング地点方向となる位置から延びているので、ステッチボンディングを行う際にキャピラリ１１によってループをつぶされにくくすることができる。   Further, the upper metal wire 4a avoids the receiving surface 9 in a plan view and extends from a position that is in the direction of the second bonding point, so that the loop can be prevented from being crushed by the capillary 11 when performing stitch bonding. .

したがって、下段チップ側電極パッド６ａ上にバンプ６０を設けずに、上段金属ワイヤ４ａと下段金属ワイヤ４ｂをボンディングすることができるので、上段金属ワイヤ４ａのループ高さをバンプ６０の高さ分低く抑えることができる。これにより、半導体装置１自体の薄型化を図ることが可能となる。また、バンプ６０を設ける工程を減らすことができるので、工数の削減によるコストの抑制を図ることができる。   Therefore, the upper metal wire 4a and the lower metal wire 4b can be bonded without providing the bump 60 on the lower chip-side electrode pad 6a, so that the loop height of the upper metal wire 4a is reduced by the height of the bump 60. Can be suppressed. As a result, the semiconductor device 1 itself can be thinned. Moreover, since the process of providing the bump 60 can be reduced, the cost can be suppressed by reducing the number of man-hours.

なお、本実施の形態では、２枚の半導体チップ３が積層された例を挙げて説明しているが、３枚以上の半導体チップ３が積層されていても構わない。例えば、４枚の半導体チップが積層された４段構成の半導体装置であれば、基板側から１〜３段目の半導体チップの電極パッドでバンプの形成を省略することができる。   In this embodiment, an example in which two semiconductor chips 3 are stacked is described. However, three or more semiconductor chips 3 may be stacked. For example, in the case of a four-stage semiconductor device in which four semiconductor chips are stacked, the formation of bumps can be omitted with the electrode pads of the first to third semiconductor chips from the substrate side.

さらなる効果や変形例は、当業者によって容易に導き出すことができる。よって、本発明のより広範な態様は、以上のように表わしかつ記述した特定の詳細および代表的な実施形態に限定されるものではない。したがって、添付のクレームおよびその均等物によって定義される総括的な発明の概念の精神または範囲から逸脱することなく、様々な変更が可能である。   Further effects and modifications can be easily derived by those skilled in the art. Accordingly, the broader aspects of the present invention are not limited to the specific details and representative embodiments shown and described above. Accordingly, various modifications can be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

１ 半導体装置、２ 基板、３ 半導体チップ、３ａ 下段側半導体チップ（一の半導体チップ）、３ｂ 上段側半導体チップ（他の半導体チップ）、４ 金属ワイヤ、４ａ 上段金属ワイヤ、４ｂ 下段金属ワイヤ（他の金属ワイヤ）、５ 基板側電極パッド（さらに他の電極パッド）、６ チップ側電極パッド、６ａ 下段チップ側電極パッド（一の電極パッド）、６ｂ 上段チップ側電極パッド（他の電極パッド）、７ 接着剤、８ 基部、９ 受け面、１０ バンプ、１１ キャピラリ、１１ａ フェイス部、１１ｂ 貫通孔、１２ ボール部、５１ 半導体装置、５４ａ 上段金属ワイヤ、５４ｂ 下段金属ワイヤ、６０ バンプ、Ｘ，Ｙ，Ｚ 間隔   DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Substrate, 3 Semiconductor chip, 3a Lower semiconductor chip (one semiconductor chip), 3b Upper semiconductor chip (other semiconductor chip), 4 Metal wire, 4a Upper metal wire, 4b Lower metal wire (Other Metal wire), 5 substrate side electrode pad (further electrode pad), 6 chip side electrode pad, 6a lower chip side electrode pad (one electrode pad), 6b upper chip side electrode pad (other electrode pad), 7 Adhesive, 8 base, 9 receiving surface, 10 bump, 11 capillary, 11a face, 11b through hole, 12 ball, 51 semiconductor device, 54a upper metal wire, 54b lower metal wire, 60 bump, X, Y, Z interval

Claims (5)

基板と、
前記基板の半導体チップ積層面側を上とした場合の、前記基板上に少なくとも２段以上積層された前記半導体チップと、
前記基板および前記半導体チップに形成された電極パッドと、
前記電極パッド間を電気的に接続させる金属ワイヤと、を備え、
前記電極パッドのうち一の電極パッドに接合された前記金属ワイヤの一端には、ステッチボンディングが可能な受け面が形成された基部が設けられ、前記受け面をよけた位置から前記一の電極パッドよりも上段に設けられた他の電極パッドに向けて前記金属ワイヤが延び、
前記一の電極パッドよりも下段に設けられたさらに他の電極パッドに一端が接合された他の金属ワイヤの他端が、前記基部に形成された前記受け面にステッチボンディングにより接合されており、
前記電極パッドのうち最上段の電極パッドに接合された前記金属ワイヤの最上段の前記電極パッド側の一端は、最上段の前記電極パッド上に設けられたバンプに接続されている半導体装置。 A substrate,
When the semiconductor chip lamination surface side of the substrate is the top, the semiconductor chip laminated at least two or more stages on the substrate;
Electrode pads formed on the substrate and the semiconductor chip;
A metal wire for electrically connecting the electrode pads,
One end of the metal wire joined to one of the electrode pads is provided with a base portion on which a receiving surface capable of stitch bonding is formed, and the one electrode pad from a position away from the receiving surface. The metal wire extends toward another electrode pad provided in the upper stage,
The other end of the other metal wire bonded at one end to the other electrode pad provided below the one electrode pad is bonded to the receiving surface formed at the base by stitch bonding,
One end of the metal wire bonded to the uppermost electrode pad among the electrode pads on the electrode pad side on the uppermost stage is connected to a bump provided on the uppermost electrode pad. 基板と、
前記基板上に少なくとも２段以上積層された半導体チップと、
前記基板および前記半導体チップに形成された電極パッドと、
前記電極パッド間を電気的に接続させる金属ワイヤと、を備え、
前記電極パッドのうち一の電極パッドに接合された前記金属ワイヤの一端には、ステッチボンディングが可能な受け面が形成された基部が設けられ、前記受け面をよけた位置から前記一の電極パッドよりも上段に設けられた他の電極パッドに向けて前記金属ワイヤが延びている半導体装置。 A substrate,
A semiconductor chip laminated on at least two stages on the substrate;
Electrode pads formed on the substrate and the semiconductor chip;
A metal wire for electrically connecting the electrode pads,
One end of the metal wire joined to one of the electrode pads is provided with a base portion on which a receiving surface capable of stitch bonding is formed, and the one electrode pad from a position away from the receiving surface. A semiconductor device in which the metal wire extends toward another electrode pad provided in the upper stage. 前記一の電極パッドよりも下段に設けられたさらに他の電極パッドに一端が接合された他の金属ワイヤの他端が、前記基部に形成された前記受け面にステッチボンディングにより接合されている請求項２に記載の半導体装置。   The other end of another metal wire having one end bonded to another electrode pad provided below the one electrode pad is bonded to the receiving surface formed on the base by stitch bonding. Item 3. The semiconductor device according to Item 2. 基板と、前記基板の半導体チップ積層面側を上とした場合の前記基板上に少なくとも２段以上積層された前記半導体チップと、前記基板および前記半導体チップに形成された電極パッドと、前記電極パッドに接合されて前記電極パッド間を電気的に接続させる金属ワイヤと、を備える半導体装置の製造方法であって、
先端から前記金属ワイヤを供給するキャピラリによって、前記金属ワイヤの一端に形成されたボール部を、前記電極パッドのうち一の電極パッドに押しつけてつぶすことで前記金属ワイヤの一端を前記一の電極パッドに接合し、
前記ボール部がつぶされて形成された基部に、前記キャピラリのフェイス部を押し当てて、ステッチボンディングが可能な受け面を形成し、
前記キャピラリを前記一の電極パッドよりも上段に設けられた他の電極パッド側に移動させて前記他の電極パッドに前記金属ワイヤの他端をステッチボンディングする半導体装置の製造方法。 The substrate, the semiconductor chip laminated on the substrate when the semiconductor chip lamination surface side of the substrate is on the upper side, the electrode pad formed on the substrate and the semiconductor chip, and the electrode pad A metal wire bonded to the electrode pads to electrically connect the electrode pads,
The ball portion formed at one end of the metal wire is pressed against one of the electrode pads by a capillary for supplying the metal wire from the tip, and the one end of the metal wire is crushed by the one electrode pad. Joined to
Pressing the face part of the capillary against the base part formed by crushing the ball part, forming a receiving surface capable of stitch bonding,
A method of manufacturing a semiconductor device, wherein the capillary is moved to another electrode pad provided above the one electrode pad, and the other end of the metal wire is stitch-bonded to the other electrode pad. 前記一の電極パッドよりも下段に設けられたさらに他の電極パッドに一端が接合された他の金属ワイヤの他端を、前記基部に形成された前記受け面にステッチボンディングによって接合する請求項４に記載の半導体装置の製造方法。   5. The other end of another metal wire, one end of which is joined to another electrode pad provided below the one electrode pad, is joined to the receiving surface formed on the base by stitch bonding. The manufacturing method of the semiconductor device as described in 2. above.
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