TW201338110A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device capable of suppressing the loop height of metal wire in thinning the device, and suppressing number of jointing steps for reducing costs. The semiconductor device 1 comprises a substrate 2, a semiconductor chip 3, electrode pads 5, 6 and a metal wire 4. The semiconductor chip is laminated at least two sections on the substrate. The electrode pads are formed on the substrate and the semiconductor chip. The metal wire is electrically connected between the electrode pads. One end of the metal wire 4a jointing to one pad 6a of the electrode pads is arranged with a base 8 having a supporting surface 9. The metal wire is extended from the position, which is away from the supporting face, to an electrode pad 6b arranged at an upper section above the other electrode pad. Another end of another metal wire 4b, which has one end jointing to an electrode pad 5 at a lower section under the electrode pad, is jointed to the supporting surface of the base through end of the wire.

Description

Semiconductor device and method of manufacturing same

Embodiments of the present invention relate to a semiconductor device and a method of fabricating the same.

[Associated Application] This application has priority in the application based on Japanese Patent Application No. 2012-57215 (application date: March 14, 2012). This application contains the entire contents of the basic application by reference to the basic application.

Conventionally, a semiconductor device in which a semiconductor wafer such as a controller wafer or a memory wafer is placed on a substrate on which a wiring layer is formed is known. In such a semiconductor device, the substrate and the wafer are electrically connected to each other by an electrode pad provided on the substrate by metal wire connection (hereinafter also referred to as bonding) and an electrode pad provided on the wafer. In such a semiconductor device, it is desirable to suppress the circuit height of the metal wire to be lower to make the device itself thinner.

An object of an embodiment of the present invention is to provide a semiconductor device and a method of manufacturing the same, which are capable of suppressing the thickness of a metal line, reducing the thickness of the device, and suppressing the number of steps of bonding, thereby reducing the cost.

According to an embodiment of the present invention, a semiconductor device including a substrate, a semiconductor wafer, an electrode pad, and a metal line is provided. The semiconductor wafer is laminated on the substrate at least two stages or more. Here, the term "substrate" refers to the substrate The semiconductor wafer layer side is the upper case. The electrode pads are formed on the substrate and the semiconductor wafer. The metal wires are electrically connected between the electrode pads. A base portion on which a support surface is formed is provided at one end of a metal wire bonded to one of the electrode pads. The metal wire extends from the position avoiding the support surface to the other electrode pad disposed on the upper portion of the one electrode pad. The other end of the other metal wire joined to the other electrode pad disposed at the lower portion of the electrode pad is joined to the support surface of the base by stitch bonding. One end of the electrode pad side of the uppermost stage of the metal line bonded to the electrode pad of the uppermost stage of the electrode pad is connected to the bump provided on the electrode pad of the uppermost stage.

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the present invention is not limited by the embodiment.

(First embodiment)

Fig. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. The semiconductor device 1 includes a substrate 2, a semiconductor wafer 3, and a metal wire 4. The substrate 2 is, for example, a wiring layer provided inside or on the surface of the insulating resin substrate, and also serves as a component mounting substrate and a terminal forming substrate. As such a substrate 2, a printed wiring board using a glass-epoxy resin or a glass-BT (bismaleimido triazine resin (bismaleimide-triazine resin) or the like is used. A plurality of electrode pads (substrate side electrode pads (further other electrode pads) 5) are formed on the surface of the substrate 2.

The semiconductor wafer 3 is a semiconductor element mounted on the substrate 2, for example, a controller chip for controlling a DRAM (Dynamic Random Access Memory) or a NAND (NOT) flash memory. , or semiconductor memory such as DRAM or NAND flash memory Body wafer. A plurality of electrode pads (wafer-side electrode pads 6) are formed on the upper surface of the semiconductor wafer 3.

A plurality of semiconductor wafers 3 are laminated on the substrate 2. In the present embodiment, two semiconductor wafers 3 are laminated as an example. In the following description, the semiconductor wafer 3 directly mounted on the substrate 2 is also referred to as a lower-side semiconductor wafer (a semiconductor wafer) 3a, and the semiconductor wafer 3 laminated on the upper-side semiconductor wafer 3a is referred to as an upper-side side. A semiconductor wafer (another semiconductor wafer) 3b.

The semiconductor wafer 3 is then attached to the substrate 2 or the lower-side semiconductor wafer 3a by using an adhesive 7 such as a thermosetting resin. The plurality of semiconductor wafers 3 are arranged to be offset from each other in plan view, and are stacked in a stepped manner. Thereby, a part of the upper surface of the lower-side semiconductor wafer 3a is not exposed by the upper-side semiconductor wafer 3b. The wafer side electrode pad 6 is formed at a position as the exposed portion. In the following description, the wafer side electrode pad 6 formed on the segment side semiconductor wafer 3a is also referred to as a lower stage wafer side electrode pad (an electrode pad) 6a, and the wafer side electrode pad formed on the upper stage side semiconductor wafer 3b. 6 is referred to as an upper wafer side electrode pad (another electrode pad) 6b.

The metal wires 4 are joined to the electrode pads 5 and 6 at both ends thereof, and the electrode pads 5 and 6 are electrically connected to each other. The metal wire 4 is made of a metal such as gold. In the following description, the metal wires electrically connecting the lower wafer side electrode pad 6a and the upper wafer side electrode pad 6b are also referred to as the upper metal wires 4a, and the substrate side electrode pads 5 and the lower wafer side electrodes are electrically connected. The metal wire of the pad 6a is referred to as a lower metal wire (another metal wire) 4b. Further, bonding the metal wires 4 to the electrode pads 5, 6 is also referred to as bonding.

Next, the manufacturing sequence of the semiconductor device 1 will be described in detail using the drawings. 2, 3, 4, and 6 are enlarged cross-sectional views showing a portion of the portion A shown in Fig. 1, which is a view for explaining the order of joining. Figure 5 is a cross-sectional view taken along line B-B of Figure 4; Fig. 7 is a cross-sectional view taken along line C-C of Fig. 6. Fig. 8 is a flow chart for explaining the manufacturing sequence of the semiconductor device. Further, the illustration of the capillary 11 is omitted in Figs.

First, the semiconductor wafer 3 is mounted on the substrate 2 (step S1). Next, bumps 10 are formed on the upper wafer side electrode pads 6b of the upper stage side semiconductor wafer 3b (step S2). The bump 10 is provided on the electrode pad (the upper wafer side electrode pad 6b in the present embodiment) as the uppermost stage, and forms a specific interval X between the lower end of the metal wire 4 and the upper surface of the upper-side semiconductor wafer 3b ( See also Figure 1). If the interval X is insufficient, the metal wire 4 may come into contact with the upper surface of the upper-stage semiconductor wafer 3b. Further, the formation of the bumps 10 is performed by the capillary 11, but a detailed description thereof will be omitted.

Next, one end of the upper metal wire 4a is bonded to the lower wafer side electrode pad 6a of the lower stage side semiconductor wafer 3a by rapid bonding. As shown in FIG. 2, the metal wire 4 is supplied through the through hole 11b formed in the capillary 11. A ball portion 12 having a substantially spherical shape is formed at a front end of the metal wire 4 before being bonded to the wafer side electrode pad 6. The ball portion 12 is formed by melting a metal wire 4 protruding from the front end of the capillary 11 by a spark generated by a voltage applied between a torch (not shown) and the wire 4. Further, the bonding of the metal wires 4 is performed by applying a load and an ultrasonic wave to the metal wires 4 by the capillary 11.

First, as shown in FIG. 3, the ball portion 12 is pressed against the lower wafer side electrode pad 6a by the capillary 11 (step S3), thereby performing the upper segment metal wire 4a to the lower segment. Bonding of the wafer side electrode pads 6a.

Next, as shown in Figs. 4 and 5, the base portion 8 and the support surface 9 are formed at one end of the upper metal wire 4a (step S4). More specifically, in step S3, the base portion 8 formed by pressing the ball portion 12 presses the face portion 11a of the capillary tube 11 to form the support surface 9.

When the face portion 11a is pressed, the capillary 11 is first moved in the direction in which the second bonding is performed, that is, in the direction of the upper wafer side electrode pad 6b. Thereby, the portion of the face portion 11a that is away from the upper wafer side electrode pad 6b is pressed against the base portion 8.

By pressing the base portion 8 with a portion of the face portion 11a that is away from the upper wafer-side electrode pad 6b, as shown in Figs. 4 and 5, the metal wire 4 can be brought from the position where the support surface 9 is avoided. The state in which the position of the second joining position (the direction of the upper wafer side electrode pad 6b) extends.

Next, the other end of the upper metal wire 4a is joined to the bump 10 on the upper wafer side electrode pad 6b by the second bonding (step S5). The bonding of the bumps 10 is generally performed by a method called tail bonding. Thereby, the lower wafer side electrode pad 6a and the upper wafer side electrode pad 6b are electrically connected by the upper metal wire 4a.

Next, one end of the lower metal wire 4b is bonded to the substrate-side electrode pad 5 by rapid bonding (step S6). The joining of the substrate-side electrode pads 5 is generally performed by a method called spherical bonding.

Next, as shown in Figs. 6 and 7, the other end of the lower wire 4b is joined to the support surface 9 formed on the base 8 by the second joining (step S7). The joining of the support faces 9 is generally performed by a method called wire tail bonding.

The semiconductor device 1 is fabricated in accordance with the above steps. Further, after step S7, the outline of the semiconductor device 1 may be formed by sealing the surface of the substrate 2 with a resin or by covering the outer casing.

Fig. 9 is a cross-sectional view showing a semiconductor device as a comparative example. The same components as those of the above-described semiconductor device 1 are denoted by the same reference numerals. The semiconductor device 51 shown as a comparative example is the same as the lower metal wire 4b of the semiconductor device 1, and is rapidly joined by ball bonding at both the upper metal wire 54a and the lower metal wire 54b, and is secondarily joined by wire tail bonding. Engage.

Further, after the lower metal wires 54b are joined, the upper metal wires 54a are joined. In the second bonding of the lower metal wires 54b, in order to perform wire tail bonding, a specific interval Z is necessary between the lower end of the lower metal wire 54b and the upper surface of the lower segment side semiconductor wafer 3a. If the interval Z is insufficient, the lower metal wire 54b may be brought into contact with the upper surface of the lower-side semiconductor wafer 3a.

In order to provide a sufficient interval Z, in the semiconductor device 51, not only the bump 60 is formed on the upper wafer side electrode pad 6b, but also the bump 60 is formed on the lower wafer side electrode pad 6a. Further, by the ball bonding, the upper metal wire 54a is bonded to the lower wafer side electrode pad 6a of the lower wire metal wire 54b.

Therefore, the loop height of the upper metal wire 54a is increased to the height of the bump 60. Moreover, since the steps for forming the bumps 60 are necessary, the cost increases due to an increase in the number of working hours.

On the other hand, in the semiconductor device 1 of the present embodiment, the upper metal wire 4a is bonded to the lower wafer side electrode pad 6a, and the base portion 8 and the support surface 9 are formed, whereby the tail tail joint can be secured without providing the bump 60. Required interval Y (also Referring to Fig. 6), a face (support surface 9) which is an object of tail bonding can be provided.

Further, since the upper wire 4a avoids the support surface 9 in plan view and extends from the position in the direction of the second joining position, the loop 11 is prevented from being crushed by the capillary 11 when the wire tail is joined.

Therefore, since the upper metal wire 4a and the lower metal wire 4b can be joined without providing the bump 60 on the lower wafer side electrode pad 6a, the loop height of the upper metal wire 4a can be suppressed to be lower than the height of the bump 60. . Thereby, the thickness of the semiconductor device 1 can be reduced. Moreover, since the step of providing the bumps 60 can be reduced, it is possible to suppress the cost caused by the reduction in man-hours.

In the present embodiment, an example in which two semiconductor wafers 3 are laminated is described. However, three or more semiconductor wafers 3 may be laminated. For example, in the case of a semiconductor device in which four semiconductor wafers are stacked in four stages, the electrode pads of the semiconductor wafer from the substrate side to the first to third stages can be omitted.

Further effects or variations can be readily derived by those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments disclosed and described. Therefore, various changes may be made without departing from the spirit and scope of the inventions of the appended claims.

1‧‧‧Semiconductor device

2‧‧‧Substrate

3‧‧‧Semiconductor wafer

3a‧‧‧Semi-side semiconductor wafer (a semiconductor wafer)

3b‧‧‧Upper side semiconductor wafer (another semiconductor wafer)

4‧‧‧Metal wire

4a‧‧‧Upper metal wire

4b‧‧‧lower metal wire (another metal wire)

5‧‧‧Substrate side electrode pad (further other electrode pads)

6‧‧‧ wafer side electrode pad

6a‧‧‧lower wafer side electrode pad (one electrode pad)

6b‧‧‧Upper wafer side electrode pad (other electrode pad)

7‧‧‧Binder

8‧‧‧ base

9‧‧‧ support surface

10‧‧‧Bumps

11‧‧‧ Capillary

11a‧‧‧Face

11b‧‧‧through hole

12‧‧‧Ball Department

51‧‧‧Semiconductor device

54a‧‧‧Upper metal wire

54b‧‧‧The lower wire

60‧‧‧Bumps

X‧‧‧ interval

Y‧‧‧ interval

Z‧‧‧ interval

Fig. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.

Fig. 2 is an enlarged cross-sectional view showing a portion of the portion A shown in Fig. 1 for explaining the sequence of joining.

Figure 3 is an enlarged cross-sectional view showing a portion of the portion A shown in Figure 1, which is used for A diagram illustrating the sequence of bonding.

Fig. 4 is an enlarged cross-sectional view showing a portion of the portion A shown in Fig. 1 for explaining the sequence of joining.

Figure 5 is a cross-sectional view taken along line B-B of Figure 4;

Fig. 6 is an enlarged cross-sectional view showing a portion of the portion A shown in Fig. 1 for explaining the sequence of joining.

Fig. 7 is a cross-sectional view taken along line C-C of Fig. 6.

Fig. 8 is a flow chart for explaining the manufacturing sequence of the semiconductor device.

Fig. 9 is a cross-sectional view showing a semiconductor device as a comparative example.

1‧‧‧Semiconductor device

2‧‧‧Substrate

3‧‧‧Semiconductor wafer

3a‧‧‧lower side semiconductor wafer

3b‧‧‧Upper side semiconductor wafer

4‧‧‧Metal wire

4a‧‧‧Upper metal wire

4b‧‧‧lower metal wire

5‧‧‧Substrate side electrode pad

6‧‧‧ wafer side electrode pad

6a‧‧‧lower wafer side electrode pad

6b‧‧‧Upper wafer side electrode pad

7‧‧‧Binder

8‧‧‧ base

9‧‧‧ support surface

10‧‧‧Bumps

X‧‧‧ interval

Claims (5)

A semiconductor device comprising: a substrate; wherein, when the semiconductor wafer is on the side of the semiconductor wafer layer, at least two or more layers are stacked on the substrate; and an electrode pad formed on the substrate and a semiconductor wafer; and a metal wire electrically connected between the electrode pads; and at one end of the metal wire bonded to one of the electrode pads, a base portion on which a support surface capable of wire tail bonding is formed is provided, The metal wire extends from the position of the support surface to the other electrode pad disposed on the upper portion of the electrode pad, and the one end is joined to the other metal wire disposed on the further electrode pad of the lower electrode segment than the one electrode pad. The other end is joined to the support surface formed on the base by wire tail bonding, and is joined to one end of the electrode pad side of the uppermost stage of the metal wire of the electrode pad of the uppermost one of the electrode pads, and is connected to The bump on the electrode pad of the uppermost stage. A semiconductor device comprising: a substrate; a semiconductor wafer having at least two or more layers stacked on the substrate; an electrode pad formed on the substrate and the semiconductor wafer; and a metal wire electrically connected between the electrode pads; And a base portion formed with a support surface capable of wire tail bonding is formed at one end of the metal wire bonded to one of the electrode pads, The metal wire extends from the position of the support surface away from the other electrode pad disposed above the upper electrode pad. The semiconductor device of claim 2, wherein one end is bonded to the other end of the other metal line disposed on the further electrode pad of the lower portion of the electrode pad, and is bonded to the support formed on the base by wire tail bonding surface. A semiconductor device comprising: a substrate; and a semiconductor wafer having at least two or more layers stacked on the substrate on a side of the semiconductor wafer layer of the substrate; and an electrode pad formed on the substrate a substrate and the semiconductor wafer; and a metal wire bonded to the electrode pad and electrically connected between the electrode pads; and the manufacturing method is formed on one end of the metal wire by supplying a capillary of the metal wire from a front end The ball portion is pressed against one of the electrode pads to bond one end of the wire to the electrode pad, and the base formed by pressing the ball portion presses the face of the capillary to form a line The support surface of the tail joint moves the capillary to the other electrode pad side disposed above the upper electrode pad, and the other end of the metal wire is bonded to the other electrode pad. The method of manufacturing the semiconductor device of claim 4, wherein one end is bonded to the other end of the other metal line disposed on the other electrode pad of the lower portion of the electrode pad, and is bonded to the above by wire tail bonding. The above bearing surface of the base.