JP2000091355A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JP2000091355A
JP2000091355A JP10257029A JP25702998A JP2000091355A JP 2000091355 A JP2000091355 A JP 2000091355A JP 10257029 A JP10257029 A JP 10257029A JP 25702998 A JP25702998 A JP 25702998A JP 2000091355 A JP2000091355 A JP 2000091355A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding
semiconductor
wire
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10257029A
Other languages
Japanese (ja)
Inventor
Makoto Tsubonoya
誠 坪野谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10257029A priority Critical patent/JP2000091355A/en
Publication of JP2000091355A publication Critical patent/JP2000091355A/en
Pending legal-status Critical Current

Links

Classifications

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the contact of a wire and a semiconductor chip by providing a compressing part at a pyramid collet and processing the loop shape of a bonding, at the lower side at the same time as die bonding. SOLUTION: A first semiconductor chip 10 is fixed on an island 13. A first electrode pad 2a and a lead terminal 17 are connected with a first bonding wire 16a. A second semiconductor chip 11 is chucked by a pyramid collet 20 and is die-bonded on a semiconductor chip 10. At this time, by pushing down the loop of the first bonding wire 16a by a compressing part 21 of the pyramid collet 20, the first bonding wire 16a is positively contained in a recess part 19, and contacting with the second conductor chip 11 is avoided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、複数の半導体チッ
プを重ね合わせてモールドしつつ、近似した大きさを持
つ半導体チップの組み合わせでも小型化できる半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be miniaturized by combining a plurality of semiconductor chips having an approximate size while overlapping and molding a plurality of semiconductor chips.

【０００２】[0002]

【従来の技術】半導体装置の封止技術として最も普及し
ているのが、図６（Ａ）に示したような、半導体チップ
１の周囲を熱硬化性のエポキシ樹脂２で封止するトラン
スファーモールド技術である。半導体チップ１の支持素
材としてリードフレームを用いており、リードフレーム
のアイランド３に半導体チップ１をダイボンドし、半導
体チップ１のボンディングパッドとリード４をワイヤ５
でワイヤボンドし、所望の外形形状を具備する金型内に
リードフレームをセットし、金型内にエポキシ樹脂を注
入、これを硬化させることにより製造される。2. Description of the Related Art A transfer molding method for sealing a semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. Technology. A lead frame is used as a support material for the semiconductor chip 1. The semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pads of the semiconductor chip 1 and the leads 4 are connected to the wires 5.
It is manufactured by setting a lead frame in a mold having a desired outer shape, injecting an epoxy resin into the mold, and curing the lead frame.

【０００３】一方、各種電子機器に対する小型、軽量化
の波はとどまるところを知らず、これらに組み込まれる
半導体装置にも、一層の大容量、高機能、高集積化が望
まれることになる。On the other hand, the wave of miniaturization and weight reduction of various electronic devices is unavoidable, and semiconductor devices incorporated therein are required to have higher capacity, higher function, and higher integration.

【０００４】そこで、以前から発想としては存在してい
た（例えば、特開昭５５ー１１１１５１７号）、１つの
パッケージ内に複数の半導体チップを封止する技術が注
目され、実現化する動きが出てきた。つまり図６（Ｂ）
に示すように、アイランド３上に第１の半導体チップ１
ａを固着し、第１の半導体チップ１ａの上に第２の半導
体チップ１ｂを固着し、対応するボンディングパッドと
リード端子４とをボンディングワイヤ５ａ、５ｂで接続
し、樹脂２で封止したものである。In view of this, a technique of sealing a plurality of semiconductor chips in one package, which has existed as an idea (for example, Japanese Patent Application Laid-Open No. 55-1111517), has been attracting attention, and there has been a movement to realize it. Have been. That is, FIG.
As shown in FIG. 1, the first semiconductor chip 1
a, the second semiconductor chip 1b is fixed on the first semiconductor chip 1a, and the corresponding bonding pads and the lead terminals 4 are connected with the bonding wires 5a, 5b and sealed with the resin 2. It is.

【０００５】[0005]

【発明が解決しようとする課題】図６（Ｂ）の構成は、
第１の半導体チップ１ａとのワイヤボンディングを確保
するため、第２の半導体チップ１ｂを固着したときに第
１の半導体チップ１ａの電極パッド部分が露出している
こと、即ちチップサイズに差のあることが絶対的な条件
となる。そのため、例えば同一機種のチップを２個組み
込む、或いは別機種のチップであってもそのチップサイ
ズが近似する場合には採用できない欠点があった。２つ
の半導体チップを十文字に重ね合わせることも考えられ
るが、これとてチップサイズの縦×横の寸法に差がある
ことが条件となり、依然として制約が残るものである。The structure shown in FIG. 6B is as follows.
In order to secure wire bonding with the first semiconductor chip 1a, the electrode pad portion of the first semiconductor chip 1a is exposed when the second semiconductor chip 1b is fixed, that is, there is a difference in chip size. That is an absolute condition. For this reason, there is a disadvantage that, for example, two chips of the same model are incorporated, or chips of different models cannot be adopted when their chip sizes are similar. Although it is conceivable to superimpose two semiconductor chips in a cross shape, the condition is that there is a difference in the vertical and horizontal dimensions of the chip size, and the restrictions still remain.

【０００６】これを解決するために、例えば図６（Ｃ）
に示すように、アイランド３の両面に各半導体チップ１
ａ、１ｂの裏面が対向するようにこれらを固着する手法
がある。しかしながら、ボンディングワイヤのループ高
さの分が２倍必要になるので、半導体装置全体の厚み
（図６（Ｃ）の図示Ｘ）が増して、薄形化できない欠点
がある。To solve this, for example, FIG.
As shown in FIG.
There is a method of fixing these so that the back surfaces of a and 1b face each other. However, since the loop height of the bonding wire needs to be doubled, the thickness of the entire semiconductor device (X in FIG. 6C) increases, and there is a disadvantage that the thickness cannot be reduced.

【０００７】[0007]

【課題を解決するための手段】本発明は上述した従来の
課題に鑑み成されたもので、あらかじめダイボンドとワ
イヤボンドを施した第１の半導体チップの上に第２の半
導体チップをダイボンドする半導体装置の製造方法であ
って、前記第２の半導体チップを吸着し搬送するコレッ
トに押圧部を設け、前記第２の半導体チップを前記第１
の半導体チップの上に固定すると同時に前記コレットの
押圧部が前記第１の半導体チップのボンディングワイヤ
のループを押し下げるようにしたことを特徴とするもの
である。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has been made in consideration of the above-described problems. A method of manufacturing an apparatus, wherein a pressing portion is provided on a collet that sucks and transports the second semiconductor chip, and the second semiconductor chip is attached to the first semiconductor chip.
And a pressing portion of the collet presses down a loop of a bonding wire of the first semiconductor chip at the same time as fixing on the semiconductor chip.

【０００８】[0008]

【発明の実施の形態】以下に本発明の一実施の形態を詳
細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail.

【０００９】先ず完成品の構成を説明する。図２は本発
明の半導体装置の主要部を示す断面図、図３（Ａ）は全
体を示す断面図、同じく図３（Ｂ）は全体を示す平面図
である。First, the structure of the finished product will be described. FIG. 2 is a sectional view showing a main part of the semiconductor device of the present invention, FIG. 3A is a sectional view showing the whole, and FIG. 3B is a plan view showing the whole.

【００１０】これらの図において、１０、１１は各々第
１と第２の半導体チップを示している。第１と第２の半
導体チップ１０、１１のシリコン表面には、前工程にお
いて各種の拡散熱処理などによって多数の能動、受動回
路素子が形成されている。第１と第２の半導体チップ１
０、１１のチップ周辺部分には外部接続用の第１と第２
の電極パッド１２ａ、１２ｂがアルミ電極によって形成
されている。各電極パッド１２ａ、１２ｂの上にはパッ
シベーション皮膜が形成され、電極パッド１２ａ、１２
ｂの上部が電気接続のために開口されている。パッシベ
ーション被膜はシリコン窒化膜、シリコン酸化膜、ポリ
イミド系絶縁膜などである。図３（Ｂ）の例では、各電
極パッド１２ａ、１２ｂは半導体チップ１０、１１の対
向する２辺に沿って集約して配置されている。In these figures, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. A large number of active and passive circuit elements are formed on the silicon surfaces of the first and second semiconductor chips 10 and 11 by various diffusion heat treatments in a previous process. First and second semiconductor chips 1
First and second external connection first and second
Electrode pads 12a and 12b are formed of aluminum electrodes. A passivation film is formed on each of the electrode pads 12a, 12b.
The top of b is open for electrical connection. The passivation film is a silicon nitride film, a silicon oxide film, a polyimide insulating film, or the like. In the example of FIG. 3B, the electrode pads 12a and 12b are arranged collectively along two opposing sides of the semiconductor chips 10 and 11.

【００１１】第１の半導体チップ１０がリードフレーム
のアイランド１３上に接着剤１４によりダイボンドされ
る。第２の半導体チップ１１が第１の半導体チップ１０
の前記パッシベーション皮膜上に接着剤１５により固着
されている。接着剤１４は導電性または絶縁性、接着剤
１５は絶縁性のエポキシ系接着剤である。A first semiconductor chip 10 is die-bonded onto an island 13 of a lead frame by an adhesive 14. The second semiconductor chip 11 is the first semiconductor chip 10
Is fixed by an adhesive 15 on the passivation film. The adhesive 14 is conductive or insulating, and the adhesive 15 is an insulating epoxy-based adhesive.

【００１２】第１の電極パッド１２ａには、金線からな
る第１のボンディングワイヤ１６ａの一端が接続されて
おり、第１のボンディングワイヤ１６ａの他端は外部導
出用のリード端子１７にワイヤボンドされている。ま
た、第２の電極パッド１２ｂの表面には、第２のボンデ
ィングワイヤ１６ｂの一端がワイヤボンドされており、
第２のボンディングワイヤ１６ｂの他端は外部導出用の
リード端子１７にワイヤボンドされている。One end of a first bonding wire 16a made of a gold wire is connected to the first electrode pad 12a, and the other end of the first bonding wire 16a is connected to an external lead terminal 17 by wire bonding. Have been. One end of a second bonding wire 16b is wire-bonded to the surface of the second electrode pad 12b,
The other end of the second bonding wire 16b is wire-bonded to a lead terminal 17 for external lead-out.

【００１３】第１と第２の半導体チップ１０、１１、リ
ード端子１７の一部、および第１と第２のボンディング
ワイヤ１６ａ、１６ｂを含む主要部は、周囲をエポキシ
系の熱硬化樹脂１８でモールドされて半導体装置のパッ
ケージを形成する。リード端子１７はパッケージの側壁
から外部に導出されて外部接続端子となる。導出された
リード端子１７はＺ字型に曲げ加工されている。アイラ
ンド１３の裏面側は樹脂１８の表面に露出しており、樹
脂１８表面と同一平面を形成している。The main portion including the first and second semiconductor chips 10 and 11, the lead terminals 17, and the first and second bonding wires 16a and 16b is surrounded by an epoxy-based thermosetting resin 18. It is molded to form a semiconductor device package. The lead terminal 17 is led out from the side wall of the package to be an external connection terminal. The lead terminal 17 is bent into a Z-shape. The back surface of the island 13 is exposed on the surface of the resin 18 and forms the same plane as the surface of the resin 18.

【００１４】第１と第２の半導体チップ１０、１１の組
み合わせは任意である。例えば、第１と第２の半導体チ
ップ１０、１１としてＥＥＰＲＯＭ（フラッシュメモ
リ）等の半導体記憶装置を用いた場合（第１の組み合わ
せ例）は、１つのパッケージで記憶容量を２倍、３倍・
・・にすることができる。また、第１の半導体チップ１
０にＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶
装置を、第２の半導体チップ１１にはＳＲＡＭ等の半導
体記憶装置を形成するような場合（第２の組み合わせ
例）ことも考えられる。どちらの組み合わせの場合で
も、各チップにはデータの入出力を行うＩ／Ｏ端子と、
データのアドレスを指定するアドレス端子、及びデータ
の入出力を許可するチップイネーブル端子とを具備して
おり、両チップのピン配列が酷似している。そのため、
第１と第２の半導体チップ１０、１１のＩ／Ｏ端子やア
ドレス端子用のリード端子１７を共用することが可能で
あり、各チップに排他的なチップイネーブル信号を印加
することにより、どちらか一方の半導体チップのメモリ
セルを排他的に選択することが可能である。The combination of the first and second semiconductor chips 10, 11 is arbitrary. For example, when semiconductor storage devices such as an EEPROM (flash memory) are used as the first and second semiconductor chips 10 and 11 (first combination example), the storage capacity can be doubled or tripled in one package.
・ ・ It can be done. Also, the first semiconductor chip 1
It is also conceivable that a semiconductor memory device such as an EEPROM (flash memory) is formed on the second semiconductor chip 11 and a semiconductor memory device such as an SRAM is formed on the second semiconductor chip 11 (second combination example). In either case, each chip has an I / O terminal for inputting and outputting data,
It has an address terminal for designating a data address and a chip enable terminal for permitting data input / output, and the pin arrangements of both chips are very similar. for that reason,
The I / O terminal and the lead terminal 17 for the address terminal of the first and second semiconductor chips 10 and 11 can be shared, and by applying an exclusive chip enable signal to each chip, one of them can be used. It is possible to exclusively select the memory cells of one semiconductor chip.

【００１５】上記第１の組み合わせ例の場合には当然の
事ながら、第１の半導体チップ１０と第２の半導体チッ
プ１１が大略同じ大きさと形状を有し、電極パッド１２
ａ、１２ｂの配列も同じである。そのため、両者を重ね
ると、第１の半導体チップ１０の電極パッド１２ａが第
２の半導体チップ１１の陰に隠れる。具体的に、図３
（Ｂ）の例では第２の電極パッド１２ｂの直下に第１の
電極パッド１２ａが位置する。又第２の組み合わせ例の
場合でも、チップサイズと形状が近似し且つピン配列が
酷似する場合があり得る。In the case of the first combination example, the first semiconductor chip 10 and the second semiconductor chip 11 have the same size and shape, and
The arrangement of a and 12b is the same. Therefore, when they are overlapped, the electrode pads 12 a of the first semiconductor chip 10 are hidden behind the second semiconductor chip 11. Specifically, FIG.
In the example of (B), the first electrode pad 12a is located immediately below the second electrode pad 12b. Also in the case of the second combination example, the chip size and shape may be similar and the pin arrangement may be very similar.

【００１６】而して、第２の半導体チップ１２ｂの対向
する２辺に沿って、第１の電極パッド１２ａの上方に凹
部１９を形成し、第２の半導体チップ１１をひさし状に
突出させている。凹部１９は第１の半導体チップ１０の
端部から第１の電極１２ａを露出するだけの幅（図１：
Ｗ）を持ち、更には第１のボンディングワイヤ１６ａの
ワイヤ高さ（図１：ｔ１）を収納するだけの高さを持
つ。尚、前記収納する高さは第１の半導体チップ１０の
表面からの高さであるから、接着剤１５の膜厚も考慮し
て凹部１９の深さ（ｔ２）を決定する。Thus, a concave portion 19 is formed above the first electrode pad 12a along two opposing sides of the second semiconductor chip 12b, and the second semiconductor chip 11 is protruded like an eaves. I have. The recess 19 has a width enough to expose the first electrode 12a from the end of the first semiconductor chip 10 (FIG. 1:
W), and has a height sufficient to accommodate the wire height of the first bonding wire 16a (FIG. 1: t1). Since the height to be accommodated is a height from the surface of the first semiconductor chip 10, the depth (t2) of the concave portion 19 is determined in consideration of the thickness of the adhesive 15.

【００１７】凹部１９は第１の電極パッド１２ａの上方
に空間を形成し、この空間内で第１のボンディングワイ
ヤ１６ａが第１の電極パッド１２ａにボールボンディン
グされている。ボール部から連続する第１のボンディン
グワイヤ１６ａは凹部１９を通過し、リード端子１７に
セカンドボンドされる。第１の半導体チップ１０の表面
の高さに対してリード端子１７の表面が高いような場合
には、第１のボンディングワイヤ１６ａは第１の電極１
２ａから凹部１９を通過して横方向に導出され、第２の
半導体チップ１１の端より外側で上昇し、リード端子１
７先端部に到達する様な軌跡を描く。The recess 19 forms a space above the first electrode pad 12a, in which the first bonding wire 16a is ball-bonded to the first electrode pad 12a. The first bonding wire 16a continuous from the ball portion passes through the concave portion 19 and is second-bonded to the lead terminal 17. When the surface of the lead terminal 17 is higher than the height of the surface of the first semiconductor chip 10, the first bonding wire 16 a is connected to the first electrode 1.
2a, is led out laterally through the concave portion 19, rises outside the end of the second semiconductor chip 11, and rises in the lead terminal 1a.
7 Draw a locus that reaches the tip.

【００１８】この様に、凹部１９を設けることによっ
て、第１の半導体チップ１１へのワイヤボンディングを
可能にし、且つ第１のボンディングワイヤ１６ａが第２
の半導体チップ１１の裏面と接触することを回避してい
る。更に、第１のボンディングワイヤ１６ａを凹部１９
を通過させることによって、半導体装置全体の高さ（図
２：ｔ３）を薄くすることができる。As described above, by providing the concave portion 19, wire bonding to the first semiconductor chip 11 is enabled, and the first bonding wire 16a is
Contact with the back surface of the semiconductor chip 11 is avoided. Further, the first bonding wire 16a is
Allows the height of the entire semiconductor device (FIG. 2: t3) to be reduced.

【００１９】本実施の形態では、アイランド１３の板厚
が１５０〜２００μであり、第１と第２の半導体チップ
１０、１１の厚みがバックグラインド工程により２５０
〜３００μとなっている、接着剤１４、１５の厚みとし
て２０〜３０μ必要であり、更にはボンディングワイヤ
の上部に樹脂の残り厚みとして１５０〜２００μは必要
である。本願出願人は、これらの厚みを収納しつつ、パ
ッケージの高さｔ３を１．０ｍｍ以下にまで薄形化した
半導体装置を実現した。In the present embodiment, the island 13 has a thickness of 150 to 200 μm, and the first and second semiconductor chips 10 and 11 have a thickness of 250 μm by a back grinding process.
The thickness of the adhesives 14, 15 needs to be 20 to 30 .mu.m, and the remaining thickness of the resin above the bonding wire needs to be 150 to 200 .mu.m. The present applicant has realized a semiconductor device in which the height t3 of the package is reduced to 1.0 mm or less while accommodating these thicknesses.

【００２０】上記の凹部１９は、例えばウェハ裏面から
ハーフダイシングを行うことによって得ることができ
る。図４（Ａ）を参照して、第１主面３０と第２主面３
１とを有する半導体ウェハ３２を準備し、その第１主面
３０に回路素子を形成する。第２主面３１側からダイシ
ングラインを認識し、幅広（約１．０ｍｍ）の第１のダ
イシングブレード３３によって、全体のウェハ厚み２８
０μに対して１３０μの深さの溝３４を形成する。ダイ
シングブレード３３の中心線はダイシングラインの中心
線に一致する。次いで、図４（Ｂ）に示したように、ダ
イシングラインに沿って幅狭（約４０μｍ）の第２のダ
イシングブレード３５によってウェハ３２を完全に切断
する。尚、ハーフダイシングによる溝３４は、凹部１９
を設ける箇所だけでも良いし、半導体チップ１０、１１
の４辺全てに凹部１９を形成するように設けても良い。
また、第２のダイシングブレード３５は第１主面３０側
から切削する形態でも良いし、第２主面３１側から切削
する形態でも良い。The recess 19 can be obtained, for example, by performing half dicing from the back surface of the wafer. Referring to FIG. 4A, first main surface 30 and second main surface 3
1 is prepared, and a circuit element is formed on the first main surface 30 of the semiconductor wafer 32. The dicing line is recognized from the second main surface 31 side, and the entire wafer thickness 28 is reduced by the wide (about 1.0 mm) first dicing blade 33.
A groove 34 having a depth of 130 μ with respect to 0 μ is formed. The center line of the dicing blade 33 coincides with the center line of the dicing line. Next, as shown in FIG. 4B, the wafer 32 is completely cut by a narrow (about 40 μm) second dicing blade 35 along the dicing line. Note that the groove 34 formed by half dicing is
Or the semiconductor chips 10 and 11
May be provided so as to form the recess 19 on all four sides.
Further, the second dicing blade 35 may be cut from the first main surface 30 side, or may be cut from the second main surface 31 side.

【００２１】以下に、本発明の特徴となる、製造方法を
説明する。Hereinafter, a manufacturing method which is a feature of the present invention will be described.

【００２２】先ず図１（Ａ）を参照して、半導体チップ
を固着するためのアイランド１３と外部接続用のリード
端子１７を有するリードフレームを準備し、接着剤１４
によってアイランド１３の上に第１の半導体チップ１０
を固着する。接着剤１４はＡｇペーストのような導電性
あるいはエポキシ系の絶縁性の接着剤である。そして、
第１の半導体チップ１０の第１の電極１２ａとリード端
子１７とを第１のボンディングワイヤ１６ａで接続す
る。First, referring to FIG. 1A, a lead frame having an island 13 for fixing a semiconductor chip and a lead terminal 17 for external connection is prepared.
The first semiconductor chip 10 on the island 13
Is fixed. The adhesive 14 is a conductive or epoxy insulating adhesive such as an Ag paste. And
The first electrode 12a of the first semiconductor chip 10 and the lead terminal 17 are connected by a first bonding wire 16a.

【００２３】次いで、第１の半導体チップ１０の上に、
絶縁性の接着剤１５を塗布する。接着剤１５はエポキシ
系の粘性を持つ液状の接着剤であり、ディスペンサー５
０からあらかじめ定められた量を供給し、２００℃。数
十分のベーキング処理を行う。Next, on the first semiconductor chip 10,
An insulating adhesive 15 is applied. The adhesive 15 is a liquid adhesive having an epoxy-based viscosity.
Feed a predetermined amount from 0, 200 ° C. Perform baking treatment for several tens minutes.

【００２４】次に図１（Ｂ）を参照して、角錐コレット
２０によって、凹部１９を形成した第２の半導体チップ
１１を吸着する。角錐コレット２０は４角錐の斜面に沿
って傾斜する内壁を有しており、その内壁に第２の半導
体チップ１１の上端が線接触で接触し、図示せぬ真空装
置によって第２の半導体チップ１１を吸引保持してい
る。角錐コレット２０の周辺部分には前記内壁の延長上
に押圧部２１を具備しており、押圧部２１の先端は少な
くとも凹部１９より深い位置まで飛び出ており、且つ全
ての角が滑らかな曲面に形成されている。Next, referring to FIG. 1B, the second semiconductor chip 11 having the concave portion 19 is sucked by the pyramid collet 20. The pyramid collet 20 has an inner wall inclined along the slope of the quadrangular pyramid, and the upper end of the second semiconductor chip 11 is in line contact with the inner wall, and the second semiconductor chip 11 is contacted by a vacuum device (not shown). Is held by suction. The peripheral portion of the pyramid collet 20 is provided with a pressing portion 21 on the extension of the inner wall, and the tip of the pressing portion 21 protrudes at least to a position deeper than the concave portion 19, and all corners are formed into a smooth curved surface. Have been.

【００２５】次に図１（Ｃ）を参照して、角錐コレット
２０によって第２の半導体チップ１１を搬送し、第１の
半導体チップ１０の上に設置する。この時前記角錐コレ
ット２０によって第２の半導体チップ１１を数十ｇ／ｃ
ｍ２の圧力で下方に押し下げ、第１と第２の半導体チッ
プ１０、１１の間の接着剤１５が均等な厚みで広がるよ
うに第２の半導体チップ１１を固定する。固定すると同
時に、角錐コレット２０の押圧部２１が第１のボンディ
ングワイヤ１６ａに当接し、ループの高さを押し下げ
る。これによって、凹部１９において第１のボンディン
グワイヤ１６ａと第２の半導体チップ１１とが接触する
ことを回避することができる。そして角錐コレット２０
を解除して、接着剤１５に含まれる有機溶剤を蒸発させ
固化させるためのベーキング処理を２００℃、数十分行
う。Next, referring to FIG. 1C, the second semiconductor chip 11 is transported by the pyramid collet 20 and set on the first semiconductor chip 10. At this time, the second semiconductor chip 11 is tens of g / c by the pyramid collet 20.
The second semiconductor chip 11 is fixed so that the adhesive 15 between the first and second semiconductor chips 10 and 11 spreads with an even thickness by pressing down with a pressure of m2. At the same time as the fixing, the pressing portion 21 of the pyramid collet 20 comes into contact with the first bonding wire 16a to lower the height of the loop. Thereby, it is possible to prevent the first bonding wire 16a from coming into contact with the second semiconductor chip 11 in the concave portion 19. And the pyramid collet 20
Is released, and baking treatment for evaporating and solidifying the organic solvent contained in the adhesive 15 is performed at 200 ° C. for several tens of minutes.

【００２６】次に、第２の電極パッド１２ｂとリード端
子１７とをボールボンディングによりワイヤボンドし、
全体を樹脂モールドし、リードフレームから個々の半導
体装置を分離して製品が完成する。Next, the second electrode pad 12b and the lead terminal 17 are wire-bonded by ball bonding.
The whole is resin-molded, and individual semiconductor devices are separated from the lead frame to complete a product.

【００２７】尚、第２の半導体チップ１１をダイボンド
したときに、接着剤１５が凹部１９にまで拡大し、その
空間を満たすようにする事が可能である。望ましくは第
２の電極パッド１２ｂの直下全体まで拡大させる。する
と、固化した接着剤１５が第２のボンディングワイヤ１
６ｂをワイヤボンドするときの土台となり、ボンダビリ
ティを改善することができる。When the second semiconductor chip 11 is die-bonded, the adhesive 15 can extend to the recess 19 and fill the space. Desirably, it is expanded to the entire area immediately below the second electrode pad 12b. Then, the solidified adhesive 15 is applied to the second bonding wire 1.
6b can be used as a base for wire bonding and bondability can be improved.

【００２８】図５に第２の実施の形態を示した。リード
フレームに代えてテープキャリアと半田ボールを用いた
例である。第１の半導体チップ１０がポリイミド系のベ
ースフィルム４０の上に接着固定され、第１の半導体チ
ップ１０の上に第２の半導体チップ１１が固着される。
ベースフィルム４０の表面にはリード端子１７に相当す
る導電パターン４１が形成されており、第１と第２の電
極パッド１２ａ、１２ｂと導電パターン４１とが各々第
１と第２のボンディングワイヤ１６ａ、１６ｂで接続さ
れている。ベースフィルム４０には貫通穴が形成され、
該貫通穴を介して、ベースフィルム４０の裏面に形成し
た半田ボール４２と接続されている、そして、周囲を熱
硬化性の樹脂でモールドされている。FIG. 5 shows a second embodiment. This is an example in which a tape carrier and solder balls are used instead of the lead frame. The first semiconductor chip 10 is bonded and fixed on the polyimide base film 40, and the second semiconductor chip 11 is fixed on the first semiconductor chip 10.
A conductive pattern 41 corresponding to the lead terminal 17 is formed on the surface of the base film 40, and the first and second electrode pads 12a, 12b and the conductive pattern 41 are respectively connected to the first and second bonding wires 16a, 16b. A through hole is formed in the base film 40,
The through holes are connected to solder balls 42 formed on the back surface of the base film 40, and the periphery is molded with a thermosetting resin.

【００２９】尚、上記実施例は半導体チップが２個の場
合を記載したが、３個、４個を積層する場合でも同様に
実施できることは言うまでもない。Although the above embodiment has been described in connection with the case where there are two semiconductor chips, it goes without saying that the same operation can be performed when three or four semiconductor chips are stacked.

【００３０】[0030]

【発明の効果】以上に説明した通り、本発明によれば、
第２の半導体チップ１１の裏面を研削して凹部１９を設
け、凹部１９が形成する空間を利用して第１の電極１２
ａに第１のボンディングワイヤ１２ａをボンディングす
るので、半導体チップ１０、１１の大きさと形状が近似
した場合でも複数の半導体チップを積層してワイヤボン
ディングが可能になる利点を有する。これにより、例え
ば１つのパッケージに２倍の記憶容量を持たせることが
可能になる。As described above, according to the present invention,
The back surface of the second semiconductor chip 11 is ground to form a concave portion 19, and the first electrode 12 is formed using a space formed by the concave portion 19.
Since the first bonding wires 12a are bonded to a, there is an advantage that even when the sizes and shapes of the semiconductor chips 10 and 11 are similar, wire bonding can be performed by stacking a plurality of semiconductor chips. Thus, for example, one package can have twice the storage capacity.

【００３１】更に、凹部１９を利用することによって第
１のボンディングワイヤ１６ａのループ高さを吸収でき
るので、パッケージの厚みを薄形化できる利点を有す
る。Furthermore, since the loop height of the first bonding wire 16a can be absorbed by using the concave portion 19, the thickness of the package can be reduced.

【００３２】更に、角錐コレット２０の押圧部２１によ
って第１のボンディングワイヤ１６ａのループ高さを押
し下げられるので、第１のボンディングワイヤ１６ａと
第２の半導体チップ１１十の接触を回避することができ
る。しかも、第２の半導体チップ１１のダイボンド時に
同時に実行できるので、工程を増加させずに済む。Further, since the loop height of the first bonding wire 16a can be lowered by the pressing portion 21 of the pyramid collet 20, contact between the first bonding wire 16a and the second semiconductor chip 110 can be avoided. . In addition, since the process can be performed at the same time as the die bonding of the second semiconductor chip 11, the number of steps does not need to be increased.

【００３３】更に、半導体チップ１０、１１としてどの
ようなサイズ、形状のものでも組み合わせが可能にな
り、製品展開の自由度が増す利点をも有する。Further, any size and shape of the semiconductor chips 10 and 11 can be combined, and there is an advantage that the degree of freedom of product development is increased.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining the present invention.

【図２】凹部１９近傍を示す断面図である。FIG. 2 is a cross-sectional view showing the vicinity of a concave portion 19;

【図３】本発明を説明するための（Ａ）断面図、（Ｂ）
平面図である。FIGS. 3A and 3B are cross-sectional views for explaining the present invention; FIGS.
It is a top view.

【図４】凹部１９の製造方法を説明する断面図である。FIG. 4 is a cross-sectional view for explaining a method of manufacturing the recess 19;

【図５】本発明の、第２の実施の形態を示す断面図であ
る。FIG. 5 is a sectional view showing a second embodiment of the present invention.

【図６】従来例を説明するための断面図である。FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 あらかじめダイボンドとワイヤボンドを
施した第１の半導体チップの上に第２の半導体チップを
ダイボンドする半導体装置の製造方法であって、 前記第２の半導体チップを吸着し搬送するコレットに押
圧部を設け、前記第２の半導体チップを前記第１の半導
体チップの上に固定すると同時に前記コレットの押圧部
が前記第１の半導体チップのボンディングワイヤのルー
プを押し下げるようにしたことを特徴とする半導体装置
の製造方法。1. A method of manufacturing a semiconductor device in which a second semiconductor chip is die-bonded on a first semiconductor chip which has been subjected to die bonding and wire bonding in advance, wherein the collet sucks and transports the second semiconductor chip. Wherein a pressing portion is provided, and the second semiconductor chip is fixed on the first semiconductor chip, and at the same time, the pressing portion of the collet presses down a loop of a bonding wire of the first semiconductor chip. Manufacturing method of a semiconductor device. 【請求項２】 前記第２の半導体チップの裏面に凹部を
形成し、前記凹部の空間内に前記第１の半導体チップの
ボンディングワイヤが延在することを特徴とする半導体
装置の製造方法。2. A method of manufacturing a semiconductor device, comprising: forming a concave portion on a back surface of the second semiconductor chip; and bonding wires of the first semiconductor chip extending in a space of the concave portion. 【請求項３】 前記凹部が裏面からのハーフダイシング
によって得られたものであることを特徴とする請求項１
記載の半導体装置の製造方法。3. The method according to claim 1, wherein the concave portion is obtained by half dicing from a back surface.
The manufacturing method of the semiconductor device described in the above.
JP10257029A 1998-09-10 1998-09-10 Manufacture of semiconductor device Pending JP2000091355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10257029A JP2000091355A (en) 1998-09-10 1998-09-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10257029A JP2000091355A (en) 1998-09-10 1998-09-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JP2000091355A true JP2000091355A (en) 2000-03-31

Family

ID=17300763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10257029A Pending JP2000091355A (en) 1998-09-10 1998-09-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JP2000091355A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002203939A (en) * 2000-12-27 2002-07-19 Sony Corp Integrated electronic component and its integrating method
JP2003318204A (en) * 2002-04-23 2003-11-07 Matsushita Electric Ind Co Ltd Nozzle for chip suction, chip mounter and chip mounting method
DE10342768A1 (en) * 2003-09-16 2005-04-21 Disco Hi Tec Europ Gmbh Semiconductor chip for chip stack provided with active side and rear side with integral spacer element
JP2005328005A (en) * 2004-05-17 2005-11-24 Seiko Epson Corp Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002203939A (en) * 2000-12-27 2002-07-19 Sony Corp Integrated electronic component and its integrating method
JP4501279B2 (en) * 2000-12-27 2010-07-14 ソニー株式会社 Integrated electronic component and method for integrating the same
JP2003318204A (en) * 2002-04-23 2003-11-07 Matsushita Electric Ind Co Ltd Nozzle for chip suction, chip mounter and chip mounting method
DE10342768A1 (en) * 2003-09-16 2005-04-21 Disco Hi Tec Europ Gmbh Semiconductor chip for chip stack provided with active side and rear side with integral spacer element
JP2005328005A (en) * 2004-05-17 2005-11-24 Seiko Epson Corp Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP4544407B2 (en) * 2004-05-17 2010-09-15 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus

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