DE10342768A1 - Semiconductor chip for chip stack provided with active side and rear side with integral spacer element - Google Patents

Semiconductor chip for chip stack provided with active side and rear side with integral spacer element Download PDF

Info

Publication number
DE10342768A1
DE10342768A1 DE10342768A DE10342768A DE10342768A1 DE 10342768 A1 DE10342768 A1 DE 10342768A1 DE 10342768 A DE10342768 A DE 10342768A DE 10342768 A DE10342768 A DE 10342768A DE 10342768 A1 DE10342768 A1 DE 10342768A1
Authority
DE
Germany
Prior art keywords
semiconductor chip
spacer element
rear side
chip
integral spacer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10342768A
Other languages
German (de)
Inventor
Karl-Heinz Priewasser
Sylvia Winter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Disco Hi Tec Europe GmbH
Original Assignee
Infineon Technologies AG
Disco Hi Tec Europe GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, Disco Hi Tec Europe GmbH filed Critical Infineon Technologies AG
Priority to DE10342768A priority Critical patent/DE10342768A1/en
Publication of DE10342768A1 publication Critical patent/DE10342768A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Die Bonding (AREA)

Abstract

The semiconductor chip has a base body (1) provided with an active side (2) and a rear side having an integral spacer element (3), which is set inwards from the peripheral edge (4) of the semiconductor chip. An independent claim for a manufacturing method for semiconductor chips is also included.
DE10342768A 2003-09-16 2003-09-16 Semiconductor chip for chip stack provided with active side and rear side with integral spacer element Ceased DE10342768A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10342768A DE10342768A1 (en) 2003-09-16 2003-09-16 Semiconductor chip for chip stack provided with active side and rear side with integral spacer element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10342768A DE10342768A1 (en) 2003-09-16 2003-09-16 Semiconductor chip for chip stack provided with active side and rear side with integral spacer element

Publications (1)

Publication Number Publication Date
DE10342768A1 true DE10342768A1 (en) 2005-04-21

Family

ID=34352865

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10342768A Ceased DE10342768A1 (en) 2003-09-16 2003-09-16 Semiconductor chip for chip stack provided with active side and rear side with integral spacer element

Country Status (1)

Country Link
DE (1) DE10342768A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091355A (en) * 1998-09-10 2000-03-31 Sanyo Electric Co Ltd Manufacture of semiconductor device
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
US20020096755A1 (en) * 2001-01-24 2002-07-25 Yasuki Fukui Semiconductor device
US20020160025A1 (en) * 2000-01-18 2002-10-31 Marina Mustapic Cosmetic preparations for skin and hair care
US20030062613A1 (en) * 2001-09-13 2003-04-03 Kenji Masumoto Semiconductor device and manufacturing method thereof
WO2003060006A1 (en) * 2002-01-14 2003-07-24 Crompton Corporation Composition of pvc and carbon monoxide-modified ethylene-vinyl ester copolymer with improved colour stability

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091355A (en) * 1998-09-10 2000-03-31 Sanyo Electric Co Ltd Manufacture of semiconductor device
US20020160025A1 (en) * 2000-01-18 2002-10-31 Marina Mustapic Cosmetic preparations for skin and hair care
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
US20020096755A1 (en) * 2001-01-24 2002-07-25 Yasuki Fukui Semiconductor device
US20030062613A1 (en) * 2001-09-13 2003-04-03 Kenji Masumoto Semiconductor device and manufacturing method thereof
WO2003060006A1 (en) * 2002-01-14 2003-07-24 Crompton Corporation Composition of pvc and carbon monoxide-modified ethylene-vinyl ester copolymer with improved colour stability

Similar Documents

Publication Publication Date Title
USD472528S1 (en) Semiconductor chip package
NL1027962A1 (en) Multi-chip package, semiconductor device used therein and method of manufacture therefor.
USD466873S1 (en) Semiconductor chip package
WO2002062527A8 (en) Abrasive article suitable for modifying a semiconductor wafer
TW200509391A (en) A device having multiple silicide types and a method for its fabrication
EP1335411A3 (en) Semiconductor wafer having a thin die and tethers and method therefor
TWI264756B (en) Semiconductor device
WO2003036715A3 (en) Adhesive wafers for die attach application
WO2007061558A3 (en) Semiconductor die package using leadframe and clip and method of manufacturing
AU2003236002A1 (en) Method for manufacturing semiconductor chip
AU2003211575A1 (en) Semiconductor substrate, semiconductor chip, and semiconductor device manufacturing method
WO2007011511A3 (en) Die package with asymmetric leadframe connection
TW200507193A (en) Adhesive sheet for dicing and die bonding and method of manufacturing semiconductor device
WO2007047058A3 (en) Semiconductor die having a protective periphery region and method for forming
TW200615107A (en) Release film for encapsulation of semiconductor chip
TW200719489A (en) Chip structure and manufacturing method of the same
AU2003206338A1 (en) Semiconductor fabrication process, lateral pnp transistor, and integrated circuit
WO2003014242A1 (en) Pressure sensitive adhesive double coated tape and method for producing ic chip using it
TW200603307A (en) Multiple device package
MY119889A (en) Planarized plastic package modules for integrated circuits
AU2002365007A1 (en) Smart card
DE10342768A1 (en) Semiconductor chip for chip stack provided with active side and rear side with integral spacer element
USD492266S1 (en) Portion of a matrix for surface mount package leadframe
USD494939S1 (en) Portion of a matrix for surface mount package leadframe
USD484858S1 (en) Portion of a matrix for surface mount package leadframe

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection