JP2000124390A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JP2000124390A JP2000124390A JP28985598A JP28985598A JP2000124390A JP 2000124390 A JP2000124390 A JP 2000124390A JP 28985598 A JP28985598 A JP 28985598A JP 28985598 A JP28985598 A JP 28985598A JP 2000124390 A JP2000124390 A JP 2000124390A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- tab
- lead
- package
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＩＣパッケージの内
部構造に関する。The present invention relates to an internal structure of an IC package.
【０００２】[0002]
【従来の技術】図４に示すように、リードフレームのタ
ブ３１の一方の側（図では、上方向）にのみＩＣチップ
３５が搭載されている。すなわち、リードフレームのタ
ブ３１の片側にのみＩＣチップ３５が接着され、ＩＣチ
ップ３５とリード３２は金属ワイヤ３７で電気的に接続
されている。なお、リード３２とタブ３１は、リードフ
レームとして一体に形成されているものを、抜きにより
分断され、電気的に絶縁される。2. Description of the Related Art As shown in FIG. 4, an IC chip 35 is mounted only on one side (upward in the figure) of a tab 31 of a lead frame. That is, the IC chip 35 is adhered to only one side of the tab 31 of the lead frame, and the IC chip 35 and the lead 32 are electrically connected by the metal wire 37. Note that the lead 32 and the tab 31 that are integrally formed as a lead frame are separated by cutting and electrically insulated.
【０００３】[0003]
【発明が解決しようとする課題】リードフレームのタブ
３１の片側にのみＩＣチップ３５が搭載されているの
で、ＩＣパッケージ一個当りの集積度が限定されるとい
う問題点があった。Since the IC chip 35 is mounted on only one side of the tab 31 of the lead frame, there is a problem that the degree of integration per IC package is limited.
【０００４】[0004]
【課題を解決するための手段】上記の問題点を解決する
ために、本発明はリードフレームのタブの片側面にリー
ドの配線を付着する構造とし、この側にはバンプを有す
るＩＣチップを搭載し、もう一方の側面にはＩＣチップ
の裏側を接着しワイヤを介してＩＣチップの表側とリー
ドを接続する。In order to solve the above problems, the present invention has a structure in which lead wiring is attached to one side of a tab of a lead frame, and an IC chip having bumps is mounted on this side. Then, the back side of the IC chip is bonded to the other side surface, and the lead and the front side of the IC chip are connected via a wire.
【０００５】[0005]
【発明の実施の形態】本発明は、２個のＩＣをひとつの
ＩＣパッケージに搭載するための構造を提供するもので
ある。以下にこの発明の実施例を図面に基づいて説明す
る。図１は、本発明の構造を示すＩＣパッケージの断面
図を示す。リードフレームのタブ１に複数のリード２が
付着している。タブ１は、第一のＩＣチップ３及び第二
のＩＣチップ５を載置するものである。つまり、タブ１
には、その平面の端部から、放射状に複数のリード２が
取り付けられている。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a structure for mounting two ICs on one IC package. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an IC package showing the structure of the present invention. A plurality of leads 2 are attached to a tab 1 of the lead frame. The tab 1 places the first IC chip 3 and the second IC chip 5 thereon. That is, tab 1
, A plurality of leads 2 are attached radially from the end of the plane.
【０００６】各リード２は、それぞれ電気的に独立して
いなければならないので、一般には、タブ１とリード２
は電気的に絶縁されている。リード２に第一のＩＣチッ
プ３がバンプ４、４で接続されている。バンプ４、４は
金属などの導電性の材料であり、第一のチップ３のＩＣ
内部の回路と外部とが、バンプ４、４とリード２、２を
介して導通している。また第一のＩＣチップはバンプ
４、４によりリード２、２に支えられている。Since each lead 2 must be electrically independent from each other, generally, the tab 1 and the lead 2
Are electrically insulated. A first IC chip 3 is connected to the lead 2 by bumps 4, 4. The bumps 4 and 4 are made of a conductive material such as a metal, and the IC of the first chip 3
The internal circuit and the outside are electrically connected via the bumps 4 and 4 and the leads 2 and 2. The first IC chip is supported by the leads 2 and 2 by the bumps 4 and 4.
【０００７】第二のＩＣチップ５の裏側はタブ１に取り
付けられている。第二のＩＣチップ５の表側はＩＣの回
路が形成されていて、第二のＩＣチップ５の配線パッド
６、６とリード２、２は金属ワイヤ７、７を通して電気
的に接続されている。図面の制約上リードは２本しか示
していないため第一のチップと第二のチップがリードで
接続しているように記載しているが、第一のＩＣチップ
３と第二のＩＣチップ５と電気的に接続する必要がなけ
れば、別のリード２に接続する事は当然である。また、
第一のチップ３のバンプ４、４および第二のチップ５の
配線パッド６、６はチップの種類に応じて多数存在する
事は当然である。The back side of the second IC chip 5 is attached to the tab 1. An IC circuit is formed on the front side of the second IC chip 5, and the wiring pads 6, 6 and the leads 2, 2 of the second IC chip 5 are electrically connected through metal wires 7, 7. Although only two leads are shown due to restrictions in the drawing, the first chip and the second chip are described as being connected by leads, but the first IC chip 3 and the second IC chip 5 If it is not necessary to electrically connect to another lead 2, it is natural to connect to another lead 2. Also,
It goes without saying that a large number of bumps 4 and 4 of the first chip 3 and a large number of wiring pads 6 and 6 of the second chip 5 exist according to the type of chip.
【０００８】また、それに応じてリード２、２が多数存
在する事も当然となる。第一のＩＣチップ３および第二
のＩＣチップ５およびリード２、２の一部および金属ワ
イヤ７、７は樹脂８で保護、固定されている。図２に、
本発明の構造をよりわかりやすく描写するために透視斜
視図を示す。なお、図２の上下は、図１とは逆に描かれ
ている。リードフレームのタブ１にリード２が取り付け
られている。リード２の一部と第一のＩＣチップ３はバ
ンプ４を介して接続されている。第二のＩＣチップ５
は、その裏側でタブ１に接着・固定されている。第二の
ＩＣチップ５の表側の配線パッド６とリード２の一部は
金属ワイヤ７を介して接続されている。２つのＩＣチッ
プ３、５は樹脂８で覆われていて、ＩＣ回路及び金属ワ
イヤ７を外部環境から保護している。It is natural that a large number of leads 2 and 2 exist accordingly. The first IC chip 3, the second IC chip 5, a part of the leads 2, 2, and the metal wires 7, 7 are protected and fixed by a resin 8. In FIG.
FIG. 2 shows a perspective perspective view to better illustrate the structure of the present invention. Note that the upper and lower sides of FIG. 2 are drawn in reverse to FIG. A lead 2 is attached to a tab 1 of the lead frame. Part of the leads 2 and the first IC chip 3 are connected via bumps 4. Second IC chip 5
Is adhered and fixed to the tab 1 on the back side. A wiring pad 6 on the front side of the second IC chip 5 and a part of the lead 2 are connected via a metal wire 7. The two IC chips 3 and 5 are covered with a resin 8 to protect the IC circuit and the metal wires 7 from the external environment.
【０００９】図１において、一般にはタブ１とリード２
は電気的に絶縁していることを述べたが、その内容につ
いて詳細に説明する。第一に、図１において、タブ１を
絶縁体材料で形成し、リード２をタブ１に接着すること
により、第一のＩＣチップの基板とリード２は電気的に
絶縁される。次に、図３に示すように金属ワイヤ７、７
で接続された第二のＩＣチップ５を搭載する側のタブ１
の材質は導電体材料５１であり、リード２が接着してい
る側のタブ１の材質５２は絶縁体材料とした。第一のＩ
Ｃチップ３は、図１にて説明したようにパッド４を介し
て、リード２に取り付けられている。すなわちタブ１を
二層の構造とする方法である。これにより、第一のＩＣ
チップ３の基板はタブ１と電気的導通を取ることができ
る。In FIG. 1, a tab 1 and a lead 2 are generally used.
Has stated that it is electrically insulated, but its contents will be described in detail. First, in FIG. 1, the tab 1 is formed of an insulating material, and the lead 2 is bonded to the tab 1, so that the substrate of the first IC chip and the lead 2 are electrically insulated. Next, as shown in FIG.
Tab 1 on the side on which the second IC chip 5 is connected, which is connected by
Is a conductor material 51, and a material 52 of the tab 1 on the side to which the lead 2 is adhered is an insulator material. The first I
The C chip 3 is attached to the lead 2 via the pad 4 as described with reference to FIG. That is, the tab 1 has a two-layer structure. Thereby, the first IC
The substrate of the chip 3 can be electrically connected to the tab 1.
【００１０】これらの場合、タブ１を形成している絶縁
体材料は高熱伝導体材料であれば、ＩＣの発熱に対して
熱放散しやすくなりＩＣの品質をさらに高めることがで
きる。たとえば、高熱伝導体材料としてダイヤモンド、
窒化アルミニウム、セラミック、高熱伝導プラスチック
などが挙げられる。さらに今までは、リード２がタブ１
に接着している場合について述べたが、リード２はタブ
２に接着しないで自由な状態であっても良い。In these cases, if the insulating material forming the tab 1 is a high thermal conductive material, heat is easily dissipated with respect to heat generated by the IC, so that the quality of the IC can be further improved. For example, diamond as a high thermal conductor material,
Examples include aluminum nitride, ceramic, and high thermal conductive plastic. Until now, lead 2 was tab 1
Although the description has been given of the case where the leads 2 are bonded, the leads 2 may be in a free state without being bonded to the tabs 2.
【００１１】次に本発明の製造方法について、図１に基
づいて説明する。リード２、２とタブ１からなるリード
フレームの上に接着材をつけて第二のＩＣチップ５をの
せる。次にワイヤ７、７をリード２、２に付着する。リ
ード２、第二のＩＣチップ５に対する接着を良好にする
には、タブ１およびリード２、２に合わせた台と押えを
使ったワイヤボンダが望ましい。Next, the manufacturing method of the present invention will be described with reference to FIG. The second IC chip 5 is mounted on the lead frame including the leads 2 and 2 and the tab 1 with an adhesive. Next, the wires 7 are attached to the leads 2. In order to improve the adhesion to the lead 2 and the second IC chip 5, a wire bonder using a table and a holder corresponding to the tab 1 and the leads 2 and 2 is desirable.
【００１２】次に第一のＩＣチップ３のバンプ４、４に
合わせてリード２，２を接着する。ここでは第二のＩＣ
チップ５を先に付けたが、バンプつきの第一のＩＣチッ
プ３を先に付けても良い。バンプ４、４がＰｂ-Ｓｎの
共晶半田の場合は融点が低いために、ワイヤボンディン
グする時の熱でバンプ４、４とリード２．２が反応しす
ぎたり、バンプ４、４が融けすぎて流れ出さないように
最適化する必要がある。Next, the leads 2 and 2 are bonded to the bumps 4 and 4 of the first IC chip 3. Here is the second IC
Although the chip 5 is attached first, the first IC chip 3 with bumps may be attached first. When the bumps 4 and 4 are Pb-Sn eutectic solder, the melting point is low, so that the heat during wire bonding causes the bumps 4 and 4 and the lead 2.2 to react too much or the bumps 4 and 4 to melt too much. Need to be optimized so that it does not flow out.
【００１３】この事と先に述べたワイヤボンディングの
押えの複雑さをなくすためには、ワイヤボンディングを
先に行う方法が簡便である。次に、上記ＩＣチップ３、
５およびワイヤ７、７のまわりをモールド材料８で覆い
リード切断・成形してＩＣパッケージが完成する。In order to eliminate this and the complexity of the wire bonding press described above, a method of performing the wire bonding first is simple. Next, the IC chip 3,
5 and the wires 7, 7 are covered with a molding material 8 and the leads are cut and molded to complete an IC package.
【００１４】[0014]
【発明の効果】以上、説明したようにＩＣパッケージの
中に、リードフレームのタブを挟んで２個のＩＣチップ
を搭載するので、従来に比べて２倍の集積度を持ったＩ
Ｃパッケージを作ることができる。さらにリードはタブ
と接着されしっかり固定されているため、リードに対し
てワイヤボンディングがしっかり行う事ができ、かつバ
ンプ接続も簡単に行うことができる。As described above, since two IC chips are mounted in the IC package with the tab of the lead frame interposed therebetween, an IC having twice the integration density as compared with the conventional one is provided.
C package can be made. Furthermore, since the lead is adhered to the tab and firmly fixed, wire bonding can be performed firmly on the lead, and bump connection can be easily performed.
【図１】図１は、本発明のＩＣパッケージの内部構造を
示す断面図である。FIG. 1 is a sectional view showing an internal structure of an IC package according to the present invention.
【図２】図２は、本発明のＩＣパッケージの内部構造を
示す透視見取り図である。FIG. 2 is a perspective view showing the internal structure of the IC package of the present invention.
【図３】図３は、本発明の第２の実施例を示す断面図で
ある。FIG. 3 is a sectional view showing a second embodiment of the present invention.
【図４】図４は、従来にＩＣパッケージの内部構造を示
す断面図である。FIG. 4 is a cross-sectional view showing the internal structure of a conventional IC package.
１ リードフレームのタブ ２ リードフレームのリード ３ 第一のＩＣチップ ４ バンプ ５ 第二のＩＣチップ ６ 配線パッド ７ 金属ワイヤ ８ 樹脂 REFERENCE SIGNS LIST 1 lead frame tab 2 lead frame lead 3 first IC chip 4 bump 5 second IC chip 6 wiring pad 7 metal wire 8 resin
Claims (6)
リードを付着しているリードフレームを用いて、タブの
裏側にはバンプを有するＩＣチップがバンプを介してリ
ードに接着し、タブの表側にはＩＣチップの裏側が接着
し、前期タブの表側のＩＣチップの配線パッドとリード
とはワイヤで結ばれている事を特徴とするＩＣパッケー
ジ。An IC chip having bumps is adhered to the leads via bumps on the back side of the tab by using a lead frame having wiring leads attached to the back side of the tab on which the IC chip is mounted. The IC package is characterized in that the back side of the IC chip is adhered to the IC chip, and the wiring pads and the leads of the IC chip on the front side of the tab are connected by wires.
気的に絶縁している事を特徴とする特許請求の範囲第一
項記載のＩＣパッケージ。2. The IC package according to claim 1, wherein the tab on which the IC chip is mounted and the lead are electrically insulated.
縁性を有した材料である事を特徴とする特許請求の範囲
第一項記載のＩＣパッケージ。3. The IC package according to claim 1, wherein the tab on which the IC chip is mounted is made of an electrically insulating material.
と絶縁体材料の二層構造であり、リードは前記絶縁体材
料の側に接着している事を特徴とする特許請求の範囲第
一項記載のＩＣパッケージ。4. A tab on which an IC chip is mounted has a two-layer structure of a conductor material and an insulator material, and a lead is adhered to the insulator material side. The IC package according to the item.
である事を特徴とする特許請求の範囲第一項記載のＩＣ
パッケージ。5. The IC according to claim 1, wherein the tab on which the IC chip is mounted is made of a high thermal conductor.
package.
い、次にバンプ接続する場合を行う事を特徴とする特許
請求の範囲第一項記載のＩＣパッケージの製造方法。6. The method for manufacturing an IC package according to claim 1, wherein the case of performing wire bonding is performed first, and then the case of performing bump connection is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28985598A JP2000124390A (en) | 1998-10-12 | 1998-10-12 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28985598A JP2000124390A (en) | 1998-10-12 | 1998-10-12 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000124390A true JP2000124390A (en) | 2000-04-28 |
Family
ID=17748643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28985598A Pending JP2000124390A (en) | 1998-10-12 | 1998-10-12 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000124390A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013058530A (en) * | 2011-09-07 | 2013-03-28 | Toppan Printing Co Ltd | Multi-chip composite lead frame and semiconductor device |
-
1998
- 1998-10-12 JP JP28985598A patent/JP2000124390A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013058530A (en) * | 2011-09-07 | 2013-03-28 | Toppan Printing Co Ltd | Multi-chip composite lead frame and semiconductor device |
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