JP2000114362A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JP2000114362A
JP2000114362A JP10281574A JP28157498A JP2000114362A JP 2000114362 A JP2000114362 A JP 2000114362A JP 10281574 A JP10281574 A JP 10281574A JP 28157498 A JP28157498 A JP 28157498A JP 2000114362 A JP2000114362 A JP 2000114362A
Authority
JP
Japan
Prior art keywords
film
trench
trenches
sog
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10281574A
Other languages
Japanese (ja)
Inventor
Hideaki Onishi
秀明 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10281574A priority Critical patent/JP2000114362A/en
Publication of JP2000114362A publication Critical patent/JP2000114362A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent degradation in shape due to wet etching during a device process, by filling element isolation trenches partway in the direction of the depth of the trenches by SOG, and filling the upper part of the trenches with an oxide film by CVD when the trenches are filled with an oxide film. SOLUTION: A SiO2 film 2 is formed on a Si substrate 1 by thermal oxidation, and a SiN film 3 is formed on the SiO2 film 2. The SiN film 3, SiO2 film 2, and Si substrate 1 are anisotropically etched, respectively, to form isolating trenches. An SiO2 film 4 is formed in the trenches, a SOG solution is then applied, and the trenches are filled by SOG partway in the direction of the depth of the trenches to form a SOG film 5. Subsequently, the upper part of the interior of the trenches is subjected to CVD at a high a temperature as 800 deg.C or so using silane gas, an HTO film 6 forming an oxide film is thereby formed, and the trenches are filled.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、トレンチ分離工程
を有する半導体装置の製造方法に関し、詳しくは、良好
なトレンチ分離形状が得られるように改良された半導体
装置の製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor device having a trench isolation step, and more particularly to a method of manufacturing a semiconductor device improved so as to obtain a good trench isolation shape.

【0002】[0002]

【従来の技術】本発明が関する半導体装置の製造方法で
は、良好なトレンチ分離形状が得られることが重要な要
素の一つとなっている。
2. Description of the Related Art In a method of manufacturing a semiconductor device according to the present invention, obtaining a good trench isolation shape is one of the important factors.

【0003】この目的のために、通常埋め込み性が比較
的良く、熱酸化膜に近い膜質のトレンチ埋め込み酸化膜
を得る方法として、HDP−CVDを用いる方法があ
る。しかしながら、この方法では、トレンチ分離幅20
0nm以下でアスペクト比3以上の高アスペクト比のト
レンチの埋め込みを行うと、図5の様に十分な埋め込み
性が得られず、素子分離特性の悪化を招くことになる。
[0003] For this purpose, there is a method using HDP-CVD as a method for obtaining a trench buried oxide film having a film quality close to that of a thermal oxide film, usually having a relatively good burying property. However, in this method, the trench isolation width 20
When a trench having a high aspect ratio of not less than 0 nm and an aspect ratio of 3 or more is buried, a sufficient burying property cannot be obtained as shown in FIG. 5, resulting in deterioration of element isolation characteristics.

【0004】また埋め込み性良く酸化膜を形成する方法
としては、塗布膜であるSOGを用いて酸化膜を形成す
る方法がある。この方法によれば、上記のような高アス
ペクト比のトレンチの埋め込みが可能となるが、図6に
示すように、トレンチと他の部分との間に大きい段差が
生じるという欠点がある。
As a method of forming an oxide film with good burying property, there is a method of forming an oxide film using SOG as a coating film. According to this method, a trench having a high aspect ratio as described above can be buried, but there is a drawback that a large step is generated between the trench and other portions as shown in FIG.

【0005】さらに特公平7−077231号公報に
は、半導体装置のトレンチ分離方法が開示されている。
この公知の方法においては、アスペクト比の大きいトレ
ンチを隙間なく埋め込むために、基板上に下敷酸化膜、
窒化膜を成長後、それらの膜にトレンチパターンを開口
し、窒化膜をマスクにトレンチを掘削し、トレンチ表面
を酸化した後、SOGを塗布、エッチバックし、トレン
チ表面近くまでSOGがトレンチを埋め込む構造とす
る。その後、ウェットエッチング耐性の良いHTO膜を
CBDにより成長させ、初期に設けた酸化膜、窒化膜を
除去し、基板表面を酸化することにより、トレンチ分離
を有する、段差の小さい基板が得られる。
Further, Japanese Patent Publication No. 7-077231 discloses a trench isolation method for a semiconductor device.
In this known method, in order to bury a trench having a large aspect ratio without a gap, an underlying oxide film,
After the nitride films are grown, trench patterns are opened in those films, trenches are excavated using the nitride film as a mask, and after oxidizing the trench surface, SOG is applied and etched back, and SOG fills the trench to near the trench surface. Structure. Thereafter, an HTO film having good wet etching resistance is grown by CBD, an oxide film and a nitride film provided at an initial stage are removed, and the substrate surface is oxidized, whereby a substrate having a trench isolation and a small step is obtained.

【0006】[0006]

【発明が解決しようとする課題】しかしSOG膜は、ウ
エットエッチング耐性が弱いために、デバイスプロセス
中のウエットエッチング工程により、図3のように大き
くエッチングされ、トレンチ分離の形状が悪化し、素子
特性に悪影響を及ぼす。またSOG膜は金属等の不純物
を多く含む膜であり、トレンチ表面にSOG膜がむき出
しの状態では、ゲート酸化工程等への悪影響を及ぼすお
それがある。
However, since the SOG film has poor wet etching resistance, the SOG film is largely etched as shown in FIG. 3 by a wet etching step in a device process, and the shape of the trench isolation deteriorates. Adversely affect The SOG film is a film containing a large amount of impurities such as metal, and if the SOG film is exposed on the trench surface, there is a possibility that the SOG film has a bad influence on a gate oxidation step and the like.

【0007】本発明の主な目的は、埋め込み性の良いト
レンチ分離を形成する半導体装置の製造方法を提供する
ことにある。
A main object of the present invention is to provide a method of manufacturing a semiconductor device for forming a trench isolation having good burying properties.

【0008】本発明の他の目的は、エッチング耐性が強
いトレンチ分離を形成し、プロセス安定性の高い半導体
装置の製造方法を提供することにある。
Another object of the present invention is to provide a method of manufacturing a semiconductor device having high process stability by forming a trench isolation having high etching resistance.

【0009】[0009]

【課題を解決するための手段】本発明の特徴は、トレン
チ素子分離の埋め込み工程において、トレンチの深さ方
向の途中までSOGを用いた酸化膜を形成し、トレンチ
の上部の埋め込みはCVD法による酸化膜で形成するこ
とにある。
A feature of the present invention is that in an embedding step of trench element isolation, an oxide film using SOG is formed halfway in the depth direction of the trench, and the upper portion of the trench is embedded by a CVD method. It is to be formed by an oxide film.

【0010】すなわち本発明による製造方法において
は、トレンチ素子分分離の酸化膜による埋め込みを行う
際、トレンチの深さ方向の途中までSOGで埋め込み、
トレンチの上部は、CVDによる酸化膜としてSiO2
膜例えばHTO膜により埋め込みを行う。
In other words, in the manufacturing method according to the present invention, when burying with an oxide film for separating the trench elements, burying with SOG is performed halfway in the depth direction of the trench.
The upper part of the trench is made of SiO 2 as an oxide film by CVD.
The filling is performed by a film, for example, an HTO film.

【0011】このようにSOGを用いてトレンチ上部の
埋め込みを行うことにより、アスペクト比の高いトレン
チの埋め込みを行うことが容易となり、かつトレンチ上
部の埋め込みを膜質、特にウエットエッチング耐性の良
いHTO膜等のCVD膜で形成することで、デバイスプ
ロセス中でのウエットエッチングによる形状悪化を防ぐ
役目を果たす。
By burying the upper part of the trench by using SOG in this way, it becomes easy to bury the trench having a high aspect ratio, and the burying of the upper part of the trench can be performed with a film quality, in particular, an HTO film or the like having good wet etching resistance. By using a CVD film, a role of preventing shape deterioration due to wet etching during a device process can be achieved.

【0012】従って、埋め込み性が良くかつプロセス安
定性の高いトレンチ分離がアスペクト比が高いトレンチ
でも実現出来るという効果が得られる。
Therefore, an effect is obtained that trench isolation having good burying property and high process stability can be realized even in a trench having a high aspect ratio.

【0013】[0013]

【発明の実施の形態】本発明を図面を参照して説明す
る。図1(a)乃至図4(j)は、本発明の一実施の形
態における工程断面図を示している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. 1 (a) to 4 (j) are cross-sectional views showing the steps in an embodiment of the present invention.

【0014】まず、Si基板1上に、熱酸化によりSi
2膜2を例えば10nmの厚さで形成し、CVD法に
よりSiN膜3を例えば150nmの厚さで形成する。
そしてリソグラフィー工程を用いてSiN膜3、SiO
2膜2、Si基板1をそれぞれ異方性エッチングにより
エッチングし、トレンチ分離の溝を例えば幅200n
m、深さ500nmで形成する(図1(a))。
First, a Si substrate 1 is formed on a Si substrate 1 by thermal oxidation.
The O 2 film 2 is formed with a thickness of, for example, 10 nm, and the SiN film 3 is formed with a thickness of, for example, 150 nm by a CVD method.
Then, using a lithography process, the SiN film 3, SiO 2
2 The film 2 and the Si substrate 1 are respectively etched by anisotropic etching, and trenches for trench isolation are formed,
m and a depth of 500 nm (FIG. 1A).

【0015】そしてエッチングダメージ緩和のために、
熱酸化によりトレンチ内部にSiO 2膜4を形成する
(図1(b))。
In order to reduce etching damage,
SiO inside the trench by thermal oxidation TwoForm the film 4
(FIG. 1 (b)).

【0016】ついでSOG溶液を塗布し、例えば400
℃でベークを行ってSOG膜5を形成する(図2
(c))。SOG膜5は、このように溶液を塗布するこ
とにより形成するので、本例の様なアスペクト比の高い
トレンチ内部にも埋め込み性良く膜形成できる。次にS
i基板表面から100nm程度の深さまで、異方性ドラ
イエッチングによりSOG膜5のエッチバックを行う
(図2(d))。
Then, an SOG solution is applied, for example, 400
The baking is performed at a temperature of about 100 ° C. to form the SOG film 5 (FIG. 2).
(C)). Since the SOG film 5 is formed by applying the solution as described above, the SOG film 5 can be formed with a good burying property even in a trench having a high aspect ratio as in this example. Then S
The SOG film 5 is etched back by anisotropic dry etching to a depth of about 100 nm from the i-substrate surface (FIG. 2D).

【0017】次に、トレンチの溝の上部100nmを、
シラン系ガスを用いて800℃程度の高温でCVDを行
うことにより、酸化膜形成を行うことによる、いわゆる
HTO膜6を200nmの厚さで形成することにより埋
め込みを行う(図2(e))。
Next, the upper 100 nm of the trench is
By performing CVD at a high temperature of about 800 ° C. using a silane-based gas to form an oxide film, a so-called HTO film 6 having a thickness of 200 nm is filled (FIG. 2E). .

【0018】このHTO膜6は、ウエットエッチング耐
性も高く、かつ金属不純物等が混入しにくいことで知ら
れている。そしてCMPにより、SiN上の余分なHT
O膜6は除去される(図3(f))。
The HTO film 6 is known to have high wet etching resistance and to be hardly mixed with metal impurities and the like. Then, extra HT on SiN is formed by CMP.
The O film 6 is removed (FIG. 3F).

【0019】ついで、ウェットエッチングにより、Si
N膜3とSiO2膜2を除去し(図3(g))、熱酸化
によりウェルやチャネル形成のイオン注入のマスクとな
るSiO2膜7を形成し(図3(h))、そして図では
簡単のため省略するが、イオン注入でウェルとチャネル
を形成した後に、ウエットエッチングでSiO2膜7を
除去し(図4(i))、熱酸化によりゲートSiO2
8が、そして例えばCVD法によるポリシリコンでゲー
ト電極9が形成される(図4(j))。
Next, Si is wet-etched.
The N film 3 and the SiO 2 film 2 are removed (FIG. 3G), and a SiO 2 film 7 serving as a mask for ion implantation for forming a well or a channel is formed by thermal oxidation (FIG. 3H). Although it is omitted for simplicity, after forming a well and a channel by ion implantation, the SiO 2 film 7 is removed by wet etching (FIG. 4 (i)), and a gate SiO 2 film 8 is formed by thermal oxidation. A gate electrode 9 is formed of polysilicon by the method (FIG. 4 (j)).

【0020】この後は、公知の方法でゲート電極のパタ
ーニングが行われ、ソース・ドレインが形成され、配線
工程を経てMOSデバイスが形成されることになる。
Thereafter, patterning of the gate electrode is performed by a known method, source / drain is formed, and a MOS device is formed through a wiring process.

【0021】このような製造方法においては、トレンチ
の下部はSOGで埋め込み、上部はCVD法で例えばH
TO膜で埋め込んでいるため、本例のようなアスペクト
比の高いトレンチでも良好に埋め込むことができ、かつ
ウエットエッチング耐性の高いHTO膜で覆っているの
で、プロセス中のトレンチ酸化膜の膜減りも小さく、こ
のため良好なトレンチ形状が得られる。さらに、SOG
がキャップされるために、SOG中の不純物のゲート酸
化工程等への影響も防ぐことが出来るという効果がもた
らされる。これにより、ウエットエッチング耐性の高い
膜を形成することができる。
In such a manufacturing method, the lower portion of the trench is buried with SOG, and the upper portion is, for example, H
Since the trench is buried with the TO film, the trench having a high aspect ratio as in this example can be buried well, and the trench is reduced in the thickness of the trench oxide film during the process because it is covered with the HTO film having high wet etching resistance. Small, so that a good trench shape can be obtained. Furthermore, SOG
Is capped, so that the effect of preventing impurities in the SOG from affecting the gate oxidation step and the like can be prevented. Thereby, a film having high wet etching resistance can be formed.

【0022】上記の実施の形態において、HTO膜の代
わりに、ウエットエッチング耐性の高さが得られるなら
ば、成長温度を低くした、いわゆるLTO膜を用いても
良い。またプラズマCVDでも、HDP(High Density
Plasma)CVDで形成した酸化膜は、ウエットエッチ
ング耐性の高い膜が得られることが知られており、HT
Oの代わりにこれを用いても良い。さらにSOG膜は、
無機SOG、有機SOGのれを用いても良く、HSQ
(Hydrogen-Silsesquioxane)の様な低誘電率の塗布膜
を用いても良い。
In the above embodiment, a so-called LTO film having a lower growth temperature may be used in place of the HTO film, if high wet etching resistance can be obtained. In plasma CVD, HDP (High Density)
It is known that a film having high wet etching resistance can be obtained from an oxide film formed by plasma (CVD) CVD.
This may be used instead of O. Furthermore, the SOG film
Inorganic SOG or organic SOG may be used.
(Hydrogen-Silsesquioxane) may be used.

【0023】[0023]

【発明の効果】以上に説明したように、本発明の半導体
装置の製造方法においては、SOGを用いてトレンチ上
部の埋め込みを行うことにより、アスペクト比の高いト
レンチの埋め込みを行うことが容易となり、かつトレン
チ上部の埋め込みを膜質、特にウエットエッチング耐性
の良いHTO膜等のCVD膜で形成することで、デバイ
スプロセス中でのウエットエッチングによる形状悪化を
防ぐ役目を果たす。
As described above, in the method of manufacturing a semiconductor device according to the present invention, by burying the upper portion of the trench using SOG, it becomes easy to bury the trench having a high aspect ratio. In addition, by filling the upper portion of the trench with a film quality, particularly a CVD film such as an HTO film having good wet etching resistance, it plays a role of preventing shape deterioration due to wet etching in a device process.

【0024】従って、埋め込み性が良くかつプロセス安
定性の高いトレンチ分離がアスペクト比が高いトレンチ
でも実現出来るという効果が得られる。
Therefore, an effect is obtained that a trench isolation having a good filling property and a high process stability can be realized even in a trench having a high aspect ratio.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a),(b)は本発明の一実施の形態におけ
る工程断面図。
FIGS. 1A and 1B are cross-sectional views illustrating a process according to an embodiment of the present invention.

【図2】(c)〜(e)は図1(a)の工程に続いて行
われる工程の工程断面図。
2 (c) to 2 (e) are process cross-sectional views of a process performed after the process of FIG. 1 (a).

【図3】(f)〜(h)は図2(e)の工程に続いて行
われる工程の工程断面図。
3 (f) to 3 (h) are process cross-sectional views of a process performed after the process of FIG. 2 (e).

【図4】(i),(j)は図3(h)の工程に続いて行
われる工程の工程断面図。
FIGS. 4 (i) and (j) are process cross-sectional views of a process performed after the process of FIG. 3 (h).

【図5】従来の方法で得られたトレンチ埋め込み酸化膜
を示す断面図。
FIG. 5 is a cross-sectional view showing a trench buried oxide film obtained by a conventional method.

【図6】従来の他の方法で得られたトレンチ埋め込み酸
化膜を示す断面図。
FIG. 6 is a cross-sectional view showing a trench buried oxide film obtained by another conventional method.

【符号の説明】[Explanation of symbols]

1 Si基板 2 SiO2膜 3 SiN膜 4 SiO2膜 5 SOG 6 HTO膜 7 SiO2膜 8 ゲートSiO2膜 9 ゲート電極REFERENCE SIGNS LIST 1 Si substrate 2 SiO 2 film 3 SiN film 4 SiO 2 film 5 SOG 6 HTO film 7 SiO 2 film 8 Gate SiO 2 film 9 Gate electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 トレンチ分離形状を有する半導体装置の
製造方法において、トレンチ素子分分離の酸化膜による
埋め込みを行う際、トレンチの深さ方向の途中までSO
Gで埋め込み、トレンチの上部は酸化膜により埋め込み
を行うことを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device having a trench isolation shape, when embedding with an oxide film for isolating a trench element, the SO is partially inserted in the depth direction of the trench.
A method of manufacturing a semiconductor device, comprising: burying with G, and burying an upper part of a trench with an oxide film.
【請求項2】 前記トレンチの上部の酸化膜が、HTO
膜またはLTO膜である請求項1に記載の方法。
2. The method according to claim 1, wherein the oxide film on the trench is HTO.
The method according to claim 1, which is a membrane or an LTO membrane.
【請求項3】 前記SOG膜が、無機SOG膜、有機S
OG膜、またはHSQ(Hydrogen-Silsesquioxane)膜
である請求項1に記載の方法。
3. The method according to claim 1, wherein the SOG film is an inorganic SOG film, an organic SOG film.
The method according to claim 1, which is an OG film or an HSQ (Hydrogen-Silsesquioxane) film.
JP10281574A 1998-10-02 1998-10-02 Manufacture of semiconductor device Pending JP2000114362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10281574A JP2000114362A (en) 1998-10-02 1998-10-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JP2000114362A true JP2000114362A (en) 2000-04-21

Family

ID=17641081

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000114362A (en)

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WO2004079819A1 (en) * 2003-03-05 2004-09-16 Az Electronic Materials (Japan) K.K. Method of forming trench isolation structure
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US7105397B2 (en) 2003-11-28 2006-09-12 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
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US7687355B2 (en) 2007-03-30 2010-03-30 Hynix Semiconductor Inc. Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer
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US7416987B2 (en) 2003-11-28 2008-08-26 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
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US7279769B2 (en) 2004-05-25 2007-10-09 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
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US8053286B2 (en) 2007-11-16 2011-11-08 Elpida Memory, Inc. Method of forming semiconductor device including trench gate structure
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