JP2000082956A - Pll回路 - Google Patents

Pll回路

Info

Publication number
JP2000082956A
JP2000082956A JP10252323A JP25232398A JP2000082956A JP 2000082956 A JP2000082956 A JP 2000082956A JP 10252323 A JP10252323 A JP 10252323A JP 25232398 A JP25232398 A JP 25232398A JP 2000082956 A JP2000082956 A JP 2000082956A
Authority
JP
Japan
Prior art keywords
clk
pfd
phase difference
feedback
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10252323A
Other languages
English (en)
Japanese (ja)
Inventor
Hiroyuki Aoki
博行 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP10252323A priority Critical patent/JP2000082956A/ja
Priority to KR1019990037292A priority patent/KR20000022898A/ko
Publication of JP2000082956A publication Critical patent/JP2000082956A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1072Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Editing Of Facsimile Originals (AREA)
JP10252323A 1998-09-07 1998-09-07 Pll回路 Pending JP2000082956A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10252323A JP2000082956A (ja) 1998-09-07 1998-09-07 Pll回路
KR1019990037292A KR20000022898A (ko) 1998-09-07 1999-09-03 Pll회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10252323A JP2000082956A (ja) 1998-09-07 1998-09-07 Pll回路

Publications (1)

Publication Number Publication Date
JP2000082956A true JP2000082956A (ja) 2000-03-21

Family

ID=17235672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10252323A Pending JP2000082956A (ja) 1998-09-07 1998-09-07 Pll回路

Country Status (2)

Country Link
JP (1) JP2000082956A (ko)
KR (1) KR20000022898A (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7061330B2 (en) 2003-02-19 2006-06-13 Kabushiki Kaisha Kobe Seiko Sho Oscillator including phase frequency detectors for detecting a phase difference between two input signals and outputting a control command signal
KR101207072B1 (ko) 2011-02-17 2012-11-30 성균관대학교산학협력단 위상 보간 기능을 갖는 위상고정루프 및 위상고정루프에서 위상 보간을 수행하는 방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4093826B2 (ja) * 2002-08-27 2008-06-04 富士通株式会社 クロック発生装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7061330B2 (en) 2003-02-19 2006-06-13 Kabushiki Kaisha Kobe Seiko Sho Oscillator including phase frequency detectors for detecting a phase difference between two input signals and outputting a control command signal
KR100629046B1 (ko) * 2003-02-19 2006-09-26 가부시키가이샤 고베 세이코쇼 발진기
US7492194B2 (en) 2003-02-19 2009-02-17 Kobe Steel, Ltd. Oscillator including phase frequency detectors for detecting a phase difference between two input signals and outputting a control command signal
KR101207072B1 (ko) 2011-02-17 2012-11-30 성균관대학교산학협력단 위상 보간 기능을 갖는 위상고정루프 및 위상고정루프에서 위상 보간을 수행하는 방법

Also Published As

Publication number Publication date
KR20000022898A (ko) 2000-04-25

Similar Documents

Publication Publication Date Title
US6937075B2 (en) Method and apparatus for reducing lock time in dual charge-pump phase-locked loops
US7558311B2 (en) Spread spectrum clock generator and method for generating a spread spectrum clock signal
US6683502B1 (en) Process compensated phase locked loop
KR100411551B1 (ko) 멀티-위상 클럭을 발생시키기 위한 지연-동기 루프 및 그 방법
US6704381B1 (en) Frequency acquisition rate control in phase lock loop circuits
JP2795323B2 (ja) 位相差検出回路
US6777991B2 (en) Method and apparatus for stable phase-locked looping
US6388485B2 (en) Delay-locked loop circuit having master-slave structure
US20100214031A1 (en) Spectrum spread clock generation device
US6873669B2 (en) Clock signal reproduction device
US7538591B2 (en) Fast locking phase locked loop for synchronization with an input signal
US20090167387A1 (en) Delay-locked loop for timing control and delay method thereof
US6320424B1 (en) Method of providing and circuit for providing phase lock loop frequency overshoot control
JP2947192B2 (ja) Pll回路
US6456165B1 (en) Phase error control for phase-locked loops
KR100423620B1 (ko) 입력 클럭에 대하여 일정한 위상차를 갖는 클럭을출력하는 pll 회로
US6330296B1 (en) Delay-locked loop which includes a monitor to allow for proper alignment of signals
CN111294043B (zh) 一种基于pll的自动恢复外部时钟的系统
US7236025B2 (en) PLL circuit and program for same
JP2000082956A (ja) Pll回路
JP3656155B2 (ja) 複数の位相同期回路を用いた周波数シンセサイザ
JP4082507B2 (ja) 位相同期回路
KR100341106B1 (ko) 위상록루프회로
JPH118552A (ja) 位相同期発振器
JPH10242851A (ja) Pll回路

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20000509