JP2000082956A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(phase locked loop) circuit reduced in jitter of output CLK and simple in circuit configuration. SOLUTION: A smaller dead zone period where a phase difference between input CLK and feedback CLK is not detected is constituted of a phase frequency comparator (PFD) 1. A larger dead zone period where the phase difference between input CLK and feedback CLK is not detected is constituted of PFD 2. A charge pump(CP) 1 is connected to PFD 1 and on-current is constituted of a smaller transistor. CP2 is connected to PFD 2 and on-current is constituted of a larger transistor. When the phase difference between input CLK and feedback CLK is large, the potential of a terminal CPOUT is speedily charged up and charged down with such a configuration. When the phase difference of input CLK and feedback CLK becomes small, only one of PFD1 and CP1 operates. Thus, a system returns to the original operation of PLL. Thus, the locking time is shortened, but jitter after locking does not change from that of a conventional PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a highly stabilized PL.
It relates to an L circuit.

[0002]

2. Description of the Related Art Conventionally, a PLL (phase-lock loop) circuit is generally constituted by a circuit shown in FIG. In FIG. 8 showing the configuration of a conventional general PLL, in the conventional PLL,
One phase frequency comparator (PFD) and one charge pump (CP) are mounted. In this PLL, even after locking, noise of power supply potential, noise of ground potential, LPF
CPOUT changes due to leakage of
(Voltage Control Oscillator) oscillation frequency change,
A phase advance and a delay occur. In order to correct a slight change in this case, the dead zone of the PFD is reduced, and C
The ON current gm of P is reduced.

In this case, points A and B in the timing chart of FIG.
As shown in the points, even when the phase difference between the input CLK before the lock and the feedback CLK is large, or even when the phase difference between the input CLK and the feedback CLK after the lock is small, the charge-up amount of CPOUT hardly changes. The time to lock becomes longer.

On the contrary, when the ON current gm of the CP is increased,
Since the charge-up amount of CPOUT is large, the lock time is short, but fine correction after locking cannot be performed.
The jitter of the output CLK increases.

In recent microprocessors, it is required to further reduce the jitter due to the increase in frequency, and the ON current gm of the charge pump is reduced.
This results in a longer lock time. Thus, it is necessary to solve the conflicting requirements of shortening the lock time and reducing the jitter.

In order to solve the above-mentioned requirements, for example, a technique disclosed in Japanese Patent Application Laid-Open No. 9-93122 of Conventional Example 2 has been proposed. According to the publication of the second conventional example, when the phase difference and the frequency of the input CLK and the feedback CLK are compared to determine that the phase difference is larger than a predetermined value and the frequency difference is equal to or smaller than the predetermined value,
It has been proposed to stop the operation of the CP. FIG.
Shows the configuration disclosed in Conventional Example 2 of the prior art document.

In the "PLL circuit" disclosed in Japanese Patent Application Laid-Open No. H10-107624 of Prior Art 3, the phase comparison judgment is subdivided based on multi-stage frequency division. By this subdivision, the conventional PLL
It is an object of the present invention to eliminate a problem that characteristics of a phase comparator and a low-pass filter are uniquely set in advance in a circuit.

[0008]

However, in the above-mentioned conventional example, a control circuit including a frequency comparing section, a frequency difference detecting section, and a decision circuit for controlling the PFD and the CP is newly provided. There is a need. For this reason, there is a problem that the configuration of the entire circuit is complicated.

In the third conventional example, a circuit for judging the phase is newly provided, and the phase comparator is selected. Therefore,
There is a problem that the circuit configuration becomes complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a PLL circuit having a small output CLK and a simple circuit configuration.

[0011]

To achieve the above object, a PLL circuit according to the present invention comprises a first PFD having a smaller dead zone period in which a phase difference between an input CLK and a feedback CLK is not detected, A second PFD that forms a larger dead zone period in which a phase difference between CLK and feedback CLK is not detected, a first CP that is connected to the first PFD and is configured by a transistor having a smaller ON current, and a second CP. And a second CP connected to the PFD and having a larger ON current.

In the above charge pump circuit, the input CLK is connected to the first input terminals of the first PFD and the second PFD, and the output terminals of the first CP and the second CP are connected in parallel. A low-pass filter may be further provided between the output terminal and the GND connected in parallel, and a VCO may be further provided between the output terminal and the output CLK terminal.

Further, a frequency divider is provided between the output terminal of the VCO and the second input terminal of each of the first PFD and the second PFD and forms a loop circuit together with the charge pump circuit. And the low-pass filter may be configured by connecting a resistor and a capacitor in series.

Note that the first PFD and the second PFD
Has a delay element in each circuit configuration, and enables adjustment of the dead zone period by adjusting the delay element.
When the phase difference between LK and feedback CLK is large, the first and second CPs are driven, and the low-pass filter is charged up or charged down earlier, so that the phase difference can be shortened.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a PLL circuit according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIGS. 1 to 7, one embodiment of the PLL circuit of the present invention is shown.

FIG. 1 is a circuit block diagram showing a configuration example of a PLL circuit according to an embodiment of the present invention. FIG. 2 shows charge pumps CP1 and CP2 applied to the present embodiment.
FIG. 3 is a diagram showing a more detailed configuration example of FIG. FIG. 3 is a circuit diagram showing a more detailed configuration example of the PFD applied to the present embodiment.

In FIG. 1, between the input CLK and the output CLK, a phase frequency comparator (PFD) and a charge pump (CP) forming a larger first dead zone, and a smaller second dead zone are formed. A phase frequency comparator (PFD) and a charge pump (CP) are connected in parallel to form a charge pump circuit. Charge Pump Circuit, Voltage Controlled Oscillator (VCO) and Dividing Period (DI
V) are connected in series to form a loop circuit. Further, a low-pass filter (LPF) is provided for the PFD 1 and the CP
1, and the output point CPO where PFD2 and CP2 are connected in parallel
Connected to UT. The input CLK is PFD1 and PF
D2 is connected to a first parallel input with D2 and the output CLK is
It is connected to the output terminal of the VCO. Output CLK is DIV
And the output of DIV is connected to the second parallel input of PFD1 and PFD2.

[0018] The PLL circuit having the above-described configuration uses a phase frequency comparator (PF) to shorten the oscillation stabilization time (lock time).
D) and two charge pumps (CPs). The main points of the configuration of the present PLL circuit are as follows.

A PFD having a different period (dead zone) during which the PFD does not detect a phase difference between the input CLK and the feedback CLK.
(PFD1, PFD2). When the phase difference between the input CLK and the feedback CLK is large, PFD1, PFD2
Operate, and when the phase difference between the input CLK and the feedback CLK decreases, only the PFD 1 operates. Further, two CPs (CP1 and CP2) having different ON currents gm of the transistors are formed, and the CP1 is connected so as to be driven by the PFD1 and the CP2 is driven by the PFD2.

As described above, the PFD1 and CP1 have the same configuration as that of the related art having a smaller dead zone and a smaller ON current. Further, the PFD2 has a larger dead zone than that of the related art, and the CP2 has an ON current gm larger than that of the related art. Thus, when the phase difference between the input CLK and the feedback CLK is large, the PFD
1, both PFD2 operate and the potential of CPOUT is quickly charged up and charged down. Also, input C
When the phase difference between LK and feedback CLK decreases, P
Only FD1 operates and returns to the operation of the conventional PLL.

Next, an operation example will be described. PFD is
The leading / lagging of the falling edges of the two CLKs (input CLK, feedback CLK) are detected, and only the leading / lagging UP is detected.
Signal, DN signal. By inserting a delay element in the PFD, it is possible to create and adjust a period (dead zone) in which the leading and trailing edges of two falling edges of CLK are not detected.

The CP is driven by the PFD, and sets the active period Pch or Nch of the UP signal and the DN signal to O.
At N, the potential (CPOUT) of the LPF is charged up or charged down.

FIG. 4 shows a circuit configuration of an embodiment of a low-pass filter (LPF). 4, the LPF applied to the present embodiment is configured by connecting a resistor R and a capacitor C in series between a terminal CPOUT and a GND terminal. In the LPF having this configuration, the CPOUT is determined by the CP and the PF
While the UP signal or the DN signal of D is active, it is charged up or charged down from the ground potential to the power supply potential.

The frequency of the output CLK changes depending on the potential of CPOUT. Although there are various control methods, this embodiment operates such that the frequency of the output CLK increases as the CPOUT potential increases.

The output CLK is divided and the feedback CLK is returned to the PFD. The frequency divider (DIV) is necessary when a frequency obtained by multiplying the frequency of the input CLK is used as the frequency of the output CLK. In this embodiment, the DIV is attached, but the DIV is
If the frequency of the input CLK and the frequency of the output CLK may be the same, they need not be provided.

Next, the overall configuration will be described. PFD
(PFD1 and PFD2), and different dead zones are set. A dead zone of a shorter period is set in PFD1 and a dead zone of a longer period is set in PFD2. In this configuration, when the phase difference between the input CLK and the feedback CLK is large, PF
D1 and PFD2 are both operated, and the input CLK and the feedback C
When the phase difference of LK becomes small, only PFD1 is operated.

Also, two CPs (CP1 and CP2) are provided, and CP1 is connected so as to be driven by PFD1 and CP2 is driven by PFD2. CP1 is composed of a transistor having a small ON current (small gm), and CP2 is composed of a transistor having a large ON current (large gm).

(Description of Operation) The operation of the present embodiment will be described below. In the circuit configuration of FIG.
Will be described with reference to the timing chart of FIG.

In FIG. 2, CP1 reduces the ON current gm of the transistor, and PFD1 (UP1, DN1)
Driven by Further, CP2 increases the ON current gm of the transistor, and PFD2 (UP2, DN2)
Driven by

FIG. 5 shows an example of the operation timing when the phase difference between the input CLK and the feedback CLK is large (when the phase difference is large) in the upper stage, and the lower stage when the phase difference between the input CLK and the feedback CLK is small. This is an operation timing example (when the phase difference is small). The magnitude of these phase differences is determined by the feedback CL
K and the falling edge of the input CLK; A or F;
Or it is an interval with G. The magnitude is PFD1, PF
It is determined by comparison with the dead zone set in D2.

The feedback CLK is PFD with respect to the input CLK.
1. When the delay is longer than the dead zone set by PFD2 (when the phase difference is large), PFD1 and PFD2 detect the delay from the fall of input CLK (point A) to the fall of feedback CLK (point B). UP1 (point C), UP
Both 2 (point D) operate. In this case, UP1, UP
2 operate to charge up CPOUT with the current flowing through CP1 + the current flowing through CP2. Therefore, C
POUT is rapidly charged up (point D).

The feedback CLK is PFD1
If the delay is equal to or greater than the dead zone set in the above and less than the dead zone set in the PFD2 (when the phase difference is small), P
FD1 is the feedback CL from the falling edge of the input CLK (point E).
The delay until the fall of K (point F) is detected and UP1
(Point H) operates. UP2 does not operate and holds Hi. In this case, CPOUT is charged up only by CP1. For this reason, CPOUT is gradually charged up.

The feedback CLK is PFD with respect to the input CLK.
1. If the delay is equal to or shorter than the dead zone set in PFD2, the PLL is locked at this time, and PFD1
(UP1) and PFD2 (UP2) do not operate (Hi
Holding).

As described above, similar to the operation when the feedback CLK lags behind the input CLK, the feedback CLK is
, UP1 operates in place of DN1 and UP2 operates in place of DN2, and CPOUT is charged down.

(Other Embodiments) As another embodiment of the present invention, the basic configuration is as described above. However, the dead zone creation of the PFD is different from the above embodiment shown in FIG. As shown in FIG. 6, it is also possible to combine the delay elements into one. In the embodiment shown in FIG. 2, two CPs are provided independently of CP1 and CP2.
However, a configuration in which the control circuit is shared and the ON current gm of the final stage of CPOUT is changed is also possible, as in the case of using a current source as a typical control circuit of CP in FIG.

The feature of the present invention is that although the lock time is shortened by using the dead zone of the PFD,
Jitter is the same as before. Therefore PFD
By simply changing the delay element without changing the basic configuration, two PFDs having different dead zones can be created. Similarly, in the charge pump, the ON current gm of the transistor at the final stage that outputs CPOUT is changed without changing the control circuit of the charge pump.
One charge pump can be made. For this reason, the effect of shortening the lock time can be improved almost in the design, almost the same as the basic PLL design period. In the above embodiment, the dead zone and the CP
Although two types of ON current are used, three or more types may be used.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0038]

As is apparent from the above description, the PLL circuit of the present invention has a smaller dead zone period and a larger dead zone period in which the phase difference between the input CLK and the feedback CLK is not detected, and the ON state is determined. A charge pump circuit is constituted by a first CP constituted by a transistor having a smaller current and a second CP constituted by a transistor having a larger ON current.

With this configuration, when the phase difference between the input CLK and the feedback CLK is large, the potential of CPOUT is charged up and charged down quickly, and the input CLK and the feedback CL
When the phase difference with K decreases, the first PFD + the first PFD
Since only one of the CPs operates, the operation returns to the operation of the conventional PLL. Therefore, although the lock time is shortened, the jitter after locking is not different from that of the conventional PLL. In addition, despite solving the conflicting issues of shortening the lock time and reducing the jitter, the design period hardly changes. This is because the basic configuration of the PFD is the same, and two PFDs having different dead zones can be formed only by forming delay elements. Further, the control circuit of the CP is the same as that of the CP.
This is because two CPs having different ON currents gm can be formed only by changing the dimension of the last stage for outputting POUT.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration example of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a charge pump CP1 applied to the embodiment;
FIG. 3 is a diagram showing a more detailed configuration example of CP2 and CP2.

FIG. 3 is a circuit diagram showing a more detailed configuration example of a PFD applied to the present embodiment.

FIG. 4 is a circuit diagram showing an embodiment of a low-pass filter (LPF).

FIG. 5 is a timing chart showing an operation example, where the upper part shows a case where the phase difference is large, and the lower part shows a case where the phase difference is small.

FIG. 6 is a circuit diagram showing another embodiment for creating a dead zone of a PFD.

FIG. 7 is a circuit diagram showing another embodiment of a CP.

FIG. 8 shows a configuration of a conventional general PLL.

FIG. 9 is a timing chart showing an operation example of a conventional PLL, where the upper part shows a case where the phase difference is large, and the lower part shows a case where the phase difference is small.

FIG. 10 is a circuit diagram showing a configuration example of a PLL of Conventional Example 2.

[Explanation of symbols]

 PFD1, PFD2 Phase frequency comparator CP1, CP2 Charge pump VCO Voltage controlled oscillator DIV Divide period LPF Low pass filter UP1, UP2 Charge up signal DN1, DN2 Charge down signal R Resistor RC Capacitor

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 30, 1999 (1999.8.3)
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

In order to achieve the above object, a PLL circuit according to the present invention comprises a first and a second phase frequency comparator for generating an output signal when there is a phase difference between an input CLK and a feedback CLK. The first phase frequency comparator has a dead zone period in which a phase difference is not detected is smaller than that of the second phase frequency comparator, and is connected to the first phase frequency comparator. And a second charge pump connected to the second phase frequency comparator and configured by a transistor. The ON current of the first charge pump is equal to the second charge pump (CP). 2 is characterized in that it has a charge pump circuit configured to be smaller than the ON current of the charge pump.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C076 AA40 5J106 AA04 CC01 CC30 CC38 CC41 CC52 CC59 DD32 JJ08 KK25 KK39

Claims (7)

[Claims] 1. A first PFD constituting a smaller dead zone period in which a phase difference between an input CLK and a feedback CLK is not detected, and a larger dead zone period not detecting a phase difference between the input CLK and the feedback CLK. The second PFD constituting
A first CP connected to the first PFD and configured with a transistor having a smaller ON current; a second CP connected to the second PFD and configured with a transistor having a larger ON current; Characterized by comprising a charge pump circuit constituted by:
circuit. 2. The charge pump circuit according to claim 1, wherein:
LK is the first of the first PFD and the first of the second PFD.
And the first CP and the second CP
Are connected in parallel, and the parallel-connected output terminal and G
2. The PLL circuit according to claim 1, wherein a low-pass filter is further provided between the NDs. 3. The PLL circuit according to claim 1, further comprising a VCO between said output terminal and an output CLK terminal. 4. An output terminal of the VCO and the first PF
4. The frequency divider according to claim 1, further comprising a frequency divider provided between D and a second input terminal of each of the second PFDs to form a loop circuit together with the charge pump circuit. The PLL circuit according to any one of the above. 5. The PLL circuit according to claim 2, wherein the low-pass filter includes a resistor and a capacitor connected in series. 6. The first PFD and the second PF
D according to any one of claims 1 to 5, wherein D has a delay element in each circuit configuration, and the dead zone period can be adjusted by adjusting the delay element.
LL circuit. 7. When the phase difference between the input CLK and the feedback CLK is large, the first and second CPs are driven, and the low-pass filter is charged up or charged down earlier to reduce the phase difference. 7. The PLL circuit according to claim 1, wherein the PLL circuit can be shortened.