JP2000077465A - Electronic unit - Google Patents

Electronic unit

Info

Publication number
JP2000077465A
JP2000077465A JP10241990A JP24199098A JP2000077465A JP 2000077465 A JP2000077465 A JP 2000077465A JP 10241990 A JP10241990 A JP 10241990A JP 24199098 A JP24199098 A JP 24199098A JP 2000077465 A JP2000077465 A JP 2000077465A
Authority
JP
Japan
Prior art keywords
chip
bare
circuit board
printed circuit
electronic unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10241990A
Other languages
Japanese (ja)
Inventor
Masayoshi Yamaguchi
政義 山口
Hajime Nakajima
元 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP10241990A priority Critical patent/JP2000077465A/en
Publication of JP2000077465A publication Critical patent/JP2000077465A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an electronic unit which can prevent the occurrence of improper conduction or an increase in contact resistance by increasing the mechanical joining strength of a bare IC chip to a printed board. SOLUTION: An electronic unit 1 is constituted by flip-chip mounting a bare IC chip 3 on a printed board 2, formed by directly forming plated silver layers 2M on the surfaces of electrodes 2A which are composed of a copper foil and by making bumps 3B formed on the electrodes 3A of the IC chip 3 bite into the electrodes 2A of the printed board 2. In addition, the unit 1 is also constituted by directly forming the plated silver layers 2M on the newly exposed surfaces of the electrodes 2A, after the newly prepared surfaces are formed by chemically polishing the surfaces of the electrodes 2A composed of the copper foil.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、プリント基板にベ
アICチップをフリップチップ実装して成る電子ユニッ
トに関するものである。
The present invention relates to an electronic unit in which a bare IC chip is flip-chip mounted on a printed circuit board.

【0002】[0002]

【従来の技術】ベアICチップをプリント基板に実装す
る方法の1つとして、異方性導電フィルム等の接合材料
を用いたフリップチップ実装方法(フリップチップボン
ディング法)がある。
2. Description of the Related Art As one method of mounting a bare IC chip on a printed circuit board, there is a flip chip mounting method (a flip chip bonding method) using a bonding material such as an anisotropic conductive film.

【0003】図7は、フリップチップ実装方法によって
製造された電子ユニットAを示しており、プリント基板
Bに異方性導電フィルムCを介してベアICチップDが
接合されている。
FIG. 7 shows an electronic unit A manufactured by a flip chip mounting method. A bare IC chip D is bonded to a printed board B via an anisotropic conductive film C.

【0004】プリント基板Bは、その実装面に銅箔から
成る電極Ba,Ba…が形成され、これら電極Ba,B
a…の表面には、各々ニッケルメッキBbを下地として
金メッキBcが施されている。
The printed board B has electrodes Ba, Ba... Made of copper foil on its mounting surface, and these electrodes Ba, B.
are plated with gold plating Bc with nickel plating Bb as a base.

【0005】一方、ベアICチップDは、その実装面に
電極Da,Da…が設けられ、これら電極Daの表面に
は、各々Au(金)等の金属材料から成るバンプDb,D
b…が形成されている。
On the other hand, the bare IC chip D is provided with electrodes Da, Da... On its mounting surface, and bumps Db, D made of a metal material such as Au (gold) are provided on the surfaces of these electrodes Da.
b ... are formed.

【0006】上述した電子ユニットAは、フィルム状の
絶縁性樹脂Caに導電粒子Cbを多数混在させて成る異
方性導電フィルムCを、プリント基板Bの実装面に仮接
着したのち、上記異方性導電フィルムCにベアICチッ
プDを載置し、ベアICチップDを加圧しつつ異方性導
電フィルムCを加熱して、プリント基板BにベアICチ
ップDを本接着することによって製造される。
In the electronic unit A described above, an anisotropic conductive film C, in which a large number of conductive particles Cb are mixed in a film-like insulating resin Ca, is temporarily bonded to a mounting surface of a printed circuit board B. The bare IC chip D is mounted on the conductive conductive film C, the anisotropic conductive film C is heated while the bare IC chip D is pressed, and the bare IC chip D is fully bonded to the printed circuit board B. .

【0007】[0007]

【発明が解決しようとする課題】ところで、従来の電子
ユニットAでは、プリント基板Bの電極Baに下地とし
て施されているニッケルメッキBbが、ベアICチップ
DにおけるバンプDbに比べて硬いため、プリント基板
Bに接合させるべく、ベアICチップDを加圧した際、
電極Baは変形することなく、ベアICチップDのバン
プDbは、電極Baにおける金メッキBcの平滑な表面
と結合する。
In the conventional electronic unit A, the nickel plating Bb applied to the electrode Ba of the printed circuit board B as a base is harder than the bump Db of the bare IC chip D. When the bare IC chip D is pressurized to be bonded to the substrate B,
The electrode Ba is not deformed, and the bump Db of the bare IC chip D is bonded to the smooth surface of the gold plating Bc on the electrode Ba.

【0008】ここで、プリント基板BとベアICチップ
Dとの電気的な導通は、プリント基板Bにおける電極B
aの金メッキBcと、ベアICチップDのバンプDbと
の接触、あるいは異方性導電フィルムCの導電粒子Cb
を介して得られており、またプリント基板Bに対するベ
アICチップDの結合強度は、主として異方性導電フィ
ルムCにおける絶縁性樹脂Caの接着成分によって得ら
れている。
Here, the electrical continuity between the printed circuit board B and the bare IC chip D is determined by the electrode B on the printed circuit board B.
(a) Contact between gold plating Bc and bump Db of bare IC chip D, or conductive particles Cb of anisotropic conductive film C
The bonding strength of the bare IC chip D to the printed board B is mainly obtained by the adhesive component of the insulating resin Ca in the anisotropic conductive film C.

【0009】このため、環境試験(恒温・恒湿試験、温
度サイクル試験等)を実施した後、上述した絶縁性樹脂
Caの接着成分が劣化することにより、プリント基板B
とベアICチップDとの機械的な接合強度が低下し、導
通不良や接触抵抗の増大を招来する不都合があった。
For this reason, after an environmental test (constant temperature / humidity test, temperature cycle test, etc.) is performed, the above-mentioned adhesive component of the insulating resin Ca deteriorates, and the printed circuit board B
The mechanical joining strength between the semiconductor chip and the bare IC chip D is reduced, which causes inconveniences such as poor conduction and increased contact resistance.

【0010】本発明は上記実状に鑑みて、プリント基板
に対するベアICチップの機械的な接合強度を増大さ
せ、もって導通不良や接触抵抗の増大を未然に防止し得
る電子ユニットの提供を目的とするものである。
The present invention has been made in view of the above circumstances, and has as its object to provide an electronic unit capable of increasing the mechanical bonding strength of a bare IC chip to a printed circuit board, thereby preventing poor conduction and increase in contact resistance. Things.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するべ
く、本発明に関わる電子ユニットは、銅箔から成る電極
の表面に銀メッキ層を直接に形成して成るプリント基板
に、ベアICチップをフリップチップ実装して成ること
を特徴としている。
In order to achieve the above object, an electronic unit according to the present invention comprises a bare IC chip mounted on a printed circuit board having a silver plating layer formed directly on the surface of an electrode made of copper foil. It is characterized by being flip-chip mounted.

【0012】また、本発明に関わる電子ユニットは、プ
リント基板にベアICチップをフリップチップ実装して
成る電子ユニットであって、ベアICチップの電極に形
成したバンプを、プリント基板の電極に食い込ませて成
ることを特徴としている。
Further, the electronic unit according to the present invention is an electronic unit in which a bare IC chip is flip-chip mounted on a printed board, and a bump formed on an electrode of the bare IC chip is cut into an electrode of the printed board. It is characterized by comprising.

【0013】また、本発明に関わる電子ユニットは、プ
リント基板にベアICチップをフリップチップ実装して
成る電子ユニットであって、プリント基板は、銅箔から
成る電極の表面を化学研磨して新生面を形成したのち、
新生面の形成された電極の表面に銀メッキ層を直接に形
成して成ることを特徴としている。
The electronic unit according to the present invention is an electronic unit in which a bare IC chip is flip-chip mounted on a printed circuit board. The printed circuit board has a new surface formed by chemically polishing the surface of an electrode made of copper foil. After forming,
It is characterized in that a silver plating layer is directly formed on the surface of the electrode on which the new surface is formed.

【0014】[0014]

【発明の実施の形態】以下、実施例を示す図面に基づい
て、本発明を詳細に説明する。図1に示す如く、本発明
に関わる電子ユニット1は、プリント基板2と、ベアI
Cチップ3とを有し、異方性導電フィルム4を用いて、
プリント基板2にベアICチップ3をフリップチップ実
装することにより構成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments. As shown in FIG. 1, an electronic unit 1 according to the present invention includes a printed circuit board 2 and a bare I
C chip 3, using anisotropic conductive film 4,
It is configured by mounting a bare IC chip 3 on a printed circuit board 2 in a flip chip manner.

【0015】図1および図2に示す如く、プリント基板
2は、その実装面に銅箔をパターニングして成る電極2
A,2A…が設けられており、これら電極2A,2A…
の表面には、それぞれ銀メッキ層2M,2M…が形成さ
れている。
As shown in FIGS. 1 and 2, a printed circuit board 2 has an electrode 2 formed by patterning a copper foil on a mounting surface thereof.
A, 2A... Are provided, and these electrodes 2A, 2A.
Are formed with silver plating layers 2M, 2M... Respectively.

【0016】また、これら銀メッキ層2M,2M…の表
面には、銀メッキ層2Mの酸化や硫化、あるいはマイグ
レーションの防止を目的として、有機膜2a,2a…が
形成されている。なお、上記有機膜2aは本発明の必須
要件でないことは言うまでもない。
On the surfaces of the silver plating layers 2M, organic films 2a are formed for the purpose of preventing oxidation, sulfurization or migration of the silver plating layers 2M. Needless to say, the organic film 2a is not an essential requirement of the present invention.

【0017】一方、ベアICチップ3は、その実装面に
電極3A,3A…が設けられ、これら電極3A,3A…
の表面には、それぞれ金(Au)等の金属材料から成るバ
ンプ3B,3B…が形成されている。
On the other hand, the bare IC chip 3 is provided with electrodes 3A, 3A... On a mounting surface thereof, and these electrodes 3A, 3A.
Are formed on the surface of each of the bumps 3B, 3B,... Made of a metal material such as gold (Au).

【0018】また、異方性導電フィルム4は、フィルム
状を呈する絶縁性樹脂4aに、多数の導電粒子4b,4
b…を混在させることによって構成されている。
Further, the anisotropic conductive film 4 is formed by adding a large number of conductive particles 4b and 4 to a film-like insulating resin 4a.
.. are mixed.

【0019】上述した如き構成の電子ユニット1は、先
ずプリント基板2の実装面に異方性導電フィルム4を供
給し、異方性導電フィルム4をプリント基板2に熱圧着
したのちベアICチップ3を供給し、次いでプリント基
板2にベアICチップ3を熱圧着することによって製造
される。
In the electronic unit 1 having the above-described configuration, first, the anisotropic conductive film 4 is supplied to the mounting surface of the printed board 2, and the bare IC chip 3 And then thermocompression bonding the bare IC chip 3 to the printed circuit board 2.

【0020】ここで、図1からも明らかなように、ベア
ICチップ3のバンプ3Bは、プリント基板2における
有機膜2aを破って、銀メッキ層2Mおよび電極2Aに
食い込んで接合されている。また、異方性導電フィルム
4の導電粒子4bは、上記バンプ3Bと銀メッキ層2M
および電極2Aとの双方に食い込んでいる。
Here, as is clear from FIG. 1, the bump 3B of the bare IC chip 3 breaks the organic film 2a on the printed circuit board 2 and cuts into and joins the silver plating layer 2M and the electrode 2A. The conductive particles 4b of the anisotropic conductive film 4 are formed by the bumps 3B and the silver plating layer 2M.
And the electrode 2A.

【0021】このように、ベアICチップ3のバンプ3
Bが、プリント基板2の銀メッキ層2Mおよび電極2A
に食い込んで接合されることにより、プリント基板2に
対するベアICチップ3の機械的な接合強度が増大する
こととなる。
As described above, the bumps 3 of the bare IC chip 3
B is the silver plating layer 2M of the printed circuit board 2 and the electrode 2A
In this case, the mechanical bonding strength of the bare IC chip 3 to the printed circuit board 2 is increased.

【0022】このため、環境試験後に異方性導電フィル
ム4の接着成分が劣化しても、プリント基板2とベアI
Cチップ3との十分な接合強度を確保することができ、
もって接合強度の低下に起因する導通不良や接触抵抗の
増大を未然に防止することができる。
Therefore, even if the adhesive component of the anisotropic conductive film 4 deteriorates after the environmental test, the printed circuit board 2 and the bare I
Sufficient bonding strength with the C chip 3 can be secured,
Therefore, poor conduction and increase in contact resistance due to a decrease in bonding strength can be prevented.

【0023】また、ベアICチップ3のバンプ3Bが、
プリント基板2の銀メッキ層2Mおよび電極2Aに食い
込んで接合されることで、上記バンプ3Bと電極2Aと
の接触面積が増大することとなり、もってプリント基板
2とベアICチップ3との電気的な接合部における接続
抵抗を減少させることが可能となる。
The bumps 3B of the bare IC chip 3
The contact between the bump 3B and the electrode 2A is increased by biting into and joining the silver plating layer 2M and the electrode 2A of the printed circuit board 2, and thus the electrical connection between the printed circuit board 2 and the bare IC chip 3 is increased. It is possible to reduce the connection resistance at the junction.

【0024】ところで、上記プリント基板2における銀
メッキ層2Mは、図3に示すS1からS8の各工程を経
て電極2Aの表面に形成される。すなわち、パターニン
グされたプリント基板に対し、先ず脱脂処理工程(S1)
において表面の油分や汚れ等を除去し、洗浄工程(S2)
において表面から脱脂剤等を取り除いて清浄する。
The silver plating layer 2M on the printed circuit board 2 is formed on the surface of the electrode 2A through the steps S1 to S8 shown in FIG. That is, first, the degreasing process (S1) is performed on the patterned printed circuit board.
In the cleaning step (S2), oil and dirt on the surface are removed.
In, cleaning is performed by removing the degreasing agent and the like from the surface.

【0025】次いで、エッチング処理工程(S3)におい
て、電極2Aの表面から酸化物を取り除くべく化学研磨
を実施し、電極2Aの表面に新生面を形成する。
Next, in the etching step (S3), chemical polishing is performed to remove oxides from the surface of the electrode 2A, and a new surface is formed on the surface of the electrode 2A.

【0026】こののち、洗浄工程(S4)を経て、コンデ
ィショニング処理工程(S5)において、電極2Aの表面
を銀メッキが付き易いよう調質する。
Thereafter, after the cleaning step (S4), in the conditioning step (S5), the surface of the electrode 2A is conditioned so that silver plating can be easily applied.

【0027】次いで、銀メッキ工程(S6)において、電
極2Aの表面に銅と銀との置換反応により銀メッキ層2
Mを形成し、こののち洗浄工程(S7)および乾燥工程
(S8)を経てプリント基板2が完成する。
Next, in a silver plating step (S6), the silver plating layer 2 is formed on the surface of the electrode 2A by a substitution reaction between copper and silver.
M is formed, followed by a washing step (S7) and a drying step
Through (S8), the printed circuit board 2 is completed.

【0028】上述した如く、電極2Aの表面から酸化物
を除去する作業を、機械研磨ではなく化学研磨によって
実施し、新生面を形成した電極2Aの表面に銀メッキ層
2Mを直接に形成したことにより、電極2Aと銀メッキ
層2Mとの密着強度を向上させることができ、さらに均
一な厚さで平滑性の良好な銀メッキ層2Mを得ることが
可能となる。
As described above, the operation of removing the oxide from the surface of the electrode 2A is performed not by mechanical polishing but by chemical polishing, and the silver plating layer 2M is formed directly on the surface of the electrode 2A on which a new surface is formed. In addition, the adhesion strength between the electrode 2A and the silver plating layer 2M can be improved, and the silver plating layer 2M having a uniform thickness and good smoothness can be obtained.

【0029】なお、図1に開示した電子ユニット1にお
いて、異方性導電フィルム4に換えて、異方性導電ペー
スト、あるいは接着剤を採用することも可能である。ま
た、プリント基板2とベアICチップ3との接合強度を
増強する目的で、ベアICチップ3の周囲に接着剤を供
給しても良い。さらに、プリント基板2とベアICチッ
プ3との接合方法は、熱圧着に限定されるものではな
く、圧力、熱、超音波、紫外線、あるいは各々の組合せ
によっても実施し得る。
In the electronic unit 1 shown in FIG. 1, an anisotropic conductive paste or an adhesive may be used instead of the anisotropic conductive film 4. Further, an adhesive may be supplied around the bare IC chip 3 for the purpose of increasing the bonding strength between the printed circuit board 2 and the bare IC chip 3. Further, the method of joining the printed circuit board 2 and the bare IC chip 3 is not limited to thermocompression bonding, but may be implemented by pressure, heat, ultrasonic waves, ultraviolet rays, or a combination of each.

【0030】図4に示す電子ユニット10は、プリント
基板12とベアICチップ13との間に、これらプリン
ト基板12とベアICチップ13との間隔を規定するた
めのスペーサ15が介在されており、このスペーサ15
はプリント基板12の導体部分とベアICチップ13と
の接触によるショートを防止するもので、絶縁材料から
構成されている。
The electronic unit 10 shown in FIG. 4 has a spacer 15 interposed between the printed circuit board 12 and the bare IC chip 13 for defining the distance between the printed circuit board 12 and the bare IC chip 13. This spacer 15
Is for preventing a short circuit caused by contact between the conductor portion of the printed circuit board 12 and the bare IC chip 13, and is made of an insulating material.

【0031】上述した如き構成の電子ユニット10は、
先ずプリント基板12の実装面に異方性導電フィルム1
4を供給し、異方性導電フィルム14をプリント基板1
2に熱圧着したのち、ベアICチップ13とスペーサ1
5とを供給し、次いでプリント基板12とベアICチッ
プ13とスペーサ15とを熱圧着により接合して製造さ
れる。
The electronic unit 10 having the above-described configuration includes:
First, the anisotropic conductive film 1 is mounted on the mounting surface of the printed circuit board 12.
4 and supply the anisotropic conductive film 14 to the printed circuit board 1.
2, the bare IC chip 13 and the spacer 1
5 is supplied, and then the printed circuit board 12, the bare IC chip 13, and the spacer 15 are joined by thermocompression bonding.

【0032】なお、上述した電子ユニット10の構成
は、スペーサ15以外、図1に示した電子ユニット1と
同一であり、また作用効果についても電子ユニット1と
同様なので、電子ユニット10の構成要素において、電
子ユニット1の構成要素と同一の作用を成すものには、
図4において図1の符号に10を加算した番号を附すこ
とで詳細な説明は省略する。
The structure of the electronic unit 10 described above is the same as that of the electronic unit 1 shown in FIG. 1 except for the spacer 15, and the operation and effect are the same as those of the electronic unit 1. , Having the same function as the components of the electronic unit 1 include:
In FIG. 4, a detailed description is omitted by attaching a number obtained by adding 10 to the reference numeral in FIG.

【0033】図5に示す電子ユニット20は、ベアIC
チップ23のバンプ23Bが、導電性ペースト26を介
して、プリント基板22における有機膜22aを破り、
銀メッキ層22Mおよび電極22Aに食い込んで接合さ
れている。
The electronic unit 20 shown in FIG.
The bump 23B of the chip 23 breaks the organic film 22a on the printed circuit board 22 via the conductive paste 26,
It is joined to the silver plating layer 22M and the electrode 22A.

【0034】上述した電子ユニット20は、先ずプリン
ト基板22に導電性ペースト26を供給し、次いでベア
ICチップ23を供給し、プリント基板22と導電性ペ
ースト26とベアICチップ23とを熱圧着により接合
し、次いでプリント基板22とベアICチップ23との
隙間に接着剤27を供給したのち、この接着剤27を熱
硬化させることによって製造される。
The above-described electronic unit 20 first supplies the conductive paste 26 to the printed circuit board 22 and then supplies the bare IC chip 23, and the printed circuit board 22, the conductive paste 26 and the bare IC chip 23 are thermocompressed. After bonding, the adhesive 27 is supplied to the gap between the printed circuit board 22 and the bare IC chip 23, and then the adhesive 27 is cured by heat.

【0035】なお、上述した電子ユニット20におけ
る、プリント基板22およびベアICチップ23の構成
は、図1に示したプリント基板2およびベアICチップ
3と同一なので、プリント基板2およびベアICチップ
3の構成要素と同一の作用を成すものには、図5におい
て図1の符号に20を加算した番号を附すことで詳細な
説明は省略する。
The configuration of the printed circuit board 22 and the bare IC chip 23 in the electronic unit 20 is the same as that of the printed circuit board 2 and the bare IC chip 3 shown in FIG. Elements having the same functions as those of the constituent elements are given the same reference numerals as those in FIG.

【0036】上述した構成の電子ユニット20において
も、先に説明した電子ユニット1と同じく、ベアICチ
ップ23のバンプ23Bが、プリント基板22の銀メッ
キ層22Mおよび電極22Aに食い込んで接合されるこ
とで、接合強度の低下に起因する導通不良や接触抵抗の
増大を未然に防止することができ、かつプリント基板2
2とベアICチップ23との電気的な接合部における接
続抵抗を減少させることが可能となる。
In the electronic unit 20 having the above-described configuration, similarly to the electronic unit 1 described above, the bump 23B of the bare IC chip 23 cuts into the silver plating layer 22M and the electrode 22A of the printed circuit board 22 and is joined. Therefore, it is possible to prevent a conduction failure and an increase in contact resistance due to a decrease in bonding strength, and to prevent the printed circuit board 2
It is possible to reduce the connection resistance at the electrical junction between the second IC and the bare IC chip 23.

【0037】なお、上述した電子ユニット20において
は、導電ペースト26に換えて導電性フィルムを採用す
ることも可能である。また、プリント基板22とベアI
Cチップ23との接合方法は、熱圧着に限定されるもの
ではなく、圧力、熱、超音波、紫外線、あるいは各々の
組合せによっても実施し得る。また、接着剤27はプリ
ント基板22とベアICチップ23との接合強度を増大
させるものであるが、必ずしも必要とするものではな
い。さらに、プリント基板22とベアICチップ23と
の間に、図4に開示したスペーサ(15)を介在させるこ
とも可能であり、上記構成によって、プリント基板22
とベアICチップ23とのショートを有効に防止するこ
とができる。
In the above-described electronic unit 20, a conductive film may be used instead of the conductive paste 26. Also, the printed circuit board 22 and the bare I
The joining method with the C chip 23 is not limited to the thermocompression bonding, but may be carried out by pressure, heat, ultrasonic waves, ultraviolet rays, or a combination thereof. The adhesive 27 increases the bonding strength between the printed circuit board 22 and the bare IC chip 23, but is not always necessary. Further, the spacer (15) disclosed in FIG. 4 can be interposed between the printed board 22 and the bare IC chip 23.
And the bare IC chip 23 can be effectively prevented.

【0038】図6に示す電子ユニット30は、ベアIC
チップ33のバンプ33Bが、プリント基板32におけ
る有機膜32aを破って、銀メッキ層32Mおよび電極
32Aに食い込んで接合されている。
The electronic unit 30 shown in FIG.
The bump 33B of the chip 33 breaks the organic film 32a on the printed circuit board 32, cuts into the silver plating layer 32M and the electrode 32A, and is joined.

【0039】上述した電子ユニット30は、プリント基
板32にベアICチップ33を供給し、プリント基板3
2とベアICチップ33とを、加圧により接合すること
によって製造されている。
The electronic unit 30 supplies the bare IC chip 33 to the printed circuit board 32 and
2 and the bare IC chip 33 are joined by pressure.

【0040】なお、上述した電子ユニット30におけ
る、プリント基板32およびベアICチップ33の構成
は、図1に示したプリント基板2およびベアICチップ
3と同一なので、プリント基板2およびベアICチップ
3の構成要素と同一の作用を成すものには、図6におい
て図1の符号に30を加算した番号を附すことで詳細な
説明は省略する。
The configurations of the printed circuit board 32 and the bare IC chip 33 in the electronic unit 30 are the same as those of the printed circuit board 2 and the bare IC chip 3 shown in FIG. In FIG. 6, those having the same functions as those of the components are denoted by the same reference numerals as those in FIG.

【0041】上述した構成の電子ユニット30において
も、先に説明した電子ユニット1と同じく、ベアICチ
ップ33のバンプ33Bが、プリント基板32の銀メッ
キ層32Mおよび電極32Aに食い込んで接合されるこ
とで、接合強度の低下に起因する導通不良や接触抵抗の
増大を未然に防止することができ、かつプリント基板3
2とベアICチップ33との電気的な接合部における接
続抵抗を減少させることが可能となる。
In the electronic unit 30 having the above-described configuration, similarly to the electronic unit 1 described above, the bump 33B of the bare IC chip 33 cuts into the silver plating layer 32M and the electrode 32A of the printed circuit board 32 and is joined. Thus, it is possible to prevent a poor conduction and an increase in contact resistance due to a decrease in bonding strength, and to prevent the printed circuit board 3
It is possible to reduce the connection resistance at the electrical junction between the semiconductor chip 2 and the bare IC chip 33.

【0042】ここで、上述した電子ユニット30におけ
る、プリント基板32とベアICチップ33との接合方
法は、加圧に限定されるものではなく、圧力、熱、超音
波、紫外線、あるいは各々の組合せによっても実施し得
る。また、接合強度を増大させる目的で、プリント基板
32とベアICチップ33との隙間、あるいはベアIC
チップ33の周囲に接着剤を供給しても良い。さらに、
プリント基板32とベアICチップ33との間に、図4
に開示したスペーサ(15)を介在させることも可能であ
り、上記構成によって、プリント基板32とベアICチ
ップ33とのショートを有効に防止することができる。
Here, the method of joining the printed circuit board 32 and the bare IC chip 33 in the above-described electronic unit 30 is not limited to pressurization, but may be pressure, heat, ultrasonic waves, ultraviolet rays, or a combination thereof. Can also be implemented. In order to increase the bonding strength, a gap between the printed circuit board 32 and the bare IC chip 33 or a bare IC
An adhesive may be supplied around the chip 33. further,
4 between the printed circuit board 32 and the bare IC chip 33.
Can be interposed, and the above-described configuration can effectively prevent a short circuit between the printed circuit board 32 and the bare IC chip 33.

【0043】なお、上述した各実施例において、ベアI
Cチップにおけるバンプは、扁平な球状を呈している
が、プリント基板に対するベアICチップの加圧力の大
小等、フリップチップ実装に関わる諸条件により、バン
プの形状を球、円柱、円錐、多角柱、多角錘、あるいは
上述した形態の一部を平面としたもの等、適宜な形状に
設定し得ることは言うまでもない。
In each of the above embodiments, the bear I
The bump in the C chip has a flat spherical shape. However, depending on various conditions related to flip chip mounting, such as the magnitude of the pressure of the bare IC chip on the printed circuit board, the bump shape may be a sphere, a cylinder, a cone, a polygonal pillar, or the like. Needless to say, the shape can be set to an appropriate shape such as a polygonal pyramid or a part of the above-described embodiment made into a plane.

【0044】[0044]

【発明の効果】以上、詳述した如く、請求項1の発明に
関わる電子ユニットは、銅箔から成る電極の表面に銀メ
ッキ層を直接に形成して成るプリント基板に、ベアIC
チップをフリップチップ実装して成る。上記構成によれ
ば、プリント基板に対してベアICチップを加圧するこ
とで、ベアICチップのバンプをプリント基板の電極に
食い込ませることができ、これによってプリント基板と
ベアICチップとの機械的な接合強度が増大し、導通不
良や接触抵抗の増大を未然に防止することが可能とな
る。
As described in detail above, the electronic unit according to the first aspect of the present invention includes a bare IC on a printed circuit board in which a silver plating layer is formed directly on the surface of an electrode made of copper foil.
The chip is flip-chip mounted. According to the above configuration, by pressing the bare IC chip against the printed circuit board, the bumps of the bare IC chip can be cut into the electrodes of the printed circuit board. The bonding strength is increased, and it is possible to prevent poor conduction and increase in contact resistance.

【0045】また、請求項3の発明に関わる電子ユニッ
トは、プリント基板にベアICチップをフリップチップ
実装して成る電子ユニットであって、ベアICチップの
電極に形成したバンプを、プリント基板の電極に食い込
ませて成る。上記構成よれば、ベアICチップのバンプ
をプリント基板の電極に食い込ませたことで、プリント
基板とベアICチップとの機械的な接合強度が増大し、
もって導通不良や接触抵抗の増大を未然に防止すること
が可能となる。
An electronic unit according to a third aspect of the present invention is an electronic unit in which a bare IC chip is flip-chip mounted on a printed circuit board. It is made to bite into. According to the above configuration, the bumps of the bare IC chip are cut into the electrodes of the printed board, so that the mechanical bonding strength between the printed board and the bare IC chip is increased,
As a result, it is possible to prevent poor conduction and increase in contact resistance.

【0046】さらに、請求項6の発明に関わる電子ユニ
ットは、プリント基板にベアICチップをフリップチッ
プ実装して成る電子ユニットであって、プリント基板
は、銅箔から成る電極の表面を化学研磨して新生面を形
成したのち、新生面の形成された電極の表面に銀メッキ
層を直接に形成して成る。上記構成によれば、電極の表
面に銀メッキ層を直接に形成したことにより、プリント
基板に対してベアICチップを加圧することで、ベアI
Cチップのバンプをプリント基板の電極に食い込ませる
ことができ、これによってプリント基板とベアICチッ
プとの機械的な接合強度が増大し、導通不良や接触抵抗
の増大を未然に防止することが可能となる。
Further, the electronic unit according to the invention of claim 6 is an electronic unit in which a bare IC chip is flip-chip mounted on a printed board, and the printed board is formed by chemically polishing the surface of an electrode made of copper foil. After the formation of the new surface, a silver plating layer is formed directly on the surface of the electrode on which the new surface is formed. According to the above configuration, since the silver plating layer is formed directly on the surface of the electrode, the bare IC chip is pressed against the printed circuit board, and the bare IC chip is pressed.
The bumps of the C chip can be cut into the electrodes of the printed circuit board, thereby increasing the mechanical bonding strength between the printed circuit board and the bare IC chip, preventing conduction failure and increasing contact resistance. Becomes

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に関わる電子ユニットを示す概念的な断
面側面図。
FIG. 1 is a conceptual cross-sectional side view showing an electronic unit according to the present invention.

【図2】本発明に関わる電子ユニットの構成要素を示す
概念的な断面側面図。
FIG. 2 is a conceptual cross-sectional side view showing components of an electronic unit according to the present invention.

【図3】本発明の電子ユニットを構成するプリント基板
の製造工程を示すフロー図。
FIG. 3 is a flowchart showing a manufacturing process of a printed circuit board constituting the electronic unit of the present invention.

【図4】本発明に関わる電子ユニットを示す概念的な断
面側面図。
FIG. 4 is a conceptual cross-sectional side view showing an electronic unit according to the present invention.

【図5】本発明に関わる電子ユニットを示す概念的な断
面側面図。
FIG. 5 is a conceptual cross-sectional side view showing an electronic unit according to the present invention.

【図6】本発明に関わる電子ユニットを示す概念的な断
面側面図。
FIG. 6 is a conceptual cross-sectional side view showing an electronic unit according to the present invention.

【図7】従来の電子ユニットを示す概念的な断面側面
図。
FIG. 7 is a conceptual cross-sectional side view showing a conventional electronic unit.

【符号の説明】[Explanation of symbols]

1,10,20,30…電子ユニット、 2,12,22,32…プリント基板、 2A,12A,22A,32A…電極、 2M,12M,22M,32M…銀メッキ層、 3,13,23,33…ベアICチップ、 3A,13A,23A,33A…電極、 3B,13B,23B,33B…バンプ、 15…スペーサ。 1, 10, 20, 30: electronic unit, 2, 12, 22, 32: printed circuit board, 2A, 12A, 22A, 32A: electrode, 2M, 12M, 22M, 32M: silver plating layer, 3, 13, 23, 33: bare IC chip, 3A, 13A, 23A, 33A: electrode, 3B, 13B, 23B, 33B: bump, 15: spacer.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 銅箔から成る電極の表面に銀メッキ層
を直接に形成して成るプリント基板に、ベアICチップ
をフリップチップ実装して成ることを特徴とする電子ユ
ニット。
An electronic unit comprising a bare IC chip flip-chip mounted on a printed circuit board having a silver plating layer formed directly on the surface of an electrode made of copper foil.
【請求項2】 プリント基板とベアICチップとの間
に、上記プリント基板と上記ベアICチップとの間隔を
規定するためのスペーサを介在させたことを特徴とする
請求項1記載の電子ユニット。
2. The electronic unit according to claim 1, further comprising a spacer interposed between the printed circuit board and the bare IC chip for defining an interval between the printed circuit board and the bare IC chip.
【請求項3】 プリント基板にベアICチップをフリ
ップチップ実装して成る電子ユニットであって、 上記ベアICチップの電極に形成したバンプを、プリン
ト基板の電極に食い込ませて成ることを特徴とする電子
ユニット。
3. An electronic unit in which a bare IC chip is flip-chip mounted on a printed circuit board, wherein the bumps formed on the electrodes of the bare IC chip are cut into the electrodes of the printed circuit board. Electronic unit.
【請求項4】 プリント基板は、銅箔から成る電極の
表面に銀メッキ層が直接に形成されていることを特徴す
る請求項3記載の電子ユニット。
4. The electronic unit according to claim 3, wherein the printed board has a silver plating layer formed directly on a surface of an electrode made of copper foil.
【請求項5】 プリント基板とベアICチップとの間
に、上記プリント基板と上記ベアICチップとの間隔を
規定するためのスペーサを介在させたことを特徴とする
請求項3記載の電子ユニット。
5. The electronic unit according to claim 3, further comprising a spacer interposed between the printed circuit board and the bare IC chip for defining an interval between the printed circuit board and the bare IC chip.
【請求項6】 プリント基板にベアICチップをフリ
ップチップ実装して成る電子ユニットであって、 プリント基板は、銅箔から成る電極の表面を化学研磨し
て新生面を形成したのち、新生面の形成された電極の表
面に銀メッキ層を直接に形成して成ることを特徴とする
電子ユニット。
6. An electronic unit in which a bare IC chip is flip-chip mounted on a printed circuit board, wherein the printed circuit board is formed by chemically polishing a surface of an electrode made of copper foil to form a new surface, and then forming the new surface. An electronic unit comprising a silver plating layer formed directly on the surface of the electrode.
JP10241990A 1998-08-27 1998-08-27 Electronic unit Pending JP2000077465A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10241990A JP2000077465A (en) 1998-08-27 1998-08-27 Electronic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10241990A JP2000077465A (en) 1998-08-27 1998-08-27 Electronic unit

Publications (1)

Publication Number Publication Date
JP2000077465A true JP2000077465A (en) 2000-03-14

Family

ID=17082618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10241990A Pending JP2000077465A (en) 1998-08-27 1998-08-27 Electronic unit

Country Status (1)

Country Link
JP (1) JP2000077465A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124538A (en) * 2000-10-12 2002-04-26 Eastern Co Ltd Circuit board
JP2006098637A (en) * 2004-09-29 2006-04-13 Seiko Epson Corp Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus
JP2011114226A (en) * 2009-11-27 2011-06-09 Nitto Denko Corp Wiring circuit structure, and method of manufacturing semiconductor device using the structure
CN104465572A (en) * 2013-09-12 2015-03-25 日月光半导体制造股份有限公司 Packaging structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124538A (en) * 2000-10-12 2002-04-26 Eastern Co Ltd Circuit board
JP2006098637A (en) * 2004-09-29 2006-04-13 Seiko Epson Corp Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus
JP4539268B2 (en) * 2004-09-29 2010-09-08 セイコーエプソン株式会社 Mounting structure
JP2011114226A (en) * 2009-11-27 2011-06-09 Nitto Denko Corp Wiring circuit structure, and method of manufacturing semiconductor device using the structure
CN102130093A (en) * 2009-11-27 2011-07-20 日东电工株式会社 Wiring circuit structure and manufacturing method for semiconductor device using the structure
CN102130093B (en) * 2009-11-27 2016-01-20 日东电工株式会社 Wired circuit structure and use the manufacture method of semiconductor device of this structure
CN104465572A (en) * 2013-09-12 2015-03-25 日月光半导体制造股份有限公司 Packaging structure
CN104465572B (en) * 2013-09-12 2017-06-06 日月光半导体制造股份有限公司 Encapsulating structure

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