JP2000076186A - 内部ル―プ同期部 - Google Patents

内部ル―プ同期部

Info

Publication number
JP2000076186A
JP2000076186A JP15679699A JP15679699A JP2000076186A JP 2000076186 A JP2000076186 A JP 2000076186A JP 15679699 A JP15679699 A JP 15679699A JP 15679699 A JP15679699 A JP 15679699A JP 2000076186 A JP2000076186 A JP 2000076186A
Authority
JP
Japan
Prior art keywords
data
signal
bit
register
strobe signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15679699A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000076186A5 (enExample
Inventor
D Hammond Maynard
メイナード・デー・ハモンド
M Dewey James
ジェームズ・エム・デューイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2000076186A publication Critical patent/JP2000076186A/ja
Publication of JP2000076186A5 publication Critical patent/JP2000076186A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
JP15679699A 1998-06-04 1999-06-03 内部ル―プ同期部 Withdrawn JP2000076186A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/090,440 US6041417A (en) 1998-06-04 1998-06-04 Method and apparatus for synchronizing data received in an accelerated graphics port of a graphics memory system
US09/090440 1998-06-04

Publications (2)

Publication Number Publication Date
JP2000076186A true JP2000076186A (ja) 2000-03-14
JP2000076186A5 JP2000076186A5 (enExample) 2006-07-13

Family

ID=22222772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15679699A Withdrawn JP2000076186A (ja) 1998-06-04 1999-06-03 内部ル―プ同期部

Country Status (2)

Country Link
US (1) US6041417A (enExample)
JP (1) JP2000076186A (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
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US6317842B1 (en) * 1999-02-16 2001-11-13 Qlogic Corporation Method and circuit for receiving dual edge clocked data
US6334163B1 (en) * 1999-03-05 2001-12-25 International Business Machines Corp. Elastic interface apparatus and method therefor
US6546449B1 (en) * 1999-07-02 2003-04-08 Ati International Srl Video controller for accessing data in a system and method thereof
US6469703B1 (en) * 1999-07-02 2002-10-22 Ati International Srl System of accessing data in a graphics system and method thereof
DE10153862B4 (de) * 2001-11-02 2004-01-29 Texas Instruments Deutschland Gmbh Verfahren zum Übertragen von Daten zwischen wenigstens zwei über einen seriellen Datenbus miteinander verbundenen Modulen und serielle Schnittstelle zur Durchführung des Verfahrens
US7111228B1 (en) 2002-05-07 2006-09-19 Marvell International Ltd. System and method for performing parity checks in disk storage system
US7007114B1 (en) * 2003-01-31 2006-02-28 Qlogic Corporation System and method for padding data blocks and/or removing padding from data blocks in storage controllers
US7287102B1 (en) 2003-01-31 2007-10-23 Marvell International Ltd. System and method for concatenating data
US7099963B2 (en) * 2003-03-10 2006-08-29 Qlogic Corporation Method and system for monitoring embedded disk controller components
US7039771B1 (en) 2003-03-10 2006-05-02 Marvell International Ltd. Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers
US7064915B1 (en) 2003-03-10 2006-06-20 Marvell International Ltd. Method and system for collecting servo field data from programmable devices in embedded disk controllers
US7870346B2 (en) * 2003-03-10 2011-01-11 Marvell International Ltd. Servo controller interface module for embedded disk controllers
US7457903B2 (en) * 2003-03-10 2008-11-25 Marvell International Ltd. Interrupt controller for processing fast and regular interrupts
US7492545B1 (en) 2003-03-10 2009-02-17 Marvell International Ltd. Method and system for automatic time base adjustment for disk drive servo controllers
US7526691B1 (en) 2003-10-15 2009-04-28 Marvell International Ltd. System and method for using TAP controllers
US7139150B2 (en) * 2004-02-10 2006-11-21 Marvell International Ltd. Method and system for head position control in embedded disk drive controllers
SE528607C2 (sv) * 2004-04-30 2006-12-27 Kvaser Consultant Ab System och anordning för att tidsmässigt relatera händelser i ett fordon
US7120084B2 (en) * 2004-06-14 2006-10-10 Marvell International Ltd. Integrated memory controller
US8166217B2 (en) * 2004-06-28 2012-04-24 Marvell International Ltd. System and method for reading and writing data using storage controllers
US7757009B2 (en) 2004-07-19 2010-07-13 Marvell International Ltd. Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device
US9201599B2 (en) * 2004-07-19 2015-12-01 Marvell International Ltd. System and method for transmitting data in storage controllers
US8032674B2 (en) * 2004-07-19 2011-10-04 Marvell International Ltd. System and method for controlling buffer memory overflow and underflow conditions in storage controllers
US7386661B2 (en) 2004-10-13 2008-06-10 Marvell International Ltd. Power save module for storage controllers
US7240267B2 (en) * 2004-11-08 2007-07-03 Marvell International Ltd. System and method for conducting BIST operations
US7802026B2 (en) * 2004-11-15 2010-09-21 Marvell International Ltd. Method and system for processing frames in storage controllers
US7493461B1 (en) * 2005-01-20 2009-02-17 Altera Corporation Dynamic phase alignment for resynchronization of captured data
US7609468B2 (en) 2005-04-06 2009-10-27 Marvell International Ltd. Method and system for read gate timing control for storage controllers
US7706996B2 (en) * 2006-04-21 2010-04-27 Altera Corporation Write-side calibration for data interface
US7509223B2 (en) * 2006-04-21 2009-03-24 Altera Corporation Read-side calibration for data interface
CN101067965B (zh) * 2006-04-21 2011-11-09 奥特拉股份有限公司 用于数据接口的读出侧校准
US7928770B1 (en) 2006-11-06 2011-04-19 Altera Corporation I/O block for high performance memory interfaces
US10546620B2 (en) * 2018-06-28 2020-01-28 Micron Technology, Inc. Data strobe calibration

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142683A (en) * 1987-03-09 1992-08-25 Unisys Corporation Intercomputer communication control apparatus and method
KR950012019B1 (ko) * 1992-10-02 1995-10-13 삼성전자주식회사 반도체메모리장치의 데이타출력버퍼
US5377205A (en) * 1993-04-15 1994-12-27 The Boeing Company Fault tolerant clock with synchronized reset
US5729719A (en) * 1994-09-07 1998-03-17 Adaptec, Inc. Synchronization circuit for clocked signals of similar frequencies
US5870591A (en) * 1995-08-11 1999-02-09 Fujitsu Limited A/D with digital PLL
US5666321A (en) * 1995-09-01 1997-09-09 Micron Technology, Inc. Synchronous DRAM memory with asynchronous column decode
JPH0973776A (ja) * 1995-09-07 1997-03-18 Mitsubishi Electric Corp 同期型半導体記憶装置

Also Published As

Publication number Publication date
US6041417A (en) 2000-03-21

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