JP2000068380A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of performing wiring for minimizing a capacitance value and a resistance value parasitic to the wiring of the clock signals of a flip-flop or latching or the like and completing arrangement and wiring with the absolute minimum number of times. SOLUTION: In this semiconductor integrated circuit device of a gate array system, for the wiring layer to wire a clock output cell 6 and respective flip- flops 2, the wiring layer of a lowest order which is identical to the wiring layer for constituting logic is used. Also the clock signal wiring of vertical direction wiring 5/horizontal direction wiring 4 is performed, by using the wiring layer of the lowest order for both. Also for power supply wiring which is conventionally wired in the lowest order, wiring is performed by using the wiring layer of a highest order. By doing so, the resistance value and capacitance value parasitic to the clock signals are restrained to a minimum, and a development period is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a technique effective when applied to a semiconductor integrated circuit device employing a gate array system.

[0002]

2. Description of the Related Art As shown in FIG. 5, clock signal wiring in a conventional gate array type semiconductor integrated circuit device is formed by using a multilayer wiring layer like other signal wirings. Further, the power supply wiring 9 was wired in the lowest wiring layer. The clock signal wiring and other clock signal wiring are
Without distinction, the horizontal wiring 10 is wired in the lowermost wiring layer, similarly to the power supply wiring described above. The vertical wiring 8 is wired using a wiring layer different from the lowest layer. The intersection of the vertical wiring and the horizontal wiring was connected by a through hole. Since signal lines are laid out vertically and horizontally, many through holes were used.

FIG. 4 shows an arrangement and wiring flow in a conventional gate array type semiconductor integrated circuit. After arranging all cells first, power supply wiring and signal wiring are performed in this order. In signal wiring, wiring is performed without distinction between clock signal wiring and other signals.

As in this example, a large number of through holes are used in a clock signal, and there is a difference between delay times reaching respective flip-flops.

A semiconductor integrated circuit device adopting the gate array system is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-53826.
No. is described in the PR.

[0006]

In the conventional method of placing and routing a semiconductor integrated circuit, a simulation after placement and routing is performed to determine whether or not an expected result is obtained in the simulation. If not, they must be placed or wired again. In particular, when the wiring is long, the wiring delay increases due to the capacitance value and the resistance value that are parasitic on the wiring. When a timing error relating to a clock occurs in a flip-flop or a latch, the state transition of the flip-flop or the latch changes, and the degree of malfunction of the semiconductor integrated circuit is large. Therefore, it is necessary to place or place and wire many times until the expected result is achieved, which causes a problem that a lot of time is spent on the trial of the placement and routing. In a gate array in which wiring is performed using multilayer wiring, the through-hole resistance has a larger value than the resistance of aluminum as a wiring material. In the conventional clock wiring, a large number of through holes are used, so that the through hole resistance increases, and as a result, the wiring delay increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a clock signal is preferentially wired at the lowest layer in a wiring layer of a clock input signal such as a flip-flop or a latch, so that a clock signal is provided. In the wiring, the wiring layer is only the lowermost layer, and there is no need to use a through hole or the like. Since clock wiring can be performed without using through holes, wiring that minimizes the capacitance value and resistance value that is parasitic on the wiring of clock signals such as flip-flops or latches can be performed, and placement and wiring can be performed with the minimum number of times It is an object of the present invention to provide a semiconductor integrated circuit capable of completing the above.

[0008]

According to the semiconductor integrated circuit device of the present invention, a clock such as a flip-flop or the like in a gate array type semiconductor integrated circuit is designed by automatically arranging and designing logic function blocks using multilayer wiring. In the signal wiring, clock signal wiring is performed using the lowermost layer of the multilayer wiring layer.

In the clock signal wiring, wiring is performed using the lowest wiring layer for both the vertical wiring and the horizontal wiring.

A semiconductor integrated circuit device according to claim 1, wherein the power supply wiring is supplied using a top wiring layer in the power supply wiring supplied to the logic function block.

Further, in the clock signal wiring of the flip-flop or the like according to the first aspect, the clock signal wiring is wired before the power supply wiring.

Further, in the clock signal wiring of the flip-flop or the like according to the first aspect of the present invention, the arrangement position of a cell which becomes an obstacle when wiring the clock signal is moved.

[0013]

According to the semiconductor integrated circuit device of the present invention, the capacitance value and the wiring resistance value which are parasitic on the clock signal wiring such as a flip-flop or a latch can be suppressed, and the arrangement and wiring can be completed with a minimum number of times. .

[0014]

Embodiment 1 FIG. 1 shows an example of a gate array type semiconductor integrated circuit device according to the present invention. In FIG. 1, all cells are arranged together with an IO cell 1, a cell 2 such as a flip-flop, and a cell 3 outside the flip-flop. In a state where all the cells are arranged, the clock signal 4 connecting the output cell 6 of the clock signal and the flip-flop 2 etc.
5 is wired. Both the horizontal wiring 4 and the vertical wiring 5 are wired by using the lowest wiring layer.

In a conventional gate array type semiconductor integrated circuit, as shown in the flow of FIG. 4, power supply wiring is performed after arrangement, and all signal wiring is performed.
Since the power supply wiring and the signal wiring were formed using the same wiring layer, the wiring had to be performed avoiding the power supply wiring at the time of the signal wiring.

In the present invention, as described in the second embodiment, the power supply wiring layer uses the uppermost wiring layer and does not overlap the lowermost wiring layer which is the clock signal wiring layer. Further, since the clock signal wiring is laid before the other signal wiring, the wiring is performed without being disturbed by the power supply wiring and other signal wiring. The clock signal wiring can be wired without being disturbed by other clock signal wirings, so that the wiring is performed through the shortest path.

If the wiring is performed in the shortest time, the delay time to reach the flip-flop may be different. Therefore, in order to make the time to reach each flip-flop the same, the wiring length is made equal. Wiring techniques may be taken. The length of the wiring from the clock signal output cell No. 6 to each flip-flop 2 must be equal.
In the present invention, even when the equal-length wiring method is used, it is considered to be an effective means because obstacles (wiring in the same layer) which hinder the wiring are minimized.

In the conventional gate array type semiconductor integrated circuit device, the lowest wiring layer is used as a wiring layer for configuring a logical function. By using the lowest wiring layer, if it is necessary to connect to the semiconductor substrate,
This is because they can be connected by a single through hole.

In the present invention, clock signal wiring is performed using the same wiring layer (lowest wiring layer) as the wiring layer for configuring the logic function. By performing wiring using the same wiring layer, wiring can be performed without using through holes in clock signal wiring.

Usually, aluminum is used as a wiring material in a gate array, and the resistance of an aluminum layer is not so large, but the through-hole resistance in a multilayer wiring has a very large value. As for the delay of the normal wiring, the ratio of the delay of the through hole to the delay is larger than that of the single wiring.

As described above, the clock signal delay can be minimized by minimizing the resistance value and the capacitance value parasitic on the clock signal. In addition, since the delay value of each clock signal can be easily made the same, malfunction of the semiconductor circuit caused by the clock signal can be minimized.

Embodiment 2 FIG. 2 shows an example of a power supply wiring according to the present invention. This is a state where the wiring related to the clock signal described in the first embodiment is completed. After the clock signal wiring is completed, power supply wiring of 7 is performed. The power supply line 7 is wired using the uppermost wiring layer. Since the wiring is performed using the uppermost wiring layer, the wiring can be performed without being disturbed by the clock signal wiring that is performed in the first embodiment.

Normally, wiring layers for configuring logic are wired using the lowest wiring layer, and power supply wiring is similarly performed using the lowest wiring layer. By using the lowest wiring layer, a single through hole was used to supply power to the semiconductor substrate. In the past, through holes could not be overlapped, but in recent years, with the progress of semiconductor integrated circuits, a technique of overlapping a plurality of through holes has been established. Even if the power supply wiring is performed using the uppermost wiring using this technique, it is possible to connect to the semiconductor substrate by overlapping through holes from the uppermost layer. In the power supply wiring of the gate array type semiconductor integrated circuit device, wirings are arranged in a matrix at equal intervals as shown in FIG. By arranging the power supply wiring in a grid pattern vertically and horizontally, it is possible to prevent electromigration, decrease in potential during high-speed operation, noise, and the like.

If the clock signal in the present invention is wired in the lowest layer, power cannot be wired in the lowest wiring layer used for the conventional power supply wiring.
Therefore, as described above, by setting the power supply wiring layer to the uppermost layer, power supply wiring can be formed in a grid pattern as in the related art.

In the second embodiment and FIG. 2, it is described that only the power supply in the horizontal direction is wired in the uppermost layer, but the wiring in the vertical direction is the lowermost layer as in the conventional gate array type semiconductor integrated circuit device. -Wiring is performed using a wiring layer other than the top layer. By performing the power supply wiring method as described above, a grid-like power supply wiring can be formed in the same vertical and horizontal directions as before.

Third Embodiment FIG. 6 shows an example in which the position of a cell serving as an obstacle is moved during clock signal wiring according to the present invention. As described above, it is desirable that the clock signal to be wired to each flip-flop be as long as possible. However, the cell 11 in FIG. 6 is an obstacle when performing clock signal wiring. Each clock signal wiring cannot be wired with the same length depending on the cell that becomes an obstacle, resulting in a difference in wiring length. In the present example, the wiring lengths connected to the twelve flip-flops are particularly different.

If there is a cell that becomes an obstacle as described above, it is not possible to perform wiring of the same length.

FIG. 7 shows a flow of automatic placement and routing when moving an obstacle in FIG. After the arrangement is completed in the same manner as in the flow of FIG. 3, only the clock signal wiring is provisionally wired. A cell that has become an obstacle during the temporary wiring of the clock signal is detected. At the time of the next modification of the arrangement position, the arrangement position of the failed cell is moved to a position that does not obstruct the wiring of the clock signal. Next, main wiring of the clock signal is performed. In the case of clock signal main wiring, there should be no obstacles in the wiring,
Wiring of the same length can be made to each flip-flop. The transfer process is the same as the above-described flow, and thus will be omitted.

[0029]

As described above, according to the present invention, when automatically arranging and wiring logic function blocks in a semiconductor integrated circuit, the capacitance value and the resistance value that are parasitic on the clock signal wiring such as a flip-flop or a latch of the semiconductor integrated circuit are determined. It can be kept to a minimum. This has the effect of reducing the time required for automatic placement and routing and trials of routing.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of clock signal wiring of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a diagram showing an example of power supply wiring of the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a flow chart of automatic placement and routing of a semiconductor integrated circuit device according to the present invention.

FIG. 4 is a flow chart of automatic placement and routing of a conventional semiconductor integrated circuit device.

FIG. 5 is a diagram showing an example of arrangement and wiring of a conventional semiconductor integrated circuit device.

FIG. 6 is a diagram illustrating an example of an obstacle arrangement of the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a layout and wiring flow of automatic obstacle removal of the semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

 1. External input / output cell 2. Flip-flop 3. 3. logic configuration cell 4. Horizontal clock signal wiring 5. Vertical clock signal wiring 6. Clock output cell Power supply wiring 8. 8. Vertical signal wiring Power supply wiring 10. 10. Horizontal signal wiring Obstacle cell 12. Clock signal wiring

Claims (5)

[Claims] In a clock signal wiring such as a flip-flop in a gate array type semiconductor integrated circuit, wherein a logic function block is automatically arranged and wired using multilayer wiring, the lowest layer of a multilayer wiring layer is used. A semiconductor integrated circuit device characterized in that clock signal wiring is performed by using the same. 2. The semiconductor integrated circuit device according to claim 1, wherein in the clock signal wiring, wiring is performed using the lowest wiring layer for both the vertical wiring and the horizontal wiring. 3. A semiconductor integrated circuit device according to claim 1, wherein the power supply wiring is supplied using the uppermost wiring layer in the power supply wiring supplied to the logic function block. 4. A semiconductor integrated circuit device according to claim 1, wherein the clock signal wiring is arranged prior to the power supply wiring in the clock signal wiring of the flip-flop or the like. 5. A semiconductor integrated circuit device according to claim 1, wherein, in the clock signal wiring of the flip-flop or the like, an arrangement position of a cell which becomes an obstacle when wiring the clock signal is moved.