JPH08116025A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit, which is operated utilizing a clock mesh system and has little clock skew. CONSTITUTION: A circuit layout region 6 is split into a plurality of sections by a clock mesh main line 3 and the region, which is near the main line 3, of each section is specified as a sequential circuit layout region 40. There is a combinational circuit layout region 20 on the inner side of each sequential circuit layout region 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit using a clock mesh system and having a small clock skew.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, in order to determine the operation timing of an internal sequential circuit, a clock signal is input from the outside and the clock signal is transmitted to the sequential circuit via a clock wiring. If the timing at which the clock signal is transmitted to each sequential circuit is deviated, a malfunction of the semiconductor integrated circuit called clock skew is caused.

In order to prevent this clock skew, many proposals have been made in the past. For example, Japanese Unexamined Patent Publication
Japanese Patent No. 29124 discloses a method of arranging sequential circuits in the same row so as to directly connect the clock main line and each sequential circuit to reduce clock skew. The outline is shown in FIG. A clock wiring area 11, a flip-flop circuit area 12, another logic circuit area 13, and a wiring area 14 are arranged on a substrate 10. Since the flip-flop circuit region 12 in which the flip-flop circuits are arranged in the same row is arranged here, the length of the clock lead lines 5a to 5n is minimized to reduce the clock skew. However, while this method is effective in reducing the clock skew, it adversely affects the quality of placement and the quality of wiring, and for example, it becomes impossible to place a required number of circuits in a predetermined area or the data line There is a problem that a timing failure occurs due to the increase in the total wiring length.

As another conventional technique, a system called a clock mesh has been proposed. FIG. 13 shows an outline of the clock mesh method. The clock signal input from the clock driver 1 is supplied to the flip-flop circuits 2, 2a, 2b, 2c, ... Through the mesh-shaped clock mesh main line 3 and the clock lead line 5. In this method, the clock mesh is divided into a plurality of sections, and the flip-flop circuits 2, 2a, 2b, 2c,
Since the degree of freedom of arrangement is increased, both the arrangement quality and the wiring quality are improved as compared with the method shown in FIG.

[0005]

However, this clock mesh method also has the following problems. That is, when cells including flip-flops are automatically arranged, the degree of freedom in cell arrangement is high. There are cases where the distance is shorter. In such a case, when automatic wiring is performed using a normal layout tool, as shown in FIG. 13, wiring is performed from a clock lead line of a certain flip-flop circuit 2a to another flip-flop circuit 2b, and then the lead-out is performed. It may happen that a line is connected to another flip-flop circuit 2c in a chain form.
In this case, the flip-flop circuits 2a, 2b,
The skew values greatly differ between 2c, which adversely affects the actual simulation result.

Therefore, the present invention solves the problems of the prior art, and when arranging a large number of sequential circuits and a large number of combinational circuits in a predetermined region of a semiconductor body, the clock skew is small and the arrangement quality of the entire circuit is high. It is an object of the present invention to provide a semiconductor integrated circuit having a short total wiring length of data lines and excellent actual simulation results.

[0007]

According to the present invention, there is provided a semiconductor integrated circuit having a clock mesh main line for transmitting a predetermined clock signal, which divides a circuit arrangement region in which a sequential circuit and a combinational circuit are arranged into a plurality of mesh-shaped sections. In the circuit, all the 1-bit unit sequential circuit elements to which the clock signal is transmitted are connected to the tips of the respective clock lead lines extending from the clock mesh main line one by one.

Further, in the above semiconductor integrated circuit,
It is preferable that all the 1-bit unit sequential circuit elements to which the clock signal is transmitted are arranged at positions adjacent to the clock mesh main line.

[0009]

As described above, in the semiconductor integrated circuit of the present invention,
Since all the 1-bit unit sequential circuit elements to which the clock signal is transmitted are connected to the tips of the respective clock lead lines extending from the clock mesh main line, the clock signal reaches each sequential circuit from the clock mesh main line. The timing before doing it does not become uneven. Therefore, in the semiconductor integrated circuit of the present invention, the clock skew, which occurs due to a plurality of flip-flop circuits connected in a chain as shown in FIG. 13, is prevented or reduced.

[0010]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a conceptual diagram of a circuit arrangement area in the embodiment of the present invention. In FIG. 1, a circuit arrangement area 6 in which a sequential circuit and a combinational circuit are arranged is a clock mesh main line 3, 3a,
It is divided into four mesh-shaped sections by 3b. There is a sequential circuit placement area 40 adjacent to the clock mesh main line of each section, and all the sequential circuit elements in each section to which the clock signal is transmitted are in the sequential circuit placement area 40.
Are connected to the clock lead lines (not shown) extending from the clock mesh trunk lines 3, 3a, 3b. Inside the sequential circuit area 40 is a combined circuit arrangement area 20.

With this configuration, the clock signal from the clock driver 1 is directly transmitted to the clock pins of all the sequential circuit elements to which the clock signal is transmitted through the clock mesh main lines 3, 3a and 3b. Therefore, the clock skew is reduced. FIG. 2 (A)
FIG. 2 is a circuit layout diagram of a semiconductor integrated circuit of an embodiment of the present invention, showing a state in which the respective circuit elements in FIG. 1 are actually arranged. A clock mesh main line 3 that surrounds a circuit arrangement region 6 in which circuit elements other than pads and I / O cells are arranged and clock mesh main lines 3a and 3b that cross and traverse the inside of the circuit arrangement region 6 are divided into four sections. ing. The sequential circuit 4 is arranged adjacent to the clock mesh main lines 3, 3a, 3b, and all the 1-bit unit sequential circuit elements 4 are automatically drawn out from the clock mesh main lines 3, 3a, 3b. 5 are connected to the tips one by one. Therefore, the clock signal from the clock driver 1 is transmitted to all the sequential circuit elements 4 via the clock mesh trunk lines 3, 3a, 3b and the clock lead line 5. Therefore, unlike the case of FIG. 13, the sequential circuits 4 are not wired in a chain.

It is preferable that all the sequential circuit elements in 1-bit units are arranged adjacent to the clock mesh main line. This is because if elements other than the sequential circuit element are arranged adjacent to the clock mesh main line and a sequential circuit element to which a clock signal is to be transmitted is arranged apart from the clock mesh main line, skew may increase. Because there is.

FIG. 2B shows another embodiment of the present invention, which is an example in which the total number of gates of the sequential circuit is small and a long clock mesh main line is not required. In this case, since the area to be surrounded by the clock mesh main lines 3, 3a, 3b is sufficient as a part of the circuit arrangement area 6, the ring of the clock mesh main line 3 is reduced as compared with FIG. 2A. Only the lower left area of the circuit arrangement area 6 is divided into a plurality of sections by the clock mesh trunk lines 3, 3a, 3b. Then, the area in contact with the clock mesh trunk lines 3, 3a, 3b is set as an area for arranging all the sequential circuit elements 4 in 1-bit units, and the remaining area is an area for arranging the combinational circuit 2 and other elements. I am trying. In the case of FIG. 2A, the sequential circuit is arranged only inside the clock mesh main line 3,
In FIG. 2B, the sequential circuit is arranged outside the clock mesh main line 3 in both the vertical and horizontal directions.

FIG. 3 is a flow chart for explaining the steps for obtaining the semiconductor integrated circuit of the present invention. First, in step S01, logical design is performed and a netlist is created. Next, in step S02, the circuit division program divides the entire netlist into combinational circuit units and sequential circuit units.

In FIG. 4, an original circuit (A) consisting of two D-type flip-flops (sequential circuits) and four gates (combinational circuits) is a combinational circuit part (B) and a sequential circuit part (C).
Shown as being divided into and. As shown in FIG. 4, the original connection relation of the original circuit (A) is temporarily deformed, so that the combinational circuit only circuit (B) and the sequential circuit only circuit (C).
Becomes This modification is due to the following reason. That is, when only the sequential circuit group or the combinational circuit group is placed in steps S05 and S07 for designating the circuit group placement area in the subsequent stage, the connection quality of each circuit must be completed in the netlist. May be lowered, that is, circuits that should be placed close to each other may be placed far apart. Therefore, in order to arrange the circuits related to each other as close as possible, the connection relation is temporarily deformed. In the final step S09, the connection relation information after the transformation is stored in order to restore the connection relation after the transformation to the original connection relation.

Next, in step S03, the congestion degree of the entire circuit becomes uniform based on the number of parent gates, the number of actually used gates and the number of gates of each of the combinational circuit group and the sequential circuit group, and all the sequential circuits are The total wiring length of the clock mesh main line is calculated so that it is directly connected to the clock mesh main line. FIG. 5 is a diagram for explaining a calculation example for obtaining the wiring length of the main line. Based on FIG.
0 out of 10,000 available gates, 5,
000 gates and 36 in the internal cell placement area 6
The case where the 0 gate sequential circuit 4 and the 4,640 gate combination circuit are arranged will be described. The mother 7 has a length of 10
Gates can be arranged in 0 rows and 100 rows horizontally, and the average number of gates per sequential circuit is 5 gates. The number of arranged columns of the sequential circuit 4 is x, the number of arranged rows is y, and x and y are determined so as to satisfy the following equation.

Gate usage rate (%) with respect to the mother body = 360 / (100x + 100y-
Number of overlapping gates) In FIG. 5, a total of 16 gates are arranged in each of the four corners of the four partitions, since 16 sequential circuit placement areas 4'are overlapping and the number of gates per circuit is 5. It becomes 80 gates. The gate usage rate (%) with respect to the mother body 10 is 50% as described above. When x and y are obtained under these conditions, x = 4 and y = 4 are obtained. Therefore, as shown in FIG. 5, the internal cell placement area 6 has three vertical and three horizontal clock mesh trunk lines 3.
Is divided into 4 sections by a total of 4 lines inside each section,
Four columns of sequential circuits 4 are arranged. When the wiring length per column is 0.2 mm and the wiring length per row is 0.3 mm, the total wiring length is (0.2 × 3) + (0.3 × 3) = 1.5 mm .

Here, since the length of the clock mesh main line is determined based on the number of gates of the combinational circuit and the sequential circuit in this manner, there is no useless clock mesh main line. Returning to FIG. 3 again, the explanation will be continued. Step S
At 04, depending on the type of sequential circuit, step S
The clock mesh trunk line is wired based on the wiring length obtained in 03.

FIG. 6 illustrates how a trunk line arrangement track is selected, a clock mesh trunk line is laid, and clock lead lines are wired in the case of a sequential circuit having normal clock pins. Tracks 9a to 9 for clock mesh main line wiring are provided near the sequential circuits 4a and 4b.
If d is present, the wiring track closest to the clock pins 8a and 8b is 9d, so the clock mesh trunk line 3 is laid at the position of 9d.
Clock lead lines 5a and 5b connect between a and 8b and the clock mesh main line 3. Case 1 is an example in which the sequential circuit arrangement area 40 is designated only for the height of the sequential circuit. Case 2 is an example in which the sequential circuit placement area 40 is designated to be larger than the height of the sequential circuit. Compared to case 1, the sequential circuit 4a is better, but the sequential circuit 4b has the sequential circuit placement area 40 larger than the cell height. Therefore, the rotation of the cell occurs and the position of the clock pin 8b is separated from the main line 3, and the wiring length becomes long. Case 3 is another example in which the sequential circuit arrangement area is designated to be larger than the height of the sequential circuit, and the clock pins 8a and 8b of the sequential circuits 4a and 4b are connected, which may cause clock skew.

FIG. 7 is a diagram showing how to select the trunk line arranging tracks and the wiring of the clock lead lines in the case of a sequential circuit of the type in which the clock pin position is inside the macro cell. Case 1 is a case where the trunk line wiring track 9b is used as the clock mesh trunk line, and the track closest to the clock pin is the track 9b.
The clock mesh main line 3 is laid at the position of b, and the clock lead line 5 is wired between the clock pin 8 and the clock mesh main line 3. When the pattern inside the cell exists in the same layer as the main line, the main track is not 9b but 9a or 9c. Case 2 is an example in which the trunk wiring track 9c becomes the clock mesh trunk 3, and the sequential circuit 4 of Case 1 is used.
The wiring lengths of the clock lead lines 5a and 5b are longer than those of a and 4b. Similarly, Case 3 is another example in which the trunk wiring track 9c is the clock mesh trunk 3, and the clock pins 8a and 8b of the sequential circuits 4a and 4b are connected to each other, which may cause clock skew.

FIG. 8 shows an example in which the trunk line arrangement track 9d exists on the clock pin 8 of the sequential circuits 4a, 4b, 4c. In this case, the wiring length of the clock lead line is zero. FIG. 9 shows an example in which two or more types of sequential circuits are mixed. In FIG. 9, a large sequential circuit arrangement area 40 is designated in accordance with the sequential circuit 4c having the maximum number of gates. In this case, the sequential circuit 4b may rotate like the sequential circuit 4d. For this reason, at the time of automatic placement, it is necessary to take either a measure so as not to rotate the sequential circuit 4b, or to adjust the size of the sequential circuit placement area 40 to a sequential circuit having the minimum number of gates.

In step S05 shown in FIG. 3, the placement area of the combinational circuit group is designated. Next, step S06.
In, the combination circuit group is automatically arranged. Next, in step S07, the placement area of the sequential circuit group is designated. In this case, as described above, the placement area is designated so that the sequential circuit is not rotated or inverted during the automatic placement in the next step S08. When designating the placement area, if the clock mesh trunk line is in the horizontal direction, the sequential circuit placement area is designated according to the height of the sequential circuit as shown in FIG. 6, and if the clock mesh trunk line is in the vertical direction, As shown in FIG. 7, the sequential circuit arrangement area is designated according to the width of the sequential circuit.

Next, in step S08, the sequential circuit group is automatically arranged. Next, in step S09,
The connection relation temporarily deformed in step 02 is restored to the original connection relation, and the nets are rearranged. Finally, in step S10, general nets are automatically routed, and all steps are completed.

Even if steps S05, S06 are replaced with steps S07, S08 in the above process, the same effect can be obtained. Further, the same effect can be obtained by designating and arranging the arrangement areas of the combinational circuit group and the sequential circuit group simultaneously and in parallel. FIG. 10 shows another embodiment of the present invention, in which the sequential circuit 4 is a scan path circuit. In each section divided by the clock mesh main line 3, the clock signal input from the clock driver 1 is transmitted to the sequential circuit 4 from the clock mesh main line 3 through the clock lead line 5. In this case, the net 15 between the scan-in 16 and the scan-out 17 is shorter than that of a normal semiconductor integrated circuit regardless of whether it is a scan-only cell or a cell that also serves as a scan. This is because the sequential circuits 4 are arranged in order, so the pin positions match.
This is an example in which the present invention is more effectively implemented.

FIG. 11 is an enlarged view of a part of FIG. The scan-in 16 to the scan-out 17 are connected by the net 15, while the clock signal from the clock driver 1 is transmitted to each sequential circuit 4 via the clock lead line 5.

[0026]

As described above, according to the present invention, since the clock wiring from the clock pin to all the sequential circuit elements in 1-bit units is shortened, the signal delay is reduced and the skew is reduced. Can be reduced. Further, the wiring capacitance value is also reduced, so that the malfunction of the semiconductor integrated circuit can be prevented.

Further, since the clock mesh main line is mesh-shaped, the clock mesh main lines are arranged evenly over the entire area, so that the lengths of the data lines can be made uniform, the quality of layout design can be improved, and the predetermined area can be improved. As many circuits as necessary can be surely arranged inside, the probability of completing the wiring 100% is increased, and the failure rate of the actual simulation is also reduced.

Further, when arranging the combinational circuits, since the automatic arrangement is performed in consideration of the connection of the sequential circuits, the wiring of the data signal is optimized. Further, when the sequential circuit is a scan path cell, the scan-in and out-out nets are shortened by connecting adjacent scan-in and scan-out pins on the upper, lower, left, and right sides, which simplifies the design.

In addition to the above, the following effects can be expected. (A) It can also be applied to multi-phase clocks. (B) Asynchronous circuits can also be used.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a circuit arrangement area in an embodiment of the present invention.

FIG. 2 is a circuit layout diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating steps for obtaining a semiconductor integrated circuit of the present invention.

FIG. 4 is an explanatory diagram showing a connection relationship when a netlist is divided into combinational circuits and sequential circuits.

FIG. 5 is an explanatory diagram of a calculation example for obtaining the wiring length of the main line.

FIG. 6 shows a case of a sequential circuit having a normal clock pin,
It is a figure which shows the appearance of wiring of a clock mesh main line and wiring of a clock lead-out line.

FIG. 7 is a diagram showing a state of laying a clock mesh main line and wiring of clock lead lines in the case of a sequential circuit of a type in which a clock pin position is inside a macro cell.

FIG. 8 is a diagram showing a state of laying a clock mesh main line and wiring a clock lead line when a track of the clock mesh main line exists on a clock pin of a sequential circuit.

FIG. 9 is a diagram showing a state of laying a clock mesh main line and wiring of clock lead lines when two or more types of sequential circuits are mixed.

FIG. 10 is a diagram showing a connection state of a net between scan-in and scan-out.

11 is an enlarged view of a part of FIG.

FIG. 12 is a schematic diagram for explaining a method of arranging flip-flop circuits side by side in the same row, which is an example of a conventional technique.

FIG. 13 is an example of a conventional technique and is a schematic diagram for explaining a wiring state of a flip-flop circuit in a clock mesh system.

[Explanation of symbols]

 1 Clock Driver 2, 2a to 2c Flip-Flop Circuit 3, 3a to 3d Clock Mesh Main Line 4, 4a to 4b Sequential Circuit 4'Sequential Circuit Arrangement Area Overlap 5a to 5n Clock Leader Line 6 Circuit Arrangement Area 7 Combination Circuit 8 Clock Pin 9a to 9f Main wiring track 10 Base 11 Clock wiring area 12 Flip-flop area 13 Other logic circuit area 14 Wiring area 15 Scan-in / out net 16 Scan-in 17 Scan-out 20 Combination circuit placement area 40 Sequential circuit placement area

Claims (2)

[Claims] 1. A semiconductor integrated circuit having a clock mesh main line for transmitting a predetermined clock signal, which divides a circuit arrangement region in which a sequential circuit and a combinational circuit are arranged into a plurality of mesh-shaped sections, wherein the clock signal is transmitted. All of the 1-bit unit sequential circuit elements are connected to the ends of the respective clock lead lines extending from the clock mesh main line one by one. 2. The semiconductor integrated circuit according to claim 1, wherein all of the 1-bit unit sequential circuit elements are arranged at positions adjacent to the clock mesh main line.