JPH09199598A - Method for automatically disposing and wiring layout design - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to, obtain uniform and high density interconnections without impairing the quality of the layout of the entire board in a semiconductor LSI. SOLUTION: The blank area on a semiconductor substrate 10 in which a hard macro block 12 is disposed is divided into three areas, and standard cell blocks 23A, 23B and 23C of the blocks of lower hierarchy are generated at the respective blank areas. First, when the standard cell blocks 23A, 23B and 23C of the lower hierarchy are disposed and wired, the partial cell is set to a temporarily disposed cell 232 in which the disposing position is not fixed, the residual cells are set to disposition fixed cell 233 in which the disposing positions are fixed, and only the cell 233 is wired. Then, when the blocks of upper hierarchy is generated by using blocks 23A, 23B and 23C of the lower hierarchy, the dispositions of the cells 232 of the temporary disposition are improved, and then the cells 232 of the temporary disposition are wired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing method for layout design in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Layout design methods for LSI semiconductor devices include a gate array (or sea of gate) method and a standard cell method. These methods are
After arranging logic cells such as AND and NOR or a composite cell combining them in an array on the LSI semiconductor substrate, wiring between terminals on the cells is performed in accordance with a desired circuit connection to form an LSI semiconductor device. to make.
Design automation of these methods is progressing, and various design support systems have been developed.

Advances in the manufacturing technology of LSI semiconductor devices have led to the development of embedded array type LSIs in which a gate array type and a standard cell type are integrated. For this, for example, a part or all of the circuit is designed by a predesigned macroblock or a newly designed standard cell type block, and is placed on a semiconductor substrate. Further, an LSI semiconductor device is developed by defining blocks as regions of a gate array in which transistors are spread over each other, and performing generation of the remaining circuits and wiring between functional blocks in the gate array region. Since a circuit can be arbitrarily generated in a region between blocks, the circuit can be added or modified relatively easily before the wiring process is started in the manufacturing process.

In recent years, as called the system-on-silicon era, an LSI semiconductor substrate that has been highly integrated so that a system is mounted on one semiconductor substrate has been developed, and the number of steps required for LSI design is increasing. It's going all the way. The layout design is no exception, and the man-hours and the processing time are exponentially increasing, and it takes a huge amount of time and labor to layout the entire circuit at once. Therefore, in many cases, a hierarchical design method is adopted in which a circuit is divided into several functional blocks, each is individually designed, and finally the functional blocks are wired and assembled. An LS in which a plurality of blocks are assembled hierarchically and a layout is designed as one semiconductor device.
I is called a building block LSI.

The blocks generated when building up by the building block method are hard blocks whose shapes are always fixed. This is because the blocks generated in the middle stage of assembly have completed the arrangement of macroblocks or logic cells contained therein and the wiring between them, so that internal layout pattern information is not particularly necessary. , Only the shape is enough.

Signals are exchanged between the block and the outside through external terminals, and in general, the external terminals are often fixedly arranged on the periphery of the block. Therefore, in the building block method, a plurality of blocks whose shapes and positions of external terminals are fixed are arranged and wiring is provided between them. In other words, the block was treated as a black box with no internal logic or layout information.

In the building block system, macroblocks and standard cells are often combined.

(Conventional Example 1) A conventional automatic layout and wiring method in layout design will be described below with reference to the drawings. 13 and 14 are views showing an automatic placement and routing method in a layout design using a conventional standard cell block. As shown in FIG. 13, I /
Five hard macroblocks 62 each having a predetermined shape are arranged on a semiconductor substrate 60 having an O pad area 61, and an empty area 63 in which a logic circuit is not arranged is formed.
There is The process of determining the layout structure of the semiconductor substrate 60 is called a floor plan. That is, the free area 6
3 shows the step of arranging and wiring the remaining logic circuits using the standard cell block.

As shown in FIG. 14A, an empty area 63
Is divided into three areas, that is, empty areas 63a, 63b, and 63c, to realize layout and wiring. First,
Standard cell blocks 73A, 73B, and 7 according to the sizes of the empty areas 63a, 63b, and 63c.
3C is generated respectively. Next, the layout of standard cells and the wiring between the standard cells are performed for each block to generate hard macro standard cell blocks 73D, 73E, and 73F.
Next, in order to perform wiring between the blocks 73D, 73E, and 73F in the upper layer, each block 73D,
The shapes of 73E and 73F and the position information of the external terminals are obtained. Next, as shown in FIG. 14B, the blocks 73D, 73E, and 73F are arranged by using the information, and wiring between all the blocks on the semiconductor substrate 60 is performed. The wiring pattern 75 in the inter-macroblock wiring area 76 shown in the interblock wiring area enlarged view 74 shows the wiring after the interblock wiring is completed.

It should be noted that the wiring area between blocks tends to be large. This is because by fixing the positions of the external terminals of the blocks when wiring between the blocks, the wiring is biased depending on the arrangement position of the blocks, so that the wiring is likely to be crowded. Conventionally, studies have been conducted on optimization of block shapes and external terminal positions, but a definitive solution or method has not yet been obtained.

(Conventional Example 2) An automatic placement and routing method in a layout design using a conventional spread type standard cell block will be described below. FIG. 15 shows a state in which standard cells are spread over the empty area 63 of the semiconductor substrate 60 shown in FIG. In FIG. 15, first, all the standard cells in the standard cell area 81 are simultaneously arranged in the empty area 63. next,
Wiring between standard cells and between macroblocks is simultaneously performed on the entire semiconductor substrate 60. A feature of this method is that the inter-macroblock wiring area wiring 83 shown in the interblock wiring area enlarged view 82 has the semiconductor substrate 60.
14B, the wiring congestion as shown in FIG. 14B may be difficult to appear. This is because the wiring is optimized for the entire semiconductor substrate 60, so that the wiring can be easily dispersed.

(Prior art example 3) A conventional gate array (embedded array system) in which transistors are spread
The automatic placement and routing method in the layout design using is explained. FIG. 16 shows a state in which the gate array is spread over the empty area 63 of the semiconductor substrate 60 shown in FIG. In FIG. 16A, the gate array region 91 is
This is a circuit in which the circuit configured by the standard cell shown in FIG. 14 or 15 is configured using a gate array (so-called gate arrangement) in the empty area 63. The scale of the circuit composed of the gate array is generally larger than that of the standard cell and not all gates can be used. Therefore, if a semiconductor device of the same scale is developed, the LSI semiconductor device of the standard cell system is used. Area tends to be larger than. Next, as shown in FIG. 16 (b), wiring is simultaneously performed between the gate array and the macro block on the entire semiconductor substrate 60. The inter-gate wiring region enlarged view 92 shows the wiring pattern 93. In this case as well, due to the same reason as in the conventional example 2, uneven wiring congestion is unlikely to occur.

Further, as the operation speed of LSI semiconductor devices has increased in recent years, timing constraints have become stricter.
However, wiring between blocks tends to be long, so be careful of optimizing the placement of blocks and the size of the driver (transistor) that drives the net (set of terminals connected to the same potential). Must.

[0014]

However, the above-described conventional automatic placement and routing methods for each layout design have their respective problems as described below. First, in the case of the conventional example 1, the empty area 63 shown in FIG. 13 is divided into several areas, and independent standard cell blocks 73A, 73B, and 73C are generated for each area. The parallelization has an advantage that a layout can be generated in a short time. However, when building the blocks,
Since all blocks are treated as hard blocks, there is a problem that it is difficult to optimize the wiring between blocks and the wiring area becomes large. Also, regarding the wiring delay constraint for the wiring net that spans between blocks,
Since wiring between blocks is performed after forming hard blocks, the wiring length exceeds the expectation, so that there is also a problem that blocks must be recreated if delay constraints cannot be observed.

Next, in the case of the second conventional example, after the standard cells are arranged in the empty area 63 of the entire semiconductor substrate 60, the wiring is arranged in the entire semiconductor substrate. Since it is possible to optimize the entire semiconductor chip, there is an advantage that a compact layout can be obtained as compared with the conventional example 1. However, since optimization is performed on the entire semiconductor substrate 60,
There has been a problem that enormous processing time is required for a large scale LSI.

Next, in the case of the conventional example 3, as in the case of the conventional example 2, since the gate is arranged and the wiring is performed on the entire semiconductor substrate 60, there is a problem that the processing time becomes huge.

The present invention solves the above-mentioned conventional problems all at once,
It is an object of the present invention to obtain uniform and high-density wiring in a short time without deteriorating the layout quality of the entire chip in a semiconductor LSI.

[0018]

In order to achieve the above-mentioned object, the present invention, when a layout is generated while hierarchically generating blocks as in a building block method, a function block in a functional block in a lower hierarchy is Some logic cells are temporarily arranged without fixing the arrangement position, and when the functional blocks of the lower hierarchy are assembled to generate the functional blocks of the upper hierarchy, the logical cells of the temporary arrangement are optimized. is there.

Specifically, the solving means devised by the invention of claim 1 is a plurality of logic cells each including at least one element,
A placement and routing step of placing a plurality of functional blocks each including at least one logic cell in a predetermined placement area, and then performing wiring between the plurality of logic cells or between the plurality of function blocks according to a logical connection request. , An upper-level functional block generating step of hierarchically generating a higher-level functional block composed of at least one of the functional blocks, the automatic placement-and-routing method of the layout design, In the provisional arrangement in which the arrangement of some of the logic cells is not fixed and the arrangement is such that the remaining logic cells of the logic cells are fixed, a set of terminals to be connected to the same potential by only the remaining logic cells. The step of generating a wiring pattern of a certain net includes the step of generating the higher-level functional block, and determines the placement of the logical cells in the temporary placement. It was followed, in which a structure comprising the step of generating a wiring pattern of the unrouted nets between the functional block or the functional blocks.

According to the structure of claim 1, when arranging and wiring the functional blocks in the lower hierarchy, some logic cells are placed in a temporary arrangement state and only the remaining logic cells are arranged and wired. After that, when the functional block of the upper layer is generated using the functional block of the lower layer, wiring is performed by improving the arrangement between the temporarily arranged logical cells. Since the layout of the logic cells can be optimized, uneven congestion of wirings that occurs when assembling the functional blocks in the higher hierarchy is reduced.

According to a second aspect of the present invention, in the configuration of the first aspect, the upper functional block generating step includes a step of exchanging the temporarily arranged logic cells included in each functional block of a lower hierarchy with each other. Is added.

According to a third aspect of the present invention, in the configuration according to the first aspect, the step of generating the upper functional block includes provisionally starting from the output terminal of the first logic cell in the temporary arrangement in the net extending between the functional blocks in the lower hierarchy. When the signal propagation time, which is the time taken for a signal to propagate to the input terminal of the second logic cell in the arrangement, does not satisfy the required value, the first logic cell has a greater driving capability than the first logic cell. A configuration including a step of replacing with a third logic cell is added.

According to a fourth aspect of the present invention, in the configuration according to the first aspect, the step of generating the upper functional block is provisionally performed from the output terminal of the first logic cell in the temporary arrangement in the net extending between the functional blocks in the lower hierarchy. If the signal propagation time, which is the time taken for the signal to propagate to the input terminal of the second logic cell in the arrangement, does not satisfy the required value, the first logic cell is placed between the first logic cell and the second logic cell. The configuration including the step of inserting the third logic cell adjacent to the logic cell is added.

According to a fifth aspect of the present invention, in addition to the configuration of the fourth aspect, a configuration in which the third logic cell is a buffer cell which has a large driving capability and does not change the logic is added.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) An automatic layout and wiring method for layout design according to a first embodiment of the present invention will be described below with reference to the drawings.

1 to 4 are top views in order of steps showing an automatic placement and routing method in a layout design using a standard cell block according to the first embodiment of the present invention. In FIG. 1, 10 is a semiconductor substrate on which logic cells or functional blocks are arranged, 11 is an I / O pad region for electrically connecting to the outside, 12 is a hard macro block,
13 is an empty area other than the hard macroblock 12.

A layout design method for the semiconductor substrate 10 having the above-described structure will be described. As shown in FIG. 1, it is assumed that there are free areas 13 after five hard macro blocks 12 are arranged on the semiconductor substrate 10. Next, as shown in FIG. 2, the vacant area 13 is divided into the first vacant area 13a, the second vacant area 13b, and the third vacant area 1 respectively.
After being divided into three areas 3c, as shown in FIG.
First standard cell method block 23A is generated for the empty area 13a, second standard cell method block 23B is generated for the second empty area 13b, and third standard cell method block 23B is generated for the third empty area 13c. 3 standard cell block 23C to generate the first free area 1
3a, the second empty area 13b and the third empty area 13c
Place each in.

Next, the method of arranging the cells and the wiring thereof will be described by taking the first standard cell block 23A as an example.

Any conventional method may be used for the cell placement method. For example, the simulated annealing method (known example: Proc. IEEE International Conference on C
omputer Aided Design, 1987, pp.478-481), minimum cut method (known example: Journal of Design Automation and Fa)
ult Tolerant Computing, Vol.1, No.4, 1977, 343-362
), Mathematical programming (known example: Proc. IEEE International
Conference on Computer Aided Design, 1991, pp.48-5
There is a method that applies 1) etc.

With respect to the placement result, as shown in the first standard cell block 23A, the cells connected to the external terminals 231 are treated as temporary placements that can be relocated, and the other cells are set as fixed placement cells. The external terminal 231 is the first
It is assumed to be on the periphery of the standard cell block 23A. In addition, the external terminals 231 can be traced in connection relation.
In the shortest path that reaches from to any cell, the number of cells on the shortest path is called a level. For example, the level of the cell connected to the external terminal 231 is level = 1.

The shaded cells shown in FIG. 3 are temporary placement cells 2.
32, and the white cells are placement fixed cells 233. The fixed placement cell 2 is larger than the temporary placement cell 232.
33 is enlarged to indicate that a plurality of fixed placement cells 233 are arranged side by side. In this embodiment, only the cells connected to the external terminals 231 are temporarily arranged cells 232.
Although (level = 1) is set, it may be defined that level = 2 or more. If the level is defined as the maximum level, all cells are temporary placement cells.

Next, wiring between cells is performed. Note that the placement of the temporary placement cells 232 is not fixed, so that it is impossible to generate a wiring pattern. Temporary placement cell 23
Since 2 only defines the rough wiring route, only the wiring pattern of the fixed placement cells 233 is generated.

Any conventional method may be used for the wiring method. As an example, "Proc. IEEE International Confere
nce Symposium on Circuits and Systems, 1987, pp. 5
18-519 ”.

The above operation is similarly performed for the second standard cell system block 23B and the third standard cell system block 23C to complete the wiring of the first standard cell system block 23A and the second standard cell system block 23C. The cell type block 23B and the third standard cell type block 23C are arranged corresponding to the first empty area 13a, the second empty area 13b and the third empty area 13c on the semiconductor substrate 10 according to the floor plan. .

Next, in order to make the temporarily arranged cells into fixed cells, the arrangement between the temporarily arranged cells is improved in each block. The double-headed arrow shown in FIG. 3 represents the exchange 25. Further, the first standard cell system block 23A and the second standard cell system block 2 shown in FIG.
As in 3B, the arrangement may be improved by exchanging the temporarily arranged cells 26 between the blocks. This makes it possible to improve the layout of chip-level standard cells in consideration of the block position. Furthermore, since only some of the cells on the semiconductor substrate 10 are targeted for layout improvement, the layout improvement can be realized in a short time. After the placement is improved, the temporary placement cell becomes the placement fixed cell.

Next, as shown in FIG. 4, wiring is carried out in the upper hierarchy of the semiconductor substrate level. Since the temporary placement cell 232 becomes the placement fixed cell 233, it becomes possible to wire the net for which the connection request between the block and the cell, which has been the rough wiring path, is targeted and the net between the blocks.
Therefore, like the inter-macroblock wiring area 27 shown in FIG. 4 and the wiring pattern 29 shown in its enlarged view 28, wiring can be performed uniformly and at high density.

As described above, according to the first embodiment, the area is divided into blocks of the lower hierarchy, the lower blocks are individually generated, and then the lower blocks are assembled hierarchically to form the upper hierarchy. When the block is generated, the layout and wiring are optimized using the cells inside the lower block or the layout and wiring information of the lower block, so that the layout with less congestion of the inter-block wiring can be generated. Moreover, since the blocks in the upper hierarchy are generated and the layout and wiring are optimized by using the layout and wiring information of only the cells related between the blocks, high-speed processing is possible.

Further, when generating the blocks of the higher hierarchy, the layout and wiring are not optimized for the entire semiconductor substrate 10, and a part of the data is divided for each block of the lower hierarchy. Since the optimization is performed using
High-density arrangement and wiring can be obtained in a short time.

(Second Embodiment) An automatic placement and routing method for layout design according to a second embodiment of the present invention will be described below with reference to the drawings.

6 to 9 are top plan views in order of the steps showing the automatic placement and routing method in the layout design using the embedded array block according to the second embodiment of the present invention. As shown in FIG. 6, five hard macro blocks 12 are arranged on a semiconductor substrate 10 having an I / O pad region for electrically connecting to the outside in the peripheral portion, and a gate array formation region is formed in the remaining region. Suppose there is 31.

First, the gate array forming region 31 is formed into the first gate array region 31a and the second gate array region 31.
It is divided into three regions of b and the third gate array region 31c. Next, the first gate array block 41a is generated for the first gate array formation region 31a, the second gate array block 41b is generated for the second gate array formation region 31b, and the third gate array block 41b is generated. After the third gate array block 41c is generated in the gate array forming region 31c, the first gate array block 41a and the second gate array block 4 are formed in the gate array forming region 31.
Consider assembling 1b and the third gate array block 41c to generate and arrange one gate array block 41. In addition, the first gate array block 41
It is assumed that a, the second gate array block 41b, and the third gate array block 41c are connected to the outside by using external terminals, respectively, and the arrangement position is on the periphery of each block. For example, the first gate array block 41a inputs / outputs signals using the external terminal 42.

Next, the first gate array block 41a
Taking the example as an example, the arrangement of gates and the wiring method thereof will be described.

First, for the arrangement of the gates, any method may be used as described in the first embodiment. For the placement result, a temporary placement gate is defined as in the first embodiment. The cells connected to the external terminals 42 are treated as a temporary arrangement (temporary arrangement gate 43) whose arrangement can be changed, and the other gates are arranged in a fixed arrangement (arrangement fixed gate 44).
Further, as in the first embodiment, in the shortest path reaching from the external terminal 42 to an arbitrary gate, the number of gates on the path is called a level. For example, the external terminal 42
The gate connected to is level = 1. In FIG.
The hatched rectangle is the temporary placement gate 43, and the gate shown in white is the placement fixed gate 44. In the present embodiment, only the gate connected to the external terminal 42 is set as the temporary placement gate 43 and the level is set to 1. However, level =
Two or more may be defined.

Next, wiring between the gates is performed. Since the placement of the temporary placement gate 43 is not fixed, a wiring pattern cannot be generated, and therefore only a rough wiring route is defined.
Therefore, the wiring pattern is generated only for the fixed placement gates 44. After the above operation is similarly performed for the second gate array block 41b and the third gate array block 41c, the first gate array block 41a and the second gate array block 41b whose wiring is completed are completed.
And the third gate array block 41c are assembled,
The gate array block 41 is generated and arranged on the semiconductor substrate 10 according to the floor plan.

Next, in order to use the temporary placement gate 43 as the placement fixed gate 44, the placement of the temporary placement gates 43 in the block is improved. Further, the placement of the temporary placement gate 43 may be improved between the blocks, such as the temporary placement gate 43 of the first gate array block 41a and the temporary placement gate 43 of the second gate array block 41b. This makes it possible to improve the arrangement of gates at the semiconductor substrate level in consideration of block positions. Furthermore, since only some gates of the entire semiconductor substrate 10 are targeted for layout improvement, high-speed layout improvement is possible. When the arrangement is improved, the temporary arrangement gate 43 becomes the arrangement fixed gate 44.

Next, as shown in FIG. 9, wiring is performed in the upper hierarchy of the semiconductor substrate level. As the wiring method, any method may be used as in the first embodiment. Since the temporary placement gate 43 becomes the placement fixed gate 44, it is possible to wire the net which is a rough wiring path and the net between blocks. Like the inter-gate wiring region 47 shown in FIG. 9 and the wiring pattern 46 shown in its enlarged view 45, wiring can be performed uniformly and at high density.

As described above, the present invention can also be applied to an embedded array type LSI.

(Third Embodiment) An automatic placement and routing method for layout design according to a third embodiment of the present invention will be described below with reference to the drawings.

FIG. 10 is a top view showing cell replacement in the automatic placement and routing method in the layout design according to the third embodiment of the present invention. After the generation and placement of the standard cell block shown in FIG. , The state immediately after the improvement of the arrangement of the temporarily arranged cells is shown. Further, in the first standard cell system block 23A, the second standard cell system block 23B, and the third standard cell system block 23C, the wiring delay constraint and the layout of the net that connects the temporary placement cell and the placement fixed cell to each other. It is assumed that the wiring delay constraint of the net in which fixed cells are connected to each other is satisfied.

As shown in the enlarged view 50 of FIG. 10, the temporarily arranged cells 51 and the first standard cell method block 23A included in the second standard cell method block 23B are included.
Suppose that the wiring delay time t ₀ between the provisionally arranged cells 52 included in the above is larger than the delay constraint request value t (t <t ₀ ), the wiring delay constraint is not satisfied, and thus t ₀ needs to be reduced. is there. In order to satisfy the wiring delay constraint, a new cell 53 having the same logic and a driving capacity larger than that of the temporary placement cell 51 is replaced with the temporary placement cell 51. That is, assuming that the value of the delay time of the signal reaching the temporary placement cell 52 from the new cell 53 is t ₁ , the new cell 5 such that t> t ₁ is satisfied.
3 is replaced with the temporary placement cell 51. At this time, the placement positions of the placement fixed cell 54 and the placement fixed cell 55 remain fixed, and the connection relationship between the placement fixed cell 54 and the temporary placement cell 51 is realized between the placement fixed cell 54 and the new cell 53. do it. If the new cell 53 is larger in area than the temporary placement cell 51, it is placed after securing a space for the new cell 53. In order to secure the space, the cells near the new cell 53 will move,
Even if the value of the wiring delay time changes a little, it does not cause a problem because it requires only a minute movement.

As described above, according to the third embodiment, in order to satisfy the wiring delay constraint between blocks, it is realized only by replacing a cell having a large driving capability without changing the logic with a temporarily arranged cell. Therefore, the correction is minimized, which enables high-speed processing.

(Fourth Embodiment) An automatic placement and routing method for layout design according to a fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 is a top view showing the insertion of cells in the automatic placement and routing method in the layout design according to the fourth embodiment of the present invention. After the generation and placement of the standard cell block shown in FIG. , The state immediately after the improvement of the arrangement of the temporarily arranged cells is shown. Also, as in the third embodiment, the first standard cell block 23A,
In the second standard cell block 23B and the third standard cell block 23C, the wiring delay constraint of the net connecting the temporary placement cell and the fixed placement cell and the wiring delay of the net connecting the fixed placement cells The constraints are satisfied. Further, the temporary placement cells 51 included in the second standard cell block 23B are included.
And the wiring delay time t ₀ between the provisionally arranged cells 52 included in the first standard cell block 23A is larger than the delay constraint request value t (t <t ₀ ).

A feature of this embodiment is that a new cell 57 having a large driving capability without changing the logic is inserted between the temporary placement cell 51 and the temporary placement cell 52. That is, assuming that the value of the delay time reaching the temporary placement cell 51, the new cell 57, and the temporary placement cell 52 is t2, the new cell 57 such that t> t2 is provided between the temporary placement cell 51 and the temporary placement cell 52. To insert. At this time, the arrangement fixing cell 54 and the arrangement fixing cell 5
The position of arrangement with 5 remains fixed, and the new cell 57 is arranged adjacent to the temporary arrangement cell 51. Further, as in the third embodiment, it is assumed that a space for inserting the new cell 57 is secured and then arranged. To secure space,
A cell in the vicinity of the new cell 57 may move, and the wiring delay value may change slightly, but since it is a minute movement, there is no problem. As shown in FIG. 12, the connection relationship is
After connecting the temporary placement cell 51 and the new cell 57, the connection relationship between the temporary placement cell 51 and the temporary placement cell 52 may be realized between the new cell 57 and the temporary placement cell 52.

As described above, according to the fourth embodiment, a cell (for example, a buffer cell) having a large driving capability without changing the logic is adjacent to the temporary placement cell so as to satisfy the wiring delay constraint between the blocks. Since it is realized only by inserting, the correction is minimized and high-speed processing is possible.

[0056]

As described above, according to the layout design automatic placement and routing method of the first aspect of the present invention, placement is performed using placement and routing information of cells (or functional blocks) in functional blocks in a lower hierarchy. Since the wiring is optimized, the uneven congestion of the wiring that occurs when assembling the functional blocks in the higher hierarchy is reduced, so that the wiring density becomes uniform.

Further, when assembling the functional blocks in the upper hierarchy, the optimization is performed by using the layout and wiring information of only the logic cells related to the functional blocks, so that the processing can be performed at high speed and the layout and wiring can be performed. Since optimization is not performed on the entire semiconductor substrate but using partial data for each functional block of the divided lower hierarchy, optimization can be performed in the minimum time, Uniform and high-density arrangement and wiring can be obtained in a short time without impairing a high-quality layout.

According to the automatic placement and routing method of the layout design of the second aspect of the present invention, the driving capability included in each functional block in the lower hierarchy so as to satisfy the wiring delay constraint of the wiring net related to the temporarily placed logic cell. The layout is improved by exchanging it with another logic cell with a high level, and the logic cells other than the temporarily arranged logic cell are not subject to the exchange, so that the minimum modification is made in a short time without impairing the high-quality layout. A uniform and high-density wiring can be obtained.

According to the automatic placement and routing method of the layout design of the invention of claim 3, the first logic cell is set to the first logic cell so as to satisfy the wiring delay constraint of the wiring net relating to the temporarily placed logic cell. The layout is improved by replacing it with a third logic cell having a larger drive capacity, and the logic cells other than the temporarily arranged logic cells are not targeted for replacement. It is possible to obtain uniform and high-density wiring in a short time without damaging the wiring.

According to the automatic placement and routing method of the layout design of the fourth aspect of the present invention, the third layout is adjacent to the first logic cell so as to satisfy the wiring delay constraint of the wiring net related to the temporarily arranged logic cell. The layout is improved by inserting the logic cells, and the logic cells other than the temporarily arranged logic cells are not targeted for insertion.Therefore, the minimum modification has been made so that high-quality layout can be performed uniformly and with high quality in a short time. High density wiring can be obtained.

According to the layout layout automatic placement and routing method of the fifth aspect of the present invention, the third logic cell inserted adjacent to the first logic cell has a large driving capability and does not change the logic. Since the buffer cells are used, the layout can be improved so that the wiring delay constraint is surely satisfied.

[Brief description of drawings]

FIG. 1 is a top view in process order showing an automatic placement and routing method in a layout design using a standard cell block according to a first embodiment of the present invention.

2A to 2C are top views in order of the steps, showing an automatic placement and routing method in a layout design using a standard cell block according to the first embodiment of the present invention.

FIG. 3 is a top view in process order showing an automatic placement and routing method in a layout design using a standard cell block according to the first embodiment of the present invention.

FIG. 4 is a top view in process order showing an automatic placement and routing method in a layout design using a standard cell block according to the first embodiment of the present invention.

FIG. 5 is a diagram showing cell exchange between blocks in an automatic placement and routing method in a layout design using a standard cell block according to the first embodiment of the present invention.

FIG. 6 shows an embedded system according to a second embodiment of the present invention.
FIG. 7 is a top view in order of the processes, showing an automatic placement and routing method in a layout design using an array block.

FIG. 7 shows an embedded system according to a second embodiment of the present invention.
FIG. 7 is a top view in order of the processes, showing an automatic placement and routing method in a layout design using an array block.

FIG. 8 shows an embedded system according to a second embodiment of the present invention.
FIG. 7 is a top view in order of the processes, showing an automatic placement and routing method in a layout design using an array block.

FIG. 9 is an embedded system according to a second embodiment of the present invention.
FIG. 7 is a top view in order of the processes, showing an automatic placement and routing method in a layout design using an array block.

FIG. 10 is a top view showing cell replacement in the automatic placement and routing method in the layout design according to the third embodiment of the present invention.

FIG. 11 is a top view showing insertion of cells in the automatic placement and routing method in the layout design according to the fourth exemplary embodiment of the present invention.

FIG. 12 is a diagram showing a connection relationship after insertion of cells in the automatic placement and routing method in the layout design according to the fourth exemplary embodiment of the present invention.

FIG. 13 is a process sequence top view showing an automatic placement and routing method in a layout design using a conventional standard cell block.

FIG. 14 is a process sequence top view showing an automatic placement and routing method in a layout design using a conventional standard cell block.

FIG. 15 is a process sequence top view showing an automatic layout and wiring method in a layout design using a conventional spread type standard cell block.

FIG. 16 is a process sequence top view showing an automatic placement and routing method in a layout design using a conventional embedded array system block.

[Description of Reference Signs] 10 semiconductor substrate 11 I / O pad area 12 hard macro block 13 empty area 13a first empty area 13b second empty area 13c third empty area 23A first standard cell block 23B second Standard cell system block 23C Third standard cell system block 231 External terminal 232 Temporary placement cell 233 Placement fixed cell 25 Exchange 26 Exchange 27 Macroblock wiring area 28 Enlarged view 29 Wiring pattern 31 Gate array forming area 31a First gate Array forming area 31b Second gate array forming area 31c Third gate array forming area 41 Gate array block 41a First gate array block 41b Second gate array block 41c Third gate array block 42 External Child 43 Temporary placement gate 44 Placement fixed gate 45 Enlarged view 46 Wiring pattern 47 Inter-gate wiring area 50 Enlarged view 51 Temporary placement cell 52 Temporary placement cell 53 New cell 54 Placement fixed cell 55 Placement fixed cell 56 Enlarged view 57 Temporary placement cell 60 Semiconductor substrate 61 I / O pad area 62 Hard macro block 63 Free area 63a Free area 63b Free area 63c Free area 73A Standard cell type block 73B Standard cell type block 73C Standard cell type block 73D Hard macro type standard cell type block 73E Hard macro standard cell block 73F Hard macro standard cell block 74 Expanded wiring area between blocks 75 Wiring pattern 76 Macro block Wiring region 81 standard cell area 82 inter-block wiring area enlargement 83 wiring pattern 84 macro-blocks between wiring region 91 gate array region 92 gate wiring area enlargement 93 wiring pattern

Claims (5)

[Claims] 1. A plurality of logic cells each including at least one element and a plurality of function blocks each including at least one logic cell are respectively arranged in a predetermined arrangement region, and then the plurality of logic cells or the plurality of functions are arranged. Automatic layout of layout design including a placement and routing step of performing wiring between blocks according to a logical connection request, and a higher-level functional block generation step of hierarchically generating a higher-level functional block including at least one of the functional blocks A wiring method, wherein the placement and routing step is a temporary placement in which the placement of some of the logic cells among the logic cells is not fixed, and a placement in which the remaining logic cells of the logic cells are fixed, Including a step of generating a wiring pattern of a net, which is a set of terminals to be connected to the same potential, using only the remaining logic cells, The layout functional block generation step includes a step of generating a wiring pattern of an unwired net in the functional block or between the functional blocks after determining the placement of the temporarily arranged logic cells. Automatic place and route method. 2. The layout design according to claim 1, wherein the upper functional block generation step includes a step of exchanging the temporarily arranged logic cells included in each functional block of a lower hierarchy with each other. Automatic place and route method. 3. The high-order functional block generation step, in the net spanning between the functional blocks of a lower hierarchy,
When the signal propagation time, which is the time required for a signal to travel from the output terminal of the temporarily arranged first logic cell to the input terminal of the temporarily arranged second logic cell, does not satisfy the required value, the first logic cell is 2. The automatic layout and wiring method for layout design according to claim 1, further comprising a step of substituting a third logic cell having a driving capability larger than that of the first logic cell. 4. In the step of generating and generating the upper and upper functional blocks, in the net extending between the functional blocks in the lower hierarchy, the output terminal of the temporarily arranged first logic cell to the input terminal of the temporarily arranged second logic cell. If the signal propagation time, which is the time for the signal to travel through, does not satisfy the required value, a third signal is provided between the first logic cell and the second logic cell adjacent to the first logic cell. The automatic layout and wiring method for layout design according to claim 1, further comprising a step of inserting a logic cell. 5. The automatic layout and wiring method for layout design according to claim 4, wherein said third logic cell is a buffer cell which has a large driving capability and whose logic is not changed.