JP2000040750A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the missing of the gate oxide film on the side of the N- type polysilicon gate by the difference of etching rates and to achieve the thin gate oxide film, by forming N-type polysilicon and P-type polysilicon in the different processes, when the polysilicon gates having the different polarities are formed. SOLUTION: Ions of 31P+ of N-type impurities 1E14-5E14 are implanted. The polysilicon at the part, which is not masked by photoresist, is set to be N-type polysilicon 4. Then, the region, where N-type impurities are not injected, is masked by the photoresist. The ions 11B+ of P-type impurities are injected as 1E14-1E25 ions, and P-type polysilicon 6 is formed. Thereafter, for patterning the N-type polysilicon 4, the total surface of the P-type polysilicon 6 and a part of the N-type polysilicon are masked with the photoresist, and dry etching is performed. Similarly, the dry etching of the P-type polysilicon 6 is performed for patterning the P-type polysilicon 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to the formation of a heteropolar polysilicon gate.

[0002]

2. Description of the Related Art Conventionally, when forming polysilicon gates having different polarities, a polysilicon is deposited by a CVD method after forming a gate oxide film, P-type impurities are ion-implanted over the entire surface of the substrate, and then the oxide film is formed. Deposition is performed, and an oxide film is left only in a region where a P-type polysilicon gate is to be formed by a photolithography process and an etching process. Next, phosphorus which is an N-type impurity is diffused by heat treatment in a region not masked by the oxide film. At this time, phosphorus is not diffused in a portion masked by the oxide film. The masked oxide film is removed at the same time as the phosphorus glass generated after the diffusion of the N-type impurity is removed.

After that, an N-type polysilicon gate and a P-type polysilicon gate are formed in the same process by a photolithography process and an etching process.

[0004]

Heretofore, an N-type polysilicon gate and a P-type polysilicon gate have been simultaneously formed by etching. Since the sheet resistance of N-type polysilicon and P-type polysilicon is higher than that of N-type polysilicon, the etching rate of P-type polysilicon is lower than that of P-type polysilicon. Therefore, when forming an N-type polysilicon gate and a P-type polysilicon gate by etching in the same process, it is necessary to adjust the etching time to P-type polysilicon having a slow etching rate. If the etching time is adjusted to the P-type polysilicon, the N-type polysilicon becomes longer than the desired etching time. Therefore, when the gate oxide film on the side of the N-type polysilicon gate is thick (300 Å or more), there is no particular problem. It is difficult to reduce the thickness of the gate oxide film.

The present invention solves these problems.
It is an object of the present invention to provide a semiconductor device capable of coping with a reduction in the thickness of a gate oxide film in forming a polysilicon gate having a different polarity.

[0006]

Therefore, according to the present invention, after forming a gate oxide film and polysilicon on a semiconductor substrate, polysilicon having different polarities is formed by ion implantation, and the polarities are formed by separate photolithography and etching steps. Different polysilicon gates are formed.

[0007]

According to the present invention, when forming polysilicon gates having different polarities, N-type polysilicon and P-type polysilicon are formed in separate steps, respectively, so that N-type polysilicon and P-type polysilicon are formed. It is possible to prevent the gate oxide film on the N-type polysilicon gate side from coming off due to a difference in etching rate, and to make the gate oxide film thinner.

That is, when forming polysilicon gates having different polarities, an N-type polysilicon gate and a P-type polysilicon gate are separately formed by performing a photolithography step and an etching step, respectively. , It is possible to prevent the gate oxide film on the N-type polysilicon gate side from coming off due to the formation in the same step.

If this method is applied to the first invention,
In forming polysilicon gates having different polarities, the thickness of the gate oxide film can be reduced.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A gate oxide film 2 is thermally oxidized on a silicon substrate 1 to a thickness of 100 to 200 angstroms, and a polysilicon 3 is further deposited thereon by a CVD method at 3000 to 400 angstroms.
0 angstrom is formed. FIG. 1 shows this state.
It is.

Thereafter, a region where a P-type polysilicon gate is to be formed is masked with a photoresist 5 by a photolithography process. Then, ³¹ P ⁺ which is an N-type impurity is
A portion of the polysilicon which is not masked with the photoresist by the ion implantation of 14 to 5E14 is set as an N-type polysilicon 4. FIG. 2 shows this state. The dose at the time of ion implantation is changed depending on the target value of the polysilicon resistance.

Thereafter, the photoresist is peeled off. Next, the region into which the N-type impurity has been ion-implanted is masked with a photoresist 5 to remove ¹¹ B ⁺ , which is a P-type impurity, from 1E14 to
P-type polysilicon 6 by 1E15 ion implantation
Is formed. FIG. 3 shows this state. Also in this case, there is no problem even if the ion implantation amount is out of the above range depending on the target value.

Thereafter, in order to pattern the N-type polysilicon gate, the entire region of the P-type polysilicon 6 is
Mask a part of the mold polysilicon 4 with a photoresist,
N-type polysilicon is formed by dry etching.
Thereafter, the photoresist 5 is removed. FIG. 4 shows this state.

Next, in order to pattern the P-type polysilicon gate in the same manner, a part of the N-type polysilicon region and the P-type polysilicon region is masked with a photoresist, and the P-type polysilicon is dry-etched. Form. Thereafter, the photoresist 5 is removed. FIG. 5 shows this state.

The present invention is not limited to the embodiment described above.

In the above embodiment, first, N
N-type polysilicon and P-type polysilicon are formed, and then N
The patterning of the p-type polysilicon gate and then the patterning of the p-type polysilicon gate were performed. As a process flow, first, an n-type polysilicon was formed by ion implantation, and then an n-type polysilicon gate was formed by patterning. Next, a P-type polysilicon gate may be formed in a similar manner.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0019]

As described above, according to the present invention, in the step of forming polysilicon gates having different polarities, the N-type polysilicon gate and the P-type polysilicon gate are formed in separate steps. , The gate oxide film on the N-type polysilicon side can be prevented from coming off, and the gate oxide film can be made thinner.

[Brief description of the drawings]

FIG. 1 is a diagram showing a state in which a gate oxide film and polysilicon of the present invention are formed.

FIG. 2 is a diagram showing a state in which N-type polysilicon is formed by ion implantation according to the present invention.

FIG. 3 is a diagram showing a state in which P-type polysilicon is formed by ion implantation according to the present invention.

FIG. 4 is a view showing a state where an N-type polysilicon of the present invention is patterned.

FIG. 5 is a view showing a state where a P-type polysilicon of the present invention is patterned.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 gate oxide film 3 polysilicon 4 N-type polysilicon 5 photoresist 6 P-type polysilicon

Claims (2)

[Claims] In a process of forming polysilicon gates having different polarities on a semiconductor substrate, after forming a gate oxide film on the entire surface of the substrate, the polysilicon is deposited by a CVD method, and N-type polysilicon and P-type polysilicon are ionized. A method of manufacturing a semiconductor device, comprising: forming an N-type polysilicon gate and a P-type polysilicon gate separately by a photolithography process and an etching process. 2. In a step of forming polysilicon gates having different polarities on a semiconductor substrate, after forming a gate oxide film on the entire surface of the substrate, the polysilicon is deposited by a CVD method, partially masked with a photoresist, and ion-implanted. To form N-type polysilicon, then photolithography again,
A semiconductor device characterized by first patterning an N-type polysilicon gate by etching, and then patterning a P-type polysilicon gate by the same method.