JPH11111638A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method by which the formation of a channel stop and control of a channel threshold are performed simultaneously with one-time ion implantation. SOLUTION: After an oxide film 12 has been formed on the surface of a p-type semiconductor substrate 11 by oxidizing the surface and a silicon nitride film is formed on the oxide film 12, a silicon nitride film pattern 13, which demarcates an element region is formed by patterning the silicon nitride film. Then an implanting region 14 for forming channel stop and an implanting region 15 for controlling channel threshold are formed at the same time, immediately below the oxide film 12 and below the silicon nitride pattern 13, respectively, by implanting the p-type impurity ions into the substrate 11 with an accelerating voltage which makes the ions pass through part of the silicon nitride film. In addition, a field oxide film 16 is formed by oxidizing the substrate 11 and a p<+> -type channel stop 17 and a threshold-controlled p-type channel region 18 are respectively formed, immediately below the field oxide film 16 and below the silicon nitride film pattern 13, respectively through one-time ion implantation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for controlling a channel threshold in a MOS type semiconductor device.

[0002]

2. Description of the Related Art In order to prevent a parasitic channel generated immediately below a field oxide film, an impurity of the same conductivity type as that of a semiconductor substrate or a well is ion-implanted before a LOCOS oxidation process, and a channel stop is formed immediately below the field oxide film. Has formed.

A MOS transistor having a low channel threshold operates at a low power supply voltage, but has problems such as a large leakage current and a low sensitivity to noise, that is, a malfunction even with a small noise. Requires a MOS transistor having an appropriate channel threshold value. For this purpose, a field oxide film is formed on a semiconductor substrate or a well, a gate oxide film is formed on an element region, and an impurity of the same conductivity type as that of the semiconductor substrate or the well is ion-implanted into the element region to control a channel threshold value. That is being done.

However, when forming the channel stop and controlling the channel threshold, impurities of the same conductivity type as the semiconductor substrate or the well are ion-implanted, but they are formed in different steps at different acceleration voltages and doses. In addition, when simultaneously forming a MOS transistor that requires the control of the channel threshold and a MOS transistor that does not require the control of the channel threshold in the semiconductor substrate, the latter element region includes, for example, In addition, a resist mask must be provided to prevent ions to be implanted, which complicates the manufacturing process and lowers the yield.

[0005]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device in which the formation of a channel stop and the control of a channel threshold are simultaneously performed by one ion implantation.

Another object of the present invention is to provide a method of manufacturing a semiconductor device in which a MOS transistor that requires control of the channel threshold and a MOS transistor that does not require control of the channel threshold are formed simultaneously by one ion implantation. Is to do.

[0007]

According to the present invention, a semiconductor substrate or well is oxidized to form an oxide film on the surface when forming a channel stop and controlling a channel threshold simultaneously by one ion implantation. Depositing a nitride film on the oxide film, patterning the nitride film to form a nitride film pattern that defines an element region, and then applying an acceleration voltage partially transmitting the nitride film to the semiconductor substrate or the well. Ion implantation of impurities of the same conductivity type into the semiconductor substrate or well to simultaneously form an implantation region for forming a channel stop immediately below the oxide film and an implantation region for controlling a channel threshold below the nitride film pattern, Oxidizing the semiconductor substrate or well to form a field oxide film, forming a channel stop immediately below the field oxide film, Forming a threshold controlled channel regions at the bottom of the monolayer pattern.

[0008]

DETAILED DESCRIPTION OF THE INVENTION The present inventor has proposed that a silicon nitride film necessary for forming a field oxide film on a semiconductor substrate via an oxide film and defining an element region is formed to a predetermined thickness, for example, 150 nm.
When an impurity such as phosphorus (P) or boron (B) is ion-implanted into the semiconductor substrate through the silicon nitride film while being deposited to a thickness of 0 Å, the impurity is opaque at an acceleration voltage of 35 KeV or less. And 40-80 Ke
It was found that V was partially transmissive and V was transmitted at 150 KeV. The present invention has been made based on such knowledge, and has been described in connection with the formation of a channel stop of a MOS transistor by utilizing the fact that the impurity partially transmits through the silicon nitride film when the acceleration voltage is 40 to 80 KeV. This is applied to control of a channel threshold.

In the present invention, a semiconductor substrate is oxidized to form an oxide film on the surface, a silicon nitride film is deposited on the oxide film, and the silicon nitride film is patterned to define an element region. A silicon nitride film pattern is formed. Next, an impurity of the same conductivity type as that of the semiconductor substrate is ion-implanted into the semiconductor substrate at an acceleration voltage partially transmitting the silicon nitride film, and an implantation region for forming a channel stop and the silicon nitride film are formed immediately below the oxide film. At the same time, an implantation region for controlling a channel threshold is formed below the pattern, the semiconductor substrate is oxidized to form a field oxide film, and a channel stop is formed immediately below the field oxide film by one ion implantation. A channel region whose threshold is controlled is formed below the silicon nitride film pattern.

When forming a MOS transistor that does not require the threshold control on the semiconductor substrate, a resist mask for selectively removing the silicon nitride film is left on the silicon nitride film pattern to form the ion mask. Implantation is performed to prevent impurity ions from penetrating the silicon nitride film.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described with reference to a first embodiment. FIGS. 1A to 1C show steps of simultaneously forming a channel stop and controlling the channel threshold of a MOS transistor by one ion implantation.

As shown in FIG. 1A, a p-type semiconductor substrate 11 or a p-well is oxidized to form an oxide film 12 on the substrate surface.
To a thickness of 250-850 angstroms, for example, 4
After being formed to a thickness of 30 angstroms, a silicon nitride film is formed on the oxide
Deposit to a thickness of 0 Angstroms, for example 1500 Angstroms. Next, the silicon nitride film is patterned by using a lithography technique to form a silicon nitride film pattern 13 on the oxide film 12 which is surrounded by a field oxide film and defines an element region. Thereafter, according to the thickness of the silicon nitride film, boron (B) is applied at an acceleration voltage of 4 to a part of the silicon nitride film pattern 13 at a dose of 2 to 10 × 10 ¹² cm ^−2.
Ion implantation into the semiconductor substrate 11 at 0 to 80 KeV,
Immediately below the oxide film 12, the implantation region 14 for forming the channel stop and the implantation region 15 for controlling the channel threshold are formed simultaneously below the silicon nitride film pattern 13.

As shown in FIG. 1B, when the semiconductor substrate 11 is oxidized, only the field portion is oxidized to form a field oxide film 16, and at the same time, the implantation regions 14, 15 are driven in. A p ⁺ -type channel stop 17 is formed directly below the field oxide film 16, and a p-type channel region 18 having a threshold controlled below the silicon nitride film pattern 13.

As shown in FIG. 1C, the silicon nitride film pattern 13 and the oxide film 12 are sequentially removed to form a p ⁺ type channel stop 17 immediately below the field oxide film 16. The semiconductor substrate 11 having the p-type channel region 18 in the element region is obtained.

Thereafter, a predetermined MOS transistor is formed on the exposed substrate surface by applying a normal silicon gate process.

A method for manufacturing a semiconductor device according to the present invention will be described with reference to a second embodiment. 2 (a) to 2 (d) show steps of simultaneously forming a channel stop and controlling the channel threshold of a MOS transistor by one ion implantation, and forming a MOS transistor which does not require the threshold control.

As shown in FIG. 2A, the p-type semiconductor substrate 21 or the p-type well is oxidized to form an oxide film 22 on the substrate surface.
To a thickness of 250-850 angstroms, for example, 4
After being formed to a thickness of 30 angstroms, a silicon nitride film 23 is deposited on the oxide film 22 to a thickness of 1000 to 3000 angstroms, for example, a thickness of 1500 angstroms. Next, the silicon nitride film 23
A resist film is applied thereon and patterned to form resist masks 24 and 25.

As shown in FIG. 2B, the silicon nitride film 23 is selectively removed using the resist masks 24 and 25, and an element region surrounded by a field oxide film on the oxide film 12 is formed. Silicon nitride film patterns 26 and 27 to be defined are formed. Thereafter, the resist mask 24 is removed from the silicon nitride film 26 for the MOS transistor section 28 whose channel threshold value is to be controlled, so that the MOS transistor section 2 which does not need to control the channel threshold value.
For 9, the resist mask 25 is left on the silicon nitride film 27.

In this state, boron (B) is dosed at a dose of 2 to 2.
At 10 × 10 ¹² cm ⁻² , ions are implanted into the semiconductor substrate 21 at an acceleration voltage of 40 to 80 KeV that partially penetrates the silicon nitride film 26, and the implantation region 31 for forming the channel stop is formed immediately below the oxide film 22. And an injection region 32 for controlling the channel threshold is formed at the same time under the silicon nitride film 26. In this case, since the resist mask 25 remains on the silicon nitride film 27, no implantation region is formed.

As shown in FIG. 2C, when the semiconductor substrate 21 is oxidized, only the field portion is oxidized to form a field oxide film 33, and at the same time, the implantation regions 31, 32 are driven in. A p ⁺ -type channel stop 34 is formed immediately below the field oxide film 33, and a p-type channel region 35 whose threshold is controlled is formed below the silicon nitride film 26.

As shown in FIG. 2D, by sequentially removing the resist mask 25, the silicon nitride films 26 and 27, and the oxide film 22, a p ⁺ type channel stop immediately below the field oxide film 33 is formed. 34,
The semiconductor substrate 21 having the p-type channel region 35 in the MOS transistor portion 28 and no channel region in the MOS transistor portion 29 is obtained.

Thereafter, a predetermined MOS transistor is formed on the exposed substrate surface by applying a normal silicon gate process.

In each of the above embodiments, the accelerating voltage for partially transmitting the silicon nitride film is set to 40 to 80 KeV, but the accelerating voltage depends on the thickness of the silicon nitride film or the permeation amount (implantation amount). It is adjusted to the above range.

[0024]

According to the present invention, a channel stop formed immediately below a field oxide film and a channel region with a controlled channel threshold are formed once by utilizing the fact that impurities partially pass through a silicon nitride film. Since a series of steps such as resist coating, baking, exposure, unnecessary resist removal, and channel ion implantation at the time of forming the channel region are omitted, the manufacturing process is simplified and the reliability is improved. A semiconductor device is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a process of simultaneously forming a channel stop and controlling a channel threshold according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a channel stop formation and a control of a channel threshold value according to a second embodiment of the present invention.
It is a figure which shows the process which makes the said threshold value control unnecessary.

[Explanation of symbols]

11: p-type semiconductor substrate, 12: oxide film, 13: silicon nitride film pattern, 14, 15: implantation region, 16: field oxide film, 17: p ⁺ type channel stop, 18 ...
p-type channel region, 21 ... p-type semiconductor substrate, 22 ...
Oxide film, 23: silicon nitride film, 24, 25: resist mask, 26, 27: silicon nitride film pattern, 31,
32: implantation region, 33: field oxide film, 34: p ⁺
Channel stop, 35 ... p-type channel region

Claims (3)

[Claims] A step of oxidizing a semiconductor substrate or a well to form an oxide film on a surface thereof; a step of depositing a nitride film on the oxide film; and patterning the nitride film to define an element region. Forming a nitride film pattern, and ion-implanting an impurity of the same conductivity type as that of the semiconductor substrate or the well into the semiconductor substrate or the well with an acceleration voltage partially transmitting the nitride film, and channel stopping immediately below the oxide film. Simultaneously forming an implantation region for formation and an implantation region for controlling a channel threshold below the nitride film pattern; oxidizing the semiconductor substrate or well to form a field oxide film, directly under the field oxide film; Forming a channel stop and forming a threshold-controlled channel region below the nitride film pattern. Method of manufacturing a conductor arrangement. 2. A step of oxidizing a semiconductor substrate or well to form an oxide film on the surface, a step of depositing a nitride film on the oxide film, and a step of applying a resist on the nitride film and patterning the resist. 1
Forming a second resist mask and using the first and second resist masks to selectively remove the nitride film to form first and second element regions.
Forming a nitride film pattern, removing one of the first and second resist masks from the first and second nitride film patterns, and accelerating partially transmitting the nitride film. An impurity of the same conductivity type as that of the semiconductor substrate or the well is ion-implanted into the semiconductor substrate or the well by a voltage, and an implantation region for forming a channel stop and the first and second nitride film patterns are formed immediately below the oxide film. Simultaneously forming an implantation region for channel threshold control under one of the following, forming a field oxide film by oxidizing the semiconductor substrate or well, and forming a channel stop immediately below the field oxide film, Forming a threshold-controlled channel region under one of the first and second nitride films. Production method. 3. An acceleration voltage partially transmitting through the nitride film is 4
3. The voltage of 0 to 80 KeV.
The manufacturing method of the semiconductor device described in the above.