JP3064330B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a silicon substrate region (hereinafter referred to as a channel stopper region) in which an impurity is implanted into an electrical isolation region on a semiconductor substrate. )).

[Prior Art] With an increase in integration degree due to a reduction in transistor size, an element isolation region between transistors is also reduced. When the element isolation region is reduced, punch-through easily occurs between diffusion layers between transistors. Therefore, a channel stop layer having a higher impurity concentration than the silicon substrate is formed in the channel stopper region below the field oxide film formed in the element isolation region.

A conventional method of manufacturing a channel stop layer will be described with reference to FIG. 3 taking a Bi-CMOS device as an example.

First, an impurity concentration of 1 is formed on the surface of a low-concentration P-type single-crystal silicon substrate 301 having an impurity concentration of 10 ¹⁴ to 10 ¹⁵ atom / cm ^3.
N ⁺ buried layer of about × 10 ²¹ cm ^-3 and P ^{+ of} about 1 × 10 ⁺¹⁷ cm ^-3
After the buried layer 303 is formed by ion implantation, an n-type epitaxial layer 304 having a thickness of about 1 μm is formed using a normal epitaxial technique (FIG. 3.a).

Next, after a thermal oxide film 305 of about 500 ° is formed on the surface of the epitaxial layer 304, a resist 306 is patterned using a normal photolithography technique so that a region for forming a P-type well is formed, and then boron is ionized. Inject (Figure 3.b).

Next, after growing a nitride film 307 of about 2000 mm, the resist 308 is patterned so that the active region of the transistor remains, and the nitride film 30 is formed using a normal dry etching technique.
Remove 7 Here, in order to maintain element isolation resistance between the diffusion layer in the n-type well region, the bipolar, the graft base, and the n-type well, phosphorus (hereinafter referred to as GR phosphorus) is implanted into the entire surface and the n-type well region and the bipolar region Then, a channel stopper layer 309 is formed (FIG. 3.c).

Subsequently, the resist 31 is opened so that the P-type well region is opened.
By patterning 0, boron is implanted into the channel stopper region in the P-type well to form a channel stopper layer 311 also in the P-type well (FIG. 3.d).

Subsequently, after the resists 308 and 310 are stripped using a resist stripper using plasma, a thermal oxide film 312 (hereinafter, referred to as a field oxide film) of about 6000 ° is formed (FIG. 3.e).

Next, the resist 313 is patterned using photolithography so that the N-type well region is opened,
Phosphorus for forming n-type well (referred to as GPH injection)
When the forming the n-type well 314 by implanting boron is implanted in V _T control simultaneously (Figure 3.f).

After this step, a predetermined Bi-CMOS element is formed using a normal Bi-CMOS manufacturing method (FIG. 3.g).

[Problems to be solved by the invention]

In the conventional process, boron that forms the channel stopper layer is implanted before the field oxide film, so that boron is incorporated into the oxide film during field oxidation.
As shown in FIG. 1, the peak of boron distribution immediately after boron injection is greatly reduced. As a result, only about 10% of the boron implanted can be activated.

In order to obtain the isolation resistance of the P-well of 10 V or more, it is necessary to perform boron implantation at a high dose of about 5E13 cm ⁻² in view of the boron absorbed by the oxide film.
When boron is ion-implanted at a high dose of cm ^-2 or more,
There is a problem that many crystal defects occur near the surface of the silicon substrate, and the leakage current between the diffusion layers increases.

[Means for solving the problem]

In the method of manufacturing a semiconductor device according to the present invention, an n-type channel stopper layer is formed on the entire electrical isolation region before the step of forming a thermal oxide film acting as element isolation on the electrical isolation region on the semiconductor substrate. And a step of injecting boron for forming a p-type channel stopper layer into the silicon substrate via the thermal oxide film.

Example Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.

This embodiment is an example in which boron having a high energy and a channel stop is implanted into a P-type well region after field oxidation. In the conventional process, channel stop boron is implanted before field oxidation, so that nearly 90% of the implanted impurities are absorbed by the field oxide film. However, in the present invention, boron is implanted after field oxidation, so that the field oxide film has There is an effect that impurities are not absorbed and impurities to be implanted can be reduced.

This embodiment is the same as the conventional manufacturing method up to the step (3.c) of forming the channel stopper layer of the n-type well.
Next, after removing the resist 308, a thermal oxide film 1 of about 6000 mm
Form 07. Thereafter, the nitride film 307 covering the active region of the transistor is removed (FIG. 1.a).

Next, the resist 108 is patterned so that the P-type well region is opened, and boron is implanted at about 1E13 cm ² at an acceleration energy of about 250 keV (FIG. 1.b).

After this step, a predetermined Bi-CMOS element is formed again using a normal Bi-CMOS manufacturing step.

 FIG. 2 shows a longitudinal sectional view of the second embodiment.

In the second embodiment, as in the case of GR boron, GR phosphorus is implanted by using a mask after field oxidation, so that the dose of GR phosphorus and GR boron can be determined independently.

In the present embodiment, the process is the same as that of the conventional manufacturing method until the thermal oxide film 305 is formed at about 200 ° and then the nitride film 307 is formed at about 2000 ° and turning is performed so that the active region of the transistor remains.

Thereafter, the resist 308 is peeled off to form a thermal oxide film 206 of about 6000 °. Thereafter, the nitride film 307 is removed (FIG. 2.
a).

Next, a resist 207 is formed so that the P-type well region is opened.
After patterning, a channel stopper layer 208 is formed under the field oxide film 206 by implanting boron at about 1E13 cm ⁻² at an acceleration energy of about 250 keV.

Subsequently, after implanting gate boron at an acceleration energy of about 15 keV, the resist 207 is stripped. Then P
The resist 209 is patterned so that the mold well region remains, and about 6E12 cm ^{-2 of} phosphorus is implanted at an acceleration energy of about 500 keV. Thus, a channel stopper layer 210 is formed below the n-type well and the field oxide film 206 in the bipolar portion (FIG. 2.c).

After this step (FIG. 2.c), a predetermined Bi-CMOS device is completed using a conventional manufacturing method.

〔The invention's effect〕

As described above, according to the present invention, by implanting boron of the channel stopper after the field oxidation step, it is possible to prevent boron from being absorbed into the oxide film, and as a result, the dose of ion implantation can be reduced. .

FIG. 4 (b) shows the distribution of boron concentration under the field oxide film using the manufacturing method of the present invention. The dose of GR boron, which previously required about 5E10 ¹³ cm ^-2, can be reduced to about 1E10 ¹³ cm ^-2 .

Furthermore, in the present manufacturing method, since the impurity of the channel stopper is implanted through the thick oxide film, the stress applied to the silicon substrate at the time of implantation can be reduced, and the crystal defects generated at the time of implantation can be reduced. be able to.

If the present invention is applied to a manufacturing process of a Bi-CMOS device, a GR that counteracts the GR phosphorus injected into the P-type channel stopper region can be obtained.
The boron dose is not absorbed by the field oxide film, and n
The impurity concentration of the p-type and p-type channel stopper layers can be increased about five times as compared with the conventional one, and as a result, there is an effect that each element isolation region of the bipolar and CMOS regions can be reduced at the same time.

[Brief description of the drawings]

1 (a) and 1 (b) are longitudinal sectional views of a manufacturing method according to a first embodiment of the present invention, FIGS. 2 (a) to 2 (c) are longitudinal sectional views illustrating a manufacturing method according to a second embodiment of the present invention, 3 (a) to 3 (g) are diagrams for explaining a conventional technique, FIG. 4 (a) is a conventional boron concentration distribution diagram below a field oxide film, and FIG. 4 (b) is a diagram of the present invention. FIG. 3 is a boron concentration distribution diagram under a field oxide film. 101, 201, 301 ... silicon substrate, 102, 202, 302 ... N ⁺ buried layer, 103, 203, 303 ... P ⁺ buried layer, 104, 204, 304 ... n
-Type epitaxial layer, 105,205 ... P-type well, 106,21
0,309 ... n-type channel stopper layer, 107,206,305,312 ...
... thermal oxide film, 108, 207, 209, 306, 308, 310 ... resist, 1
09,208,311 ... P-type channel stopper layer, 307 ... Nitride film.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 21/76 H01L 27/06

Claims (1)

(57) [Claims] 1. A method for forming an n-type channel stopper layer over the entire area of an electrical isolation region before implanting a thermal oxide film acting as an element isolation in an electrical isolation region on a semiconductor substrate. A method for manufacturing a semiconductor device, comprising: a step of implanting boron for forming a p-type channel stopper layer through a thermal oxide film into a silicon substrate.