JPH0364946A - Formation of semiconductor element isolation - Google Patents

Abstract

PURPOSE:To make possible the formation of an element isolation of a small narrow-channel effect by a method wherein a selective ion-implantation process, by which the position of the peak of an impurity concentration becomes a specified position from the surface of a silicon substrate, and a process for oxidizing selectively the silicon substrate on said implanted part are provided. CONSTITUTION:An impurity is implanted using ions of an accelerating energy in a selective ion implantation process, by which the position of the peak of an impurity concentration becomes a position of 0.4 to 0.6mum from the surface of a substrate, and after a P-type impurity layer is formed, the substrate on this P-type impurity layer is selectively oxidized. A silicon nitride film 3a is selectively removed by dry etching using a resist film 4 formed by patterning as a mask and after a silicon nitride film 3b with a pattern transferred thereon is formed, boron ions 5 are implanted in 4X10<13>/cm<-2> in 200keV, for example, and a P-type impurity diffused layer 6a is formed. Then, the film 4 is removed and an oxide film 7 of about 600nm is formed on the opening parts of the film 3b, which is formed by patterning and consists of an oxidation resisting material, by selective oxidation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming semiconductor isolation.

BACKGROUND OF THE INVENTION In recent years, integrated circuit technology has developed in which a large number of functional elements are incorporated into a semiconductor substrate. A local oxidation method, the so-called LOCO8 method, is one means of element isolation technology for achieving high integration in such integrated circuits.

However, as devices become smaller, the LOCO8 method
It is becoming impossible to ignore the diffusion of impurities directly under the oxide film that serves as the separation layer due to heat during oxidation.

Below, we will discuss the fourth method of forming conventional semiconductor element isolation.
This will be explained using step-by-step cross-sectional views of FIGS. (a) to (d).

FIG. 4 (al to (dl), 11 is a p-type silicon substrate, 12 is a silicon oxide film, 13a, 13b and 13
c is a silicon nitride film, 14 is a resist film, 15 is a poron ion, 16a and 16b are p-type impurity diffusion layers, 17
1 is a silicon oxide film, 18 is a gate oxide film, and 19 is a gate polysilicon film.

First, as shown in FIG. 4(a), a p-type silicon substrate 1
1, a silicon oxide film 12 is grown to a thickness of 40 nm by thermal oxidation, and a silicon nitride film 13a is deposited thereon to a thickness of 150 nm using the CVD method. Subsequently, a resist 14 is applied, and a desired pattern of the resist film 14 is formed by exposure and development.

Next, as shown in FIG. 4(b), using the patterned resist film 14 as a mask, the silicon nitride film 13a is
After selectively removing the silicon nitride film 13b by dry etching and shaping the pattern-transferred silicon nitride film 13b, boron ions 1
5 at relatively low acceleration, e.g. 4 x 101 at 5QkeV
3/am-2 is implanted to form a p-type impurity diffusion layer 16a.

Next, as shown in FIG. 4 (C1), the resist film 14 is removed and the patterned oxidation-resistant silicon nitride film 1 is removed.
By selectively oxidizing the opening portion of 3b, approximately 600n
An oxide film 17 of m is formed. Through these steps, a semiconductor element isolation layer including the thick oxide film 17 and the p-type impurity diffusion layer 16b is formed.

Thereafter, as shown in FIG. 4 Td), the silicon nitride film 13c is removed with phosphoric acid, and a mixed solution of ammonium fluoride and hydrofluoric acid (
After removing the oxide film in the element region by etching at a ratio of 20:1) for 1 minute, a 10 nm gate oxide film 18 is formed, and then a gate polysilicon film 19 with a desired pattern is formed, forming an MO8 type semiconductor element. form.

Problems to be Solved by the Invention However, the p-type impurity diffusion layer formed in the element isolation region is significantly diffused by high-temperature heat treatments such as selective oxidation, gate oxidation, and vapor phase diffusion of phosphorus into gate polysilicon. There is a problem in that the impurity concentration on the substrate surface of the device region increases, and in devices with narrow gate widths, a narrow channel effect occurs in which the threshold voltage increases.

Means for Solving the Problems In order to solve the above problems, the present invention implants ions with acceleration energy such that the impurity concentration peak is 0.4 μm to 0.6 μm below the substrate surface, and implants the p-type impurity layer. After forming the p-type impurity layer, the substrate on the p-type impurity layer is selectively oxidized.

Effect: By using such a method, even if impurity diffusion occurs due to high-temperature heat treatment, there is little change in the impurity concentration on the substrate surface in the element region, and it is possible to form element isolation with a small narrow channel effect.

EXAMPLES Below, a method for forming a semiconductor element isolation according to the present invention will be described with reference to step-by-step sectional views of FIGS. 1(a) to (dl).

In FIG. 1 (al to Td), 1 is a p-type silicon substrate, 2 is a silicon oxide film, 3a, 3b and 3c are silicon nitride films, 4 is a resist film, 5 is a boron ion, 6a and 6b are p-type impurities Diffusion layer, 7, silicon oxide film, 8
9 is a gate oxide film, and 9 is a gate polysilicon film.

First, as shown in FIG. 1 (al), a p-type silicon substrate 1
A silicon oxide film 2 is grown to a thickness of 40 nm by thermal oxidation.
On top of that, a silicon nitride film 3a with a thickness of 150 mm is deposited using the CVD method.
nm deposited. Subsequently, a resist 4 is applied, and a desired pattern of the resist film 4 is formed by exposure and development.

Next, as shown in FIG. 1 (bl), using the patterned resist film 4 as a mask, the silicon nitride film 3a is selectively removed by dry etching to form a pattern-transferred silicon nitride film 3b. 5 is implanted at, for example, 200 keV in an amount of 4.times.10 I3/am-" to form a p-type impurity diffusion layer 6a.

Next, as shown in FIG. 1C, the resist film 4 is removed and the patterned silicon nitride film 3b of the oxidation-resistant material is removed.
An oxide film 7 of approximately 600 nm is formed by selective oxidation of the opening portion of the
form. Through these steps, a semiconductor element isolation layer including the thick oxide film 7 and the p-type impurity diffusion layer 6b is formed.

Thereafter, as shown in FIG. 1 1dl, the silicon nitride film 3C is removed with phosphoric acid, and a mixed solution of ammonium fluoride and hydrofluoric acid (2
After removing the oxide film in the element region by etching at a ratio of 0:1) for 1 minute, a gate oxide film 8 of 10 nm is formed, and then a gate polysilicon film 9 of a desired pattern is formed, and MO
An 8-type semiconductor element is formed.

FIG. 2 shows the impurity concentration distribution on the surface of the silicon substrate. It can be seen that the method of the present invention causes less p-type impurity to seep into the element region than the conventional method for forming element isolation.

FIG. 3 shows the narrow channel effect in terms of the relationship between gate width and threshold voltage. In the element isolation forming method of the present invention,
Compared to the conventional method, the narrow channel effect is significantly reduced.

Further, the present invention is an excellent element isolation formation method that can easily handle changes in heat treatment conditions because the peak position of the impurity concentration can be changed accurately depending on the implantation energy.

Further, in the embodiment, an n-channel MOS type semiconductor device has been described, but if phosphorus ions are used, the present invention can also be applied to a p-channel MOS type semiconductor device.

Effects of the Invention According to the present invention, the p-type impurity concentration is implanted with acceleration energy that makes the peak concentration 0.4 μm to 0.6 μm from the substrate surface, so that the impurity concentration in the element region due to diffusion during high-temperature heat treatment is reduced. In other words, there is little change in the amount of the same impurity seeped out.

[Brief explanation of drawings]

FIG. 1 (al to (dl) are cross-sectional views in the order of steps for semiconductor element isolation formation in one embodiment of the present invention, FIG. 2 is a graph showing the impurity concentration distribution on the substrate surface in the isolation region and the element region, and FIG. 3 is A graph showing the narrow channel effect, and FIG. 4 are cross-sectional views in the order of steps of conventional semiconductor element isolation formation. 1...p-type silicon substrate, 2... silicon oxide film, 3a, 3b and 3c...Silicon nitride film, 4...Resist film, 5...
Poron ions, 6a and 6b...p-type impurity diffusion layer, 7...silicon oxide film, 8...
・Gate oxide film, 9... Gate polysilicon film, 11... P-type silicon substrate, 12...
・Silicon oxide film, 13a, 13b and 13c...
...Silicon nitride film, 14...Resist film,
15... Poron ion, 16a and 16b.
...p-type impurity diffusion layer, 17 ... silicon oxide film, 18 ... gate oxide film, 19 ...
...Gate polysilicon film.

Claims (1)

[Claims] The peak position of impurity concentration is 0.4 from the silicon substrate surface.
A method for forming semiconductor element isolation comprising a selective ion implantation step at a position of .mu.m to 0.6 .mu.m and a selective oxidation step of the silicon substrate on the same implantation part.